Blackfin: unify core MMRs
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
aa79cbbf27
commit
9615398dc2
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@ -986,18 +986,6 @@
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#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
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#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
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#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
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#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
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#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
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#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
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#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
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#define bfin_read_TBUF() bfin_readPTR(TBUF)
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#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
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#define bfin_read_PFCTL() bfin_read32(PFCTL)
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#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
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#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
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#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
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#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
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#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
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#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
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#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
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#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
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@ -497,12 +497,6 @@
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#define NFC_CMD 0xFFC03744 /* NAND Command Register */
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#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */
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#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */
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#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
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#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
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#define TBUF 0xFFE06100 /* Trace Buffer */
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#define PFCTL 0xFFE08000
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#define PFCNTR0 0xFFE08100
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#define PFCNTR1 0xFFE08104
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#define DMA_TC_CNT 0xFFC00B0C
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#define DMA_TC_PER 0xFFC00B10
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@ -26,207 +26,5 @@
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#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
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#define bfin_read_SYSCR() bfin_read16(SYSCR)
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#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
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#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
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#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
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#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
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#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
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#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
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#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
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#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
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#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
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#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
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#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
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#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
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#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
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#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
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#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
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#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
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#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
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#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
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#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
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#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
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#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
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#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
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#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
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#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
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#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
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#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
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#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
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#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
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#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
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#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
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#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
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#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
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#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
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#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
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#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
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#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
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#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
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#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
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#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
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#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
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#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
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#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
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#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
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#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
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#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
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#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
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#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
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#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
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#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
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#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
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#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
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#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
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#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
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#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
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#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
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#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
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#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
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#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
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#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
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#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
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#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
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#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
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#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
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#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
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#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
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#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
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#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
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#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
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#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
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#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
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#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
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#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
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#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
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#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
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#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
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#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
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#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
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#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
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#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
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#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
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#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
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#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
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#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
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#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
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#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
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#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
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#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
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#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
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#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
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#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
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#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
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#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
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#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
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#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
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#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
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#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
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#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
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#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
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#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
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#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
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#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
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#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
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#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
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#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
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#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
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#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
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#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
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#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
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#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
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#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
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#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
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#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
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#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
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#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
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#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
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#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
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#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
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#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
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#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
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#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
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#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
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#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
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#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
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#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
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#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
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#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
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#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
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#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
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#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
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#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
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#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
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#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
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#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
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#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
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#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
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#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
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#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
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#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
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#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
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#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
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#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
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#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
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#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
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#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
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#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
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#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
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#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
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#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
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#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
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#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
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#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
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#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
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#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
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#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
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#define bfin_read_EVT0() bfin_readPTR(EVT0)
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#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
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#define bfin_read_EVT1() bfin_readPTR(EVT1)
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#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
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#define bfin_read_EVT2() bfin_readPTR(EVT2)
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#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
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#define bfin_read_EVT3() bfin_readPTR(EVT3)
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#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
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#define bfin_read_EVT4() bfin_readPTR(EVT4)
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#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
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#define bfin_read_EVT5() bfin_readPTR(EVT5)
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#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
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#define bfin_read_EVT6() bfin_readPTR(EVT6)
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#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
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#define bfin_read_EVT7() bfin_readPTR(EVT7)
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#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
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#define bfin_read_EVT8() bfin_readPTR(EVT8)
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#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
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#define bfin_read_EVT9() bfin_readPTR(EVT9)
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#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
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#define bfin_read_EVT10() bfin_readPTR(EVT10)
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#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
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#define bfin_read_EVT11() bfin_readPTR(EVT11)
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#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
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#define bfin_read_EVT12() bfin_readPTR(EVT12)
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#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
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#define bfin_read_EVT13() bfin_readPTR(EVT13)
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#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
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#define bfin_read_EVT14() bfin_readPTR(EVT14)
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#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
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#define bfin_read_EVT15() bfin_readPTR(EVT15)
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#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
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#define bfin_read_ILAT() bfin_read32(ILAT)
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#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
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#define bfin_read_IMASK() bfin_read32(IMASK)
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#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
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#define bfin_read_IPEND() bfin_read32(IPEND)
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#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
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#define bfin_read_IPRIO() bfin_read32(IPRIO)
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||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
|
||||
|
|
|
|||
|
|
@ -18,106 +18,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
|
||||
|
|
|
|||
|
|
@ -26,208 +26,6 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
|
||||
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
||||
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
|
||||
|
|
|
|||
|
|
@ -18,107 +18,6 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define USB_FADDR 0xFFC03800 /* Function address register */
|
||||
#define USB_POWER 0xFFC03804 /* Power management register */
|
||||
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
||||
|
|
|
|||
|
|
@ -26,208 +26,6 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
|
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
||||
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
|
||||
|
|
|
|||
|
|
@ -18,107 +18,6 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
||||
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
|
||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__
|
||||
#define __BFIN_CDEF_ADSP_EDN_BF534_extended__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_cdef.h"
|
||||
|
||||
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
|
||||
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
|
||||
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
|
||||
|
|
@ -1612,222 +1614,8 @@
|
|||
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
|
||||
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
|
||||
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
#define bfin_read_PFCTL() bfin_read32(PFCTL)
|
||||
#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
|
||||
#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
|
||||
#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
|
||||
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
|
||||
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
|
||||
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
|
||||
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
|
||||
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__
|
||||
#define __BFIN_DEF_ADSP_EDN_BF534_extended__
|
||||
|
||||
#include "../mach-common/ADSP-EDN-core_def.h"
|
||||
|
||||
#define PLL_CTL 0xFFC00000 /* PLL Control Register */
|
||||
#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
|
||||
#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
|
||||
|
|
@ -810,114 +812,7 @@
|
|||
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
|
||||
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
|
||||
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define CHIPID 0xFFC00014
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
#define PFCTL 0xFFE08000
|
||||
#define PFCNTR0 0xFFE08100
|
||||
#define PFCNTR1 0xFFE08104
|
||||
#define DMA_TC_CNT 0xFFC00B0C
|
||||
#define DMA_TC_PER 0xFFC00B10
|
||||
|
||||
|
|
|
|||
|
|
@ -1308,14 +1308,6 @@
|
|||
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
|
||||
#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
|
||||
#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
||||
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
||||
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
||||
|
|
|
|||
|
|
@ -657,10 +657,6 @@
|
|||
#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
|
||||
#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
|
||||
#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
|
|
@ -1382,14 +1382,6 @@
|
|||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
||||
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
||||
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
||||
|
|
|
|||
|
|
@ -694,10 +694,6 @@
|
|||
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
|
|
@ -1382,14 +1382,6 @@
|
|||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
||||
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
||||
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
||||
|
|
|
|||
|
|
@ -694,10 +694,6 @@
|
|||
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
|
|
@ -1382,14 +1382,6 @@
|
|||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
||||
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
||||
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
||||
|
|
|
|||
|
|
@ -694,10 +694,6 @@
|
|||
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
|
|
@ -1382,14 +1382,6 @@
|
|||
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
|
||||
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
|
||||
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
|
||||
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
|
||||
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
|
||||
|
|
|
|||
|
|
@ -694,10 +694,6 @@
|
|||
#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
|
||||
#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
|
||||
#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
|
|
@ -16,205 +16,5 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
|
||||
|
|
|
|||
|
|
@ -13,105 +13,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
|
||||
|
|
|
|||
|
|
@ -16,205 +16,5 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
|
||||
|
|
|
|||
|
|
@ -13,105 +13,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
|
||||
|
|
|
|||
|
|
@ -16,205 +16,5 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
|
||||
|
|
|
|||
|
|
@ -13,105 +13,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
|
||||
|
|
|
|||
|
|
@ -16,205 +16,5 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
|
||||
|
|
|
|||
|
|
@ -13,105 +13,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
|
||||
|
|
|
|||
|
|
@ -16,205 +16,5 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
|
||||
|
|
|
|||
|
|
@ -13,105 +13,5 @@
|
|||
#define CHIPID 0xFFC00014
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
|
||||
|
|
|
|||
|
|
@ -10,160 +10,6 @@
|
|||
|
||||
#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
|
||||
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
|
||||
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
|
||||
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
|
||||
#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
|
||||
|
|
@ -252,24 +98,6 @@
|
|||
#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT, val)
|
||||
#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
|
||||
#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_read32(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_write32(TBUF, val)
|
||||
#define bfin_read_PFCTL() bfin_read32(PFCTL)
|
||||
#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
|
||||
#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
|
||||
#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
|
||||
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
|
||||
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
|
||||
#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
|
||||
#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
|
||||
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
|
||||
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
|
||||
#define bfin_read_UART_THR() bfin_read16(UART_THR)
|
||||
#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
|
||||
#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
|
||||
|
|
|
|||
|
|
@ -10,83 +10,6 @@
|
|||
|
||||
#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
|
||||
|
||||
#define SRAM_BASE_ADDR 0xFFE00000
|
||||
#define DMEM_CONTROL 0xFFE00004
|
||||
#define DCPLB_STATUS 0xFFE00008
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C
|
||||
#define DCPLB_ADDR0 0xFFE00100
|
||||
#define DCPLB_ADDR1 0xFFE00104
|
||||
#define DCPLB_ADDR2 0xFFE00108
|
||||
#define DCPLB_ADDR3 0xFFE0010C
|
||||
#define DCPLB_ADDR4 0xFFE00110
|
||||
#define DCPLB_ADDR5 0xFFE00114
|
||||
#define DCPLB_ADDR6 0xFFE00118
|
||||
#define DCPLB_ADDR7 0xFFE0011C
|
||||
#define DCPLB_ADDR8 0xFFE00120
|
||||
#define DCPLB_ADDR9 0xFFE00124
|
||||
#define DCPLB_ADDR10 0xFFE00128
|
||||
#define DCPLB_ADDR11 0xFFE0012C
|
||||
#define DCPLB_ADDR12 0xFFE00130
|
||||
#define DCPLB_ADDR13 0xFFE00134
|
||||
#define DCPLB_ADDR14 0xFFE00138
|
||||
#define DCPLB_ADDR15 0xFFE0013C
|
||||
#define DCPLB_DATA0 0xFFE00200
|
||||
#define DCPLB_DATA1 0xFFE00204
|
||||
#define DCPLB_DATA2 0xFFE00208
|
||||
#define DCPLB_DATA3 0xFFE0020C
|
||||
#define DCPLB_DATA4 0xFFE00210
|
||||
#define DCPLB_DATA5 0xFFE00214
|
||||
#define DCPLB_DATA6 0xFFE00218
|
||||
#define DCPLB_DATA7 0xFFE0021C
|
||||
#define DCPLB_DATA8 0xFFE00220
|
||||
#define DCPLB_DATA9 0xFFE00224
|
||||
#define DCPLB_DATA10 0xFFE00228
|
||||
#define DCPLB_DATA11 0xFFE0022C
|
||||
#define DCPLB_DATA12 0xFFE00230
|
||||
#define DCPLB_DATA13 0xFFE00234
|
||||
#define DCPLB_DATA14 0xFFE00238
|
||||
#define DCPLB_DATA15 0xFFE0023C
|
||||
#define DTEST_COMMAND 0xFFE00300
|
||||
#define DTEST_DATA0 0xFFE00400
|
||||
#define DTEST_DATA1 0xFFE00404
|
||||
#define IMEM_CONTROL 0xFFE01004
|
||||
#define ICPLB_STATUS 0xFFE01008
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C
|
||||
#define ICPLB_ADDR0 0xFFE01100
|
||||
#define ICPLB_ADDR1 0xFFE01104
|
||||
#define ICPLB_ADDR2 0xFFE01108
|
||||
#define ICPLB_ADDR3 0xFFE0110C
|
||||
#define ICPLB_ADDR4 0xFFE01110
|
||||
#define ICPLB_ADDR5 0xFFE01114
|
||||
#define ICPLB_ADDR6 0xFFE01118
|
||||
#define ICPLB_ADDR7 0xFFE0111C
|
||||
#define ICPLB_ADDR8 0xFFE01120
|
||||
#define ICPLB_ADDR9 0xFFE01124
|
||||
#define ICPLB_ADDR10 0xFFE01128
|
||||
#define ICPLB_ADDR11 0xFFE0112C
|
||||
#define ICPLB_ADDR12 0xFFE01130
|
||||
#define ICPLB_ADDR13 0xFFE01134
|
||||
#define ICPLB_ADDR14 0xFFE01138
|
||||
#define ICPLB_ADDR15 0xFFE0113C
|
||||
#define ICPLB_DATA0 0xFFE01200
|
||||
#define ICPLB_DATA1 0xFFE01204
|
||||
#define ICPLB_DATA2 0xFFE01208
|
||||
#define ICPLB_DATA3 0xFFE0120C
|
||||
#define ICPLB_DATA4 0xFFE01210
|
||||
#define ICPLB_DATA5 0xFFE01214
|
||||
#define ICPLB_DATA6 0xFFE01218
|
||||
#define ICPLB_DATA7 0xFFE0121C
|
||||
#define ICPLB_DATA8 0xFFE01220
|
||||
#define ICPLB_DATA9 0xFFE01224
|
||||
#define ICPLB_DATA10 0xFFE01228
|
||||
#define ICPLB_DATA11 0xFFE0122C
|
||||
#define ICPLB_DATA12 0xFFE01230
|
||||
#define ICPLB_DATA13 0xFFE01234
|
||||
#define ICPLB_DATA14 0xFFE01238
|
||||
#define ICPLB_DATA15 0xFFE0123C
|
||||
#define ITEST_COMMAND 0xFFE01300
|
||||
#define ITEST_DATA0 0xFFE01400
|
||||
#define ITEST_DATA1 0xFFE01404
|
||||
#define SICA_SWRST 0xFFC00100
|
||||
#define SICA_SYSCR 0xFFC00104
|
||||
#define SICA_RVECT 0xFFC00108
|
||||
|
|
@ -131,15 +54,6 @@
|
|||
#define PPI1_DELAY 0xFFC0130C
|
||||
#define PPI1_COUNT 0xFFC01308
|
||||
#define PPI1_FRAME 0xFFC01310
|
||||
#define TBUFCTL 0xFFE06000
|
||||
#define TBUFSTAT 0xFFE06004
|
||||
#define TBUF 0xFFE06100
|
||||
#define PFCTL 0xFFE08000
|
||||
#define PFCNTR0 0xFFE08100
|
||||
#define PFCNTR1 0xFFE08104
|
||||
#define SRAM_BASE_ADDR_CORE_A 0xFFE00000
|
||||
#define SRAM_BASE_ADDR_CORE_B 0xFFE00000
|
||||
#define EVT_OVERRIDE 0xFFE02100
|
||||
#define UART_THR 0xFFC00400
|
||||
#define UART_RBR 0xFFC00400
|
||||
#define UART_DLL 0xFFC00400
|
||||
|
|
|
|||
|
|
@ -1276,53 +1276,5 @@
|
|||
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
|
||||
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
|
||||
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */
|
||||
|
|
|
|||
|
|
@ -642,29 +642,5 @@
|
|||
#define SPORT1_MRCS1 0xFFC00954
|
||||
#define SPORT1_MRCS2 0xFFC00958
|
||||
#define SPORT1_MRCS3 0xFFC0095C
|
||||
#define EVT0 0xFFE02000
|
||||
#define EVT1 0xFFE02004
|
||||
#define EVT2 0xFFE02008
|
||||
#define EVT3 0xFFE0200C
|
||||
#define EVT4 0xFFE02010
|
||||
#define EVT5 0xFFE02014
|
||||
#define EVT6 0xFFE02018
|
||||
#define EVT7 0xFFE0201C
|
||||
#define EVT8 0xFFE02020
|
||||
#define EVT9 0xFFE02024
|
||||
#define EVT10 0xFFE02028
|
||||
#define EVT11 0xFFE0202C
|
||||
#define EVT12 0xFFE02030
|
||||
#define EVT13 0xFFE02034
|
||||
#define EVT14 0xFFE02038
|
||||
#define EVT15 0xFFE0203C
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000
|
||||
#define TPERIOD 0xFFE03004
|
||||
#define TSCALE 0xFFE03008
|
||||
#define TCOUNT 0xFFE0300C
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,227 @@
|
|||
#ifndef __BFIN_CDEF_ADSP_EDN_core__
|
||||
#define __BFIN_CDEF_ADSP_EDN_core__
|
||||
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
|
||||
#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
|
||||
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
|
||||
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
|
||||
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
|
||||
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
|
||||
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
|
||||
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
|
||||
#define bfin_read_TBUF() bfin_readPTR(TBUF)
|
||||
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
|
||||
|
||||
#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
|
||||
#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val)
|
||||
#define bfin_read_WPIA0() bfin_readPTR(WPIA0)
|
||||
|
|
@ -44,9 +265,12 @@
|
|||
#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val)
|
||||
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
|
||||
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
|
||||
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
|
||||
|
||||
#define bfin_read_PFCTL() bfin_read32(PFCTL)
|
||||
#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
|
||||
#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
|
||||
#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
|
||||
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
|
||||
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,120 @@
|
|||
#ifndef __BFIN_DEF_ADSP_EDN_core__
|
||||
#define __BFIN_DEF_ADSP_EDN_core__
|
||||
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_FAULT_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_FAULT_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
|
||||
#define EVT_OVERRIDE 0xFFE02100
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
|
||||
#define DSPID 0xFFE05000
|
||||
#define DBGSTAT 0xFFE05008
|
||||
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
#define WPIACTL 0xFFE07000
|
||||
#define WPIA0 0xFFE07040
|
||||
#define WPIA1 0xFFE07044
|
||||
|
|
@ -25,7 +139,9 @@
|
|||
#define WPDACNT0 0xFFE07180
|
||||
#define WPDACNT1 0xFFE07184
|
||||
#define WPSTAT 0xFFE07200
|
||||
#define DSPID 0xFFE05000
|
||||
#define DBGSTAT 0xFFE05008
|
||||
|
||||
#define PFCTL 0xFFE08000
|
||||
#define PFCNTR0 0xFFE08100
|
||||
#define PFCNTR1 0xFFE08104
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_EDN_core__ */
|
||||
|
|
|
|||
|
|
@ -6,208 +6,6 @@
|
|||
#ifndef __BFIN_CDEF_ADSP_EDN_extended__
|
||||
#define __BFIN_CDEF_ADSP_EDN_extended__
|
||||
|
||||
#define bfin_read_ILAT() bfin_read32(ILAT)
|
||||
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
|
||||
#define bfin_read_IMASK() bfin_read32(IMASK)
|
||||
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
||||
#define bfin_read_IPEND() bfin_read32(IPEND)
|
||||
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define bfin_read_TCNTL() bfin_read32(TCNTL)
|
||||
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
|
||||
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
|
||||
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
|
||||
#define bfin_read_TSCALE() bfin_read32(TSCALE)
|
||||
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
|
||||
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
|
||||
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
|
||||
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
|
||||
#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
|
||||
#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
|
||||
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
|
||||
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
|
||||
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
|
||||
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
|
||||
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
|
||||
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
|
||||
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
|
||||
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
|
||||
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
|
||||
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
|
||||
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
|
||||
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
|
||||
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
|
||||
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
|
||||
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
|
||||
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
|
||||
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
|
||||
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
|
||||
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
|
||||
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
|
||||
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
|
||||
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
|
||||
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
|
||||
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
|
||||
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
|
||||
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
|
||||
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
|
||||
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
|
||||
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
|
||||
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
|
||||
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
|
||||
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
|
||||
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
|
||||
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
|
||||
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
|
||||
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
|
||||
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
|
||||
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
|
||||
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
|
||||
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
|
||||
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
|
||||
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
|
||||
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
|
||||
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
|
||||
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
|
||||
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
|
||||
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
|
||||
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
|
||||
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
|
||||
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
|
||||
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
|
||||
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
|
||||
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
|
||||
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
|
||||
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
|
||||
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
|
||||
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
|
||||
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
|
||||
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
|
||||
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
|
||||
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
|
||||
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
|
||||
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
|
||||
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
|
||||
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
|
||||
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
|
||||
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
|
||||
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
|
||||
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
|
||||
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
|
||||
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
|
||||
#define bfin_read_EVT0() bfin_readPTR(EVT0)
|
||||
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
|
||||
#define bfin_read_EVT1() bfin_readPTR(EVT1)
|
||||
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
|
||||
#define bfin_read_EVT2() bfin_readPTR(EVT2)
|
||||
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
|
||||
#define bfin_read_EVT3() bfin_readPTR(EVT3)
|
||||
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
|
||||
#define bfin_read_EVT4() bfin_readPTR(EVT4)
|
||||
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
|
||||
#define bfin_read_EVT5() bfin_readPTR(EVT5)
|
||||
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
|
||||
#define bfin_read_EVT6() bfin_readPTR(EVT6)
|
||||
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
|
||||
#define bfin_read_EVT7() bfin_readPTR(EVT7)
|
||||
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
|
||||
#define bfin_read_EVT8() bfin_readPTR(EVT8)
|
||||
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
|
||||
#define bfin_read_EVT9() bfin_readPTR(EVT9)
|
||||
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
|
||||
#define bfin_read_EVT10() bfin_readPTR(EVT10)
|
||||
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
|
||||
#define bfin_read_EVT11() bfin_readPTR(EVT11)
|
||||
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
|
||||
#define bfin_read_EVT12() bfin_readPTR(EVT12)
|
||||
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
|
||||
#define bfin_read_EVT13() bfin_readPTR(EVT13)
|
||||
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
|
||||
#define bfin_read_EVT14() bfin_readPTR(EVT14)
|
||||
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
|
||||
#define bfin_read_EVT15() bfin_readPTR(EVT15)
|
||||
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
|
||||
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
|
||||
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
|
||||
#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS)
|
||||
#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
|
||||
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
|
||||
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
|
||||
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
|
||||
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
|
||||
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
|
||||
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
|
||||
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
|
||||
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
|
||||
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
|
||||
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
|
||||
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
|
||||
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
|
||||
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
|
||||
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
|
||||
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
|
||||
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
|
||||
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
|
||||
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
|
||||
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
|
||||
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
|
||||
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
|
||||
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
|
||||
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
|
||||
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
|
||||
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
|
||||
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
|
||||
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
|
||||
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
|
||||
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
|
||||
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
|
||||
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
|
||||
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
|
||||
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
|
||||
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
|
||||
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
|
||||
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
|
||||
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
|
||||
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
|
||||
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
|
||||
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
|
||||
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
|
||||
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
|
||||
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
|
||||
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
|
||||
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
|
||||
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
|
||||
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
|
||||
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
|
||||
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
|
||||
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
|
||||
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
|
||||
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
|
||||
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
|
||||
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
|
||||
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
|
||||
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
|
||||
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
|
||||
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
|
||||
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
|
||||
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
|
||||
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
|
||||
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
|
||||
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
|
||||
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
|
||||
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
|
||||
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
|
||||
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
|
||||
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
|
||||
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
|
||||
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
|
||||
#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
|
||||
#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D)
|
||||
|
|
@ -604,8 +402,6 @@
|
|||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define bfin_read_SYSCR() bfin_read16(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
|
||||
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
|
||||
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
|
|
|
|||
|
|
@ -6,107 +6,6 @@
|
|||
#ifndef __BFIN_DEF_ADSP_EDN_extended__
|
||||
#define __BFIN_DEF_ADSP_EDN_extended__
|
||||
|
||||
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
|
||||
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
|
||||
#define DCPLB_FAULT_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */
|
||||
#define DCPLB_FAULT_ADDR 0xFFE0000C
|
||||
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
|
||||
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
|
||||
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
|
||||
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
|
||||
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
|
||||
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
|
||||
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
|
||||
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
|
||||
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
|
||||
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
|
||||
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
|
||||
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
|
||||
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
|
||||
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
|
||||
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
|
||||
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
|
||||
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
|
||||
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
|
||||
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
|
||||
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
|
||||
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
|
||||
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
|
||||
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
|
||||
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
|
||||
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
|
||||
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
|
||||
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
|
||||
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
|
||||
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
|
||||
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
|
||||
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
|
||||
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
|
||||
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
|
||||
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
|
||||
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
|
||||
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
|
||||
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
|
||||
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
|
||||
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
|
||||
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
|
||||
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
|
||||
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
|
||||
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
|
||||
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
|
||||
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
|
||||
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
|
||||
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
|
||||
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
|
||||
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
|
||||
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
|
||||
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
|
||||
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
|
||||
#define ICPLB_FAULT_STATUS 0xFFE01008
|
||||
#define ICPLB_FAULT_ADDR 0xFFE0100C
|
||||
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
|
||||
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
|
||||
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
|
||||
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
|
||||
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
|
||||
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
|
||||
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
|
||||
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
|
||||
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
|
||||
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
|
||||
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
|
||||
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
|
||||
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
|
||||
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
|
||||
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
|
||||
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
|
||||
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
|
||||
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
|
||||
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
|
||||
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
|
||||
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
|
||||
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
|
||||
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
|
||||
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
|
||||
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
|
||||
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
|
||||
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
|
||||
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
|
||||
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
|
||||
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
|
||||
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
|
||||
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
|
||||
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
|
||||
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
|
||||
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
|
||||
#define MDMAFLX0_DMACNFG_D 0xFFC00E08
|
||||
#define MDMAFLX0_XCOUNT_D 0xFFC00E10
|
||||
#define MDMAFLX0_XMODIFY_D 0xFFC00E14
|
||||
|
|
@ -305,14 +204,7 @@
|
|||
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define EVT_OVERRIDE 0xFFE02100
|
||||
#define CHIPID 0xFFC00014
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
#define PFCTL 0xFFE08000
|
||||
#define PFCNTR0 0xFFE08100
|
||||
#define PFCNTR1 0xFFE08104
|
||||
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
|
||||
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
|
||||
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
|
||||
|
|
|
|||
Loading…
Reference in New Issue