Remove AmigaOneG3SE board

The AmigaOneG3SE board has been orphaned or a very long time, and
broken for more than 12 releases resp. more than 3 years.  As nobody
seems to be interested any more in this stuff we may as well ged rid
of it, especially as it clutters many areas of the code so it is a
continuous pain for all kinds of ongoing work.

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2010-06-13 18:28:54 +02:00
parent ee80fa7b6e
commit 953b7e6291
51 changed files with 15 additions and 8868 deletions

View File

@ -49,11 +49,6 @@
#include <fdt_support.h>
#endif
#ifdef CONFIG_AMIGAONEG3SE
#include "../board/MAI/AmigaOneG3SE/via686.h"
#include "../board/MAI/AmigaOneG3SE/memio.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
cpu_t
@ -277,7 +272,7 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
*/
#if defined(CONFIG_AMIGAONEG3SE) || !defined(CONFIG_SYS_BUS_CLK)
#ifndef CONFIG_SYS_BUS_CLK
#define CONFIG_SYS_BUS_CLK gd->bus_clk
#endif

View File

@ -34,20 +34,19 @@
int interrupt_init_cpu (unsigned *decrementer_count)
{
#if defined(DEBUG) && !defined(CONFIG_AMIGAONEG3SE)
printf("interrupt_init: GT main cause reg: %08x:%08x\n",
debug("interrupt_init: GT main cause reg: %08x:%08x\n",
GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER),
GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER));
printf("interrupt_init: ethernet cause regs: %08x %08x %08x\n",
debug("interrupt_init: ethernet cause regs: %08x %08x %08x\n",
GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER),
GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER),
GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER));
printf("interrupt_init: ethernet mask regs: %08x %08x %08x\n",
debug("interrupt_init: ethernet mask regs: %08x %08x %08x\n",
GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER),
GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER),
GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER));
puts("interrupt_init: setting decrementer_count\n");
#endif
debug("interrupt_init: setting decrementer_count\n");
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
return (0);

View File

@ -25,10 +25,6 @@
#include <74xx_7xx.h>
#include <asm/processor.h>
#ifdef CONFIG_AMIGAONEG3SE
#include "../board/MAI/AmigaOneG3SE/via686.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long get_board_bus_clk (void);

View File

@ -745,9 +745,8 @@ in_ram:
bne 5b
6:
mr r3, r10 /* Destination Address */
#if defined(CONFIG_AMIGAONEG3SE) || \
defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460) || \
#if defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460) || \
defined(CONFIG_CPCI750) || \
defined(CONFIG_PPMC7XX) || \
defined(CONFIG_P3Mx)

View File

@ -37,20 +37,12 @@
#include <kgdb.h>
#include <asm/processor.h>
#ifdef CONFIG_AMIGAONEG3SE
DECLARE_GLOBAL_DATA_PTR;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
#ifdef CONFIG_AMIGAONEG3SE
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
#else
#define END_OF_MEM 0x02000000
#endif
/*
* Trap & Exception support

View File

@ -1,122 +0,0 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <netdev.h>
#include "articiaS.h"
#include "memio.h"
#include "via686.h"
__asm__(" .globl send_kb \n "
"send_kb: \n "
" lis r9, 0xfe00 \n "
" \n "
" li r4, 0x10 # retries \n "
" mtctr r4 \n "
" \n "
"idle: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x02 \n "
" bne idle \n "
"ready: \n "
" stb r3, 0x60(r9) \n "
" \n "
"check: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x01 \n "
" beq check \n "
" \n "
" lbz r4, 0x60(r9) \n "
" cmpwi r4, 0xfa \n "
" beq done \n "
" bdnz idle \n "
" li r3, 0 \n "
" blr \n "
"done: \n "
" li r3, 1 \n "
" blr \n "
".globl test_kb \n "
"test_kb: \n "
" mflr r10 \n "
" li r3, 0xed \n "
" bl send_kb \n "
" li r3, 0x01 \n "
" bl send_kb \n "
" mtlr r10 \n "
" blr \n "
);
int checkboard (void)
{
printf ("Board: AmigaOneG3SE\n");
return 0;
}
phys_size_t initdram (int board_type)
{
return articiaS_ram_init ();
}
void after_reloc (ulong dest_addr, gd_t *gd)
{
board_init_r (gd, dest_addr);
}
int misc_init_r (void)
{
extern pci_dev_t video_dev;
extern void drv_video_init (void);
if (video_dev != ~0)
drv_video_init ();
return (0);
}
void pci_init_board (void)
{
#ifndef CONFIG_RAMBOOT
articiaS_pci_init ();
#endif
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_3COM)
eth_3com_initialize(bis);
#endif
return 0;
}

View File

@ -1,63 +0,0 @@
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../menu)
$(shell mkdir -p $(obj)../bios_emulator)
endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
via686.o i8259.o ../bios_emulator/x86interface.o \
../bios_emulator/bios.o ../bios_emulator/glue.o \
interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \
../menu/cmd_menu.o cmd_boota.o nvram.o
SOBJS = board_asm_init.o memio.o
EMUDIR = ../bios_emulator/scitech/src/x86emu/
EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
$(EMUDIR)ops.o $(EMUDIR)sys.o
EMUSRC = $(EMUOBJ:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
EMUOBJ := $(addprefix $(obj),$(EMUOBJ))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(EMUSRC)
make $(obj)libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
-rm $(LIB)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(EMUOBJ)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

View File

@ -1,704 +0,0 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include "memio.h"
#include "articiaS.h"
#include "smbus.h"
#include "via686.h"
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
struct dimm_bank {
uint8 used; /* Bank is populated */
uint32 rows; /* Number of row addresses */
uint32 columns; /* Number of column addresses */
uint8 registered; /* SIMM is registered */
uint8 ecc; /* SIMM has ecc */
uint8 burst_len; /* Supported burst lengths */
uint32 cas_lat; /* Supported CAS latencies */
uint32 cas_used; /* CAS to use (not set by user) */
uint32 trcd; /* RAS to CAS latency */
uint32 trp; /* Precharge latency */
uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */
uint32 tclk_2hi; /* SDRAM second highest CAS latency */
uint32 size; /* Size of bank in bytes */
uint8 auto_refresh; /* Module supports auto refresh */
uint32 refresh_time; /* Refresh time (in ns) */
};
/*
** Based in part on the evb64260 code
*/
/*
* translate ns.ns/10 coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short NS10to10PS (unsigned char spd_byte)
{
unsigned short ns, ns10;
/* isolate upper nibble */
ns = (spd_byte >> 4) & 0x0F;
/* isolate lower nibble */
ns10 = (spd_byte & 0x0F);
return (ns * 100 + ns10 * 10);
}
/*
* translate ns coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short NSto10PS (unsigned char spd_byte)
{
return (spd_byte * 100);
}
long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
{
int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
uint32 busclock = gd->bus_clk;
uint32 memclock = busclock;
uint32 tmemclock = 1000000000 / (memclock / 100);
uint32 datawidth;
if (sm_get_data (rom, dimm_address) == 0) {
/* Nothing in slot, make both banks empty */
debug ("Slot %d: vacant\n", dimmNum);
banks[0].used = 0;
banks[1].used = 0;
return 0;
}
if (rom[2] != 0x04) {
debug ("Slot %d: No SDRAM\n", dimmNum);
banks[0].used = 0;
banks[1].used = 0;
return 0;
}
/* Determine number of banks/rows */
if (rom[5] == 1) {
banks[0].used = 1;
banks[1].used = 0;
} else {
banks[0].used = 1;
banks[1].used = 1;
}
/* Determine number of row addresses */
if (rom[3] & 0xf0) {
/* Different banks sizes */
banks[0].rows = rom[3] & 0x0f;
banks[1].rows = (rom[3] & 0xf0) >> 4;
} else {
/* Equal sized banks */
banks[0].rows = rom[3] & 0x0f;
banks[1].rows = banks[0].rows;
}
/* Determine number of column addresses */
if (rom[4] & 0xf0) {
/* Different bank sizes */
banks[0].columns = rom[4] & 0x0f;
banks[1].columns = (rom[4] & 0xf0) >> 4;
} else {
banks[0].columns = rom[4] & 0x0f;
banks[1].columns = banks[0].columns;
}
/* Check Jedec revision, and modify row/column accordingly */
if (rom[62] > 0x10) {
if (banks[0].rows <= 3)
banks[0].rows += 15;
if (banks[1].rows <= 3)
banks[1].rows += 15;
if (banks[0].columns <= 3)
banks[0].columns += 15;
if (banks[0].columns <= 3)
banks[0].columns += 15;
}
/* Check registered/unregisterd */
if (rom[21] & 0x12) {
banks[0].registered = 1;
banks[1].registered = 1;
} else {
banks[0].registered = 0;
banks[1].registered = 0;
}
#ifdef CONFIG_ECC
/* Check parity/ECC */
banks[0].ecc = (rom[11] == 0x02);
banks[1].ecc = (rom[11] == 0x02);
#endif
/* Find burst lengths supported */
banks[0].burst_len = rom[16] & 0x8f;
banks[1].burst_len = rom[16] & 0x8f;
/* Find possible cas latencies */
banks[0].cas_lat = rom[18] & 0x7F;
banks[1].cas_lat = rom[18] & 0x7F;
/* RAS/CAS latency */
banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
/* Precharge latency */
banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
/* highest CAS latency */
banks[0].tclk_hi = NS10to10PS (rom[9]);
banks[1].tclk_hi = NS10to10PS (rom[9]);
/* second highest CAS latency */
banks[0].tclk_2hi = NS10to10PS (rom[23]);
banks[1].tclk_2hi = NS10to10PS (rom[23]);
/* bank sizes */
datawidth = rom[13] & 0x7f;
banks[0].size =
(1L << (banks[0].rows + banks[0].columns)) *
/* FIXME datawidth */ 8 * rom[17];
if (rom[13] & 0x80)
banks[1].size = 2 * banks[0].size;
else
banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
/* FIXME datawidth */ 8 * rom[17];
/* Refresh */
if (rom[12] & 0x80) {
banks[0].auto_refresh = 1;
banks[1].auto_refresh = 1;
} else {
banks[0].auto_refresh = 0;
banks[1].auto_refresh = 0;
}
switch (rom[12] & 0x7f) {
case 0:
banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
break;
case 1:
banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
break;
case 2:
banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
break;
case 3:
banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
break;
case 4:
banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
break;
case 5:
banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
break;
default:
banks[0].refresh_time = 0x100; /* Default of Articia S */
banks[1].refresh_time = 0x100;
break;
}
#ifdef DEBUG
printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
printf ("Number of row addresses: %ld\n", banks[0].rows);
printf ("Number of coumns addresses: %ld\n", banks[0].columns);
printf ("SIMM is %sregistered\n",
banks[0].registered == 0 ? "not " : "");
#ifdef CONFIG_ECC
printf ("SIMM %s ECC\n",
banks[0].ecc == 1 ? "supports" : "doesn't support");
#endif
printf ("Supported burst lenghts: %s %s %s %s %s\n",
banks[0].burst_len & 0x08 ? "8" : " ",
banks[0].burst_len & 0x04 ? "4" : " ",
banks[0].burst_len & 0x02 ? "2" : " ",
banks[0].burst_len & 0x01 ? "1" : " ",
banks[0].burst_len & 0x80 ? "PAGE" : " ");
printf ("Supported CAS latencies: %s %s %s\n",
banks[0].cas_lat & 0x04 ? "CAS 3" : " ",
banks[0].cas_lat & 0x02 ? "CAS 2" : " ",
banks[0].cas_lat & 0x01 ? "CAS 1" : " ");
printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
printf ("Precharge latency: %ld\n", banks[0].trp);
printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
printf ("SDRAM data width: %ld\n", datawidth);
printf ("Auto Refresh %ssupported\n",
banks[0].auto_refresh ? "" : "not ");
printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
if (banks[0].used)
printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
if (banks[1].used)
printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
printf ("\n");
#endif
sm_term ();
return 1;
}
void select_cas (struct dimm_bank *banks, uint8 fast)
{
if (!banks[0].used) {
banks[0].cas_used = 0;
banks[0].cas_used = 0;
return;
}
if (fast) {
/* Search for fast CAS */
uint32 i;
uint32 c = 0x01;
for (i = 1; i < 5; i++) {
if (banks[0].cas_lat & c) {
banks[0].cas_used = i;
banks[1].cas_used = i;
debug ("Using CAS %d (fast)\n", i);
return;
}
c <<= 1;
}
/* Default to CAS 3 */
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3 (fast)\n");
return;
} else {
/* Search for slow cas */
uint32 i;
uint32 c = 0x08;
for (i = 4; i > 1; i--) {
if (banks[0].cas_lat & c) {
banks[0].cas_used = i;
banks[1].cas_used = i;
debug ("Using CAS %d (slow)\n", i);
return;
}
c >>= 1;
}
/* Default to CAS 3 */
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3 (slow)\n");
return;
}
banks[0].cas_used = 3;
banks[1].cas_used = 3;
debug ("Using CAS 3\n");
return;
}
uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
{
uint32 i;
struct RowColumnSize {
uint32 banks;
uint32 rows;
uint32 columns;
uint32 size;
uint32 register_value;
};
struct RowColumnSize rcs_map[] = {
/* Sbk Radr Cadr MB Value */
{1, 11, 8, 8, 0x00840f00},
{1, 11, 9, 16, 0x00925f00},
{1, 11, 10, 32, 0x00a64f00},
{2, 12, 8, 32, 0x00c55f00},
{2, 12, 9, 64, 0x00d66f00},
{2, 12, 10, 128, 0x00e77f00},
{2, 12, 11, 256, 0x00ff8f00},
{2, 13, 11, 512, 0x00ff9f00},
{0, 0, 0, 0, 0x00000000}
};
i = 0;
while (rcs_map[i].banks != 0) {
if (rows == rcs_map[i].rows
&& columns == rcs_map[i].columns
&& (size / 1024 / 1024) == rcs_map[i].size)
return rcs_map[i].register_value;
i++;
}
return 0;
}
uint32 burst_to_len (uint32 support)
{
if (support & 0x80)
return 0x7;
else if (support & 0x8)
return 0x3;
else if (support & 0x4)
return 0x2;
else if (support & 0x2)
return 0x1;
else if (support & 0x1)
return 0x0;
return 0;
}
long articiaS_ram_init (void)
{
register uint32 i;
register uint32 value1;
register uint32 value2;
uint8 rom[128];
uint32 burst_len;
uint32 burst_support;
uint32 total_ram = 0;
struct dimm_bank banks[4]; /* FIXME: Move to initram */
uint32 busclock = gd->bus_clk;
uint32 memclock = busclock;
uint32 reg32;
uint32 refresh_clocks;
uint8 auto_refresh;
memset (banks, 0, sizeof (struct dimm_bank) * 4);
detect_sdram (rom, 0, &banks[0]);
detect_sdram (rom, 1, &banks[2]);
for (i = 0; i < 4; i++) {
total_ram = total_ram + (banks[i].used * banks[i].size);
}
pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */
pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */
pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */
/* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
if (banks[0].used) {
value1 = get_reg_setting (banks[0].used + banks[1].used,
banks[0].rows, banks[0].columns,
banks[0].size);
} else {
value1 = 0;
}
if (banks[1].used) {
value2 = get_reg_setting (banks[0].used + banks[1].used,
banks[1].rows, banks[1].columns,
banks[1].size);
} else {
value2 = 0;
}
pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
if (banks[2].used) {
value1 = get_reg_setting (banks[2].used + banks[3].used,
banks[2].rows, banks[2].columns,
banks[2].size);
} else {
value1 = 0;
}
if (banks[3].used) {
value2 = get_reg_setting (banks[2].used + banks[3].used,
banks[3].rows, banks[3].columns,
banks[3].size);
} else {
value2 = 0;
}
pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
/* Determine timing */
select_cas (&banks[0], 0);
select_cas (&banks[2], 0);
/* FIXME: What about write recovery */
/* Auto refresh Precharge */
#if 0
reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
/* Write recovery CAS Latency */
(0x1 << 6) | (banks[0].cas_used << 4) |
/* RAS/CAS latency */
((banks[0].trcd - 1) << 0);
reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
(0x1 << 6) | (banks[2].cas_used << 4) |
((banks[2].trcd - 1) << 0)) << 16;
#else
if (100000000 == gd->bus_clk)
reg32 = 0x71737173;
else
reg32 = 0x69736973;
#endif
pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
/* Write default in DIMM2/3 (not used on A1) */
pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
/* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
reg32 &= 0xFF00FFFF;
#if 0
if (banks[0].used && banks[0].registered)
reg32 |= 0x1 << 16;
if (banks[2].used && banks[2].registered)
reg32 |= 0x1 << 18;
#else
if (banks[0].registered || banks[2].registered)
reg32 |= 0x55 << 16;
#endif
pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
debug ("DRAM_GCR0 = 0x%08x\n", reg32);
/* Determine refresh */
refresh_clocks = 0xffffffff;
auto_refresh = 1;
for (i = 0; i < 4; i++) {
if (banks[i].used) {
if (banks[i].auto_refresh == 0)
auto_refresh = 0;
if (banks[i].refresh_time < refresh_clocks)
refresh_clocks = banks[i].refresh_time;
}
}
#if 1
/* It seems this is suggested by the ArticiaS data book */
if (100000000 == gd->bus_clk)
refresh_clocks = 1561;
else
refresh_clocks = 2083;
#endif
debug ("Refresh set to %ld clocks, auto refresh %s\n",
refresh_clocks, auto_refresh ? "on" : "off");
pci_write_cfg_long (0, 0, DRAM_REFRESH0,
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
(refresh_clocks));
debug ("DRAM_REFRESH0 = 0x%08x\n",
(1 << 16) | (1 << 15) | (auto_refresh << 12) |
(refresh_clocks));
/* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */
/* Set mode registers */
/* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
/* Find a common burst len */
burst_support = 0xff;
if (banks[0].used)
burst_support = banks[0].burst_len;
if (banks[1].used)
burst_support = banks[1].burst_len;
if (banks[2].used)
burst_support = banks[2].burst_len;
if (banks[3].used)
burst_support = banks[3].burst_len;
/*
** Mode register:
** Bits Use
** 0-2 Burst len
** 3 Burst type (0 = sequential, 1 = interleave)
** 4-6 CAS latency
** 7-8 Operation mode (0 = default, all others invalid)
** 9 Write burst
** 10-11 Reserved
**
** Mode register burst table:
** A2 A1 A0 lenght
** 0 0 0 1
** 0 0 1 2
** 0 1 0 4
** 0 1 1 8
** 1 0 0 invalid
** 1 0 1 invalid
** 1 1 0 invalid
** 1 1 1 page (only valid for non-interleaved)
*/
burst_len = burst_to_len (burst_support);
burst_len = 2; /* FIXME */
if (banks[0].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0x8000 | burst_len | (banks[0].cas_used << 4));
debug ("Mode bank 0: 0x%08x\n",
0x8000 | burst_len | (banks[0].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
}
if (banks[1].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0x9000 | burst_len | (banks[1].cas_used << 4));
debug ("Mode bank 1: 0x%08x\n",
0x8000 | burst_len | (banks[1].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
}
if (banks[2].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0xa000 | burst_len | (banks[2].cas_used << 4));
debug ("Mode bank 2: 0x%08x\n",
0x8000 | burst_len | (banks[2].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
}
if (banks[3].used) {
pci_write_cfg_word (0, 0, DRAM_PCR0,
0xb000 | burst_len | (banks[3].cas_used << 4));
debug ("Mode bank 3: 0x%08x\n",
0x8000 | burst_len | (banks[3].cas_used << 4));
} else {
/* Seems to be needed to disable the bank */
pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
}
pci_write_cfg_word (0, 0, 0xba, 0x00);
return total_ram;
}
extern int drv_isa_kbd_init (void);
int last_stage_init (void)
{
drv_isa_kbd_init ();
return 0;
}
int overwrite_console (void)
{
return (0);
}
#define in_8 read_byte
#define out_8 write_byte
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
asm volatile ("mfmsr %0":"=r" (msr):);
return msr;
}
static __inline__ void set_msr (unsigned long msr)
{
asm volatile ("mtmsr %0"::"r" (msr));
}
int board_early_init_f (void)
{
unsigned char c_value = 0;
unsigned long msr;
/* Basic init of PS/2 keyboard (needed for some reason)... */
/* Ripped from John's code */
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xaa);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
c_value = in_8 ((unsigned char *) 0xfe000060);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xab);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
c_value = in_8 ((unsigned char *) 0xfe000060);
while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
out_8 ((unsigned char *) 0xfe000064, 0xae);
/* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
/* c_value = in_8((unsigned char *)0xfe000060); */
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
via_calibrate_bus_freq ();
return 0;
}

View File

@ -1,142 +0,0 @@
#ifndef ARTICIAS_H
#define ARTICIAS_H
#include "short_types.h"
#include <common.h>
#define REG_GROUP 0xF0
/* ArticiaS registers */
#define GLOBALINFO0 0x50
#define GLOBALINFO1 0x51
#define GLOBALINFO2 0x52
#define GLOBALINFO3 0x53
#define GLOBALCTL0 0x54
#define GLOBALCTL1 0x55
#define NVRAMCTL 0x56
#define PCI1ACR0 0x58
#define PCI1ACR1 0x59
#define PCI1ACR2 0x5a
#define PCI1ACR3 0x5b
#define HBUSACR0 0x5c
#define HBUSACR1 0x5d
#define HBUSACR2 0x5e
#define HBUSACR3 0x5f
#define HOSTINT0 0x68
#define HOSTINT1 0x69
#define HOSTINT2 0x6a
#define HOSTINT3 0x6b
#define HOSTRBCR 0x70
#define XDBCR 0x74
#define LBSBCR2 0xd2
/* Memory controller */
#define DIMM0_B0_SCR0 0x90
#define DIMM0_B1_SCR0 0x94
#define DIMM1_B2_SCR0 0x98
#define DIMM1_B3_SCR0 0x9c
#define DIMM2_B4_SCR0 0xa0
#define DIMM2_B5_SCR0 0xa4
#define DIMM3_B6_SCR0 0xa8
#define DIMM3_B7_SCR0 0xac
#define DIMM0_TCR0 0xb0
#define DIMM1_TCR0 0xb2
#define DIMM2_TCR0 0xb4
#define DIMM3_TCR0 0xb6
#define DRAM_REFRESH0 0xb8
#define DRAM_GCR0 0xc0
#define DRAM_PCR0 0xc6
#define DRAM_ECC0 0xc4
#define SRAM_CR 0xc8
#define DRAM_RAS_CTL0 0xcc
#define DRAM_RAS_CTL1 0xcd
/* Bits for REG_GROUP */
#define REG_GROUP_MULTI (1<<1)
#define REG_GROUP_SPECIAL (1<<3)
#define REG_GROUP_DIAG (0x1<<4)
#define REG_GROUP_POWER (0x2<<4)
#define GLOBALINFO0_BO (1<<7)
#define GLOBALINFO2_B1ARBITER (1<<6)
#define HBUSACR0_CPUAPC (1<<0)
#define HBUSACR0_NUMREQ_2 (0<<1)
#define HBUSACR0_NUMREQ_3 (1<<1)
#define HBUSACR0_NUMREQ_4 (2<<1)
#define HBUSACR0_NUMREQ_MASK (7<<1)
#define HBUSACR0_RAW (1<<6)
#define HBUSACR0_WAIT (1<<7)
#define HBUSACR0_RESERVED (0x30)
#define HBUSACR2_BURST (1<<0)
#define HBUSACR2_LAT (1<<1)
#define HBUSACR3_LMWC_SM (1<<0)
#define HBUSACR3_LMWC_PCI1 (1<<1)
#define HBUSACR3_LMWC_PCI0 (1<<2)
#define HBUSACR3_PMWC_PCI1 (1<<3)
#define HBUSACR3_PMWC_PCI0 (1<<4)
#define HBUSACR3_FKH (1<<5)
#define HBUSACR3_92H_EN (1<<6)
#define HBUSACR3_60H_64H_EN (1<<7)
#define HOSTRBCR_PREFETCH (1<<4)
#define XDBCR_HWTOXD (1<<0)
#define XDBCR_KBTOXD (1<<1)
#define XDBCR_RTCTOXD (1<<2)
#define XDBCR_SCALE_1_1 (0x0<<3)
#define XDBCR_SCALE_2_2 (0x1<<3)
#define XDBCR_SCALE_3_2 (0x2<<3)
#define XDBCR_SCALE_4_4 (0x3<<3)
#define XDBCR_SCALE_5_8 (0x4<<3)
#define XDBCR_SCALE_6_8 (0x5<<3)
#define XDBCR_SCALE_8_8 (0x6<<3)
#define XDBCR_SCALE_0_16 (0x7<<3)
#define XDBCR_XDPROM (1<<7)
#define LBSBCR2_1_RWAC (1<<2)
/* PCI controller */
#define ARTICIAS_PCI_CFGADDR 0xfec00cf8
#define ARTICIAS_PCI_CFGDATA 0xfee00cfc
#define ARTICIAS_PCI_BUS 0x80000000
#define ARTICIAS_PCI_MAXSIZE 0x7cffffff
#define ARTICIAS_PCI_PHYS 0x80000000
#define ARTICIAS_SYS_BUS 0x00000000
#define ARTICIAS_SYS_MAXSIZE 0x7fffffff
#define ARTICIAS_SYS_PHYS 0x00000000
#define ARTICIAS_PCIIO_BUS 0x00800000
#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff
#define ARTICIAS_PCIIO_PHYS 0xfe800000
#define ARTICIAS_ISAIO_BUS 0x00002000
#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000
#define ARTICIAS_ISAIO_PHYS 0xfe002000
/* Prototypes */
long articiaS_ram_init(void);
void articiaS_pci_init(void);
#endif

View File

@ -1,576 +0,0 @@
/*
* (C) Copyright 2002
* Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include "memio.h"
#include "articiaS.h"
DECLARE_GLOBAL_DATA_PTR;
#undef ARTICIA_PCI_DEBUG
#ifdef ARTICIA_PCI_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct pci_controller articiaS_hose;
long irq_alloc(long wanted);
static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index);
static int articiaS_init_vga(void);
static void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
unsigned char pci_irq_alloc(void);
extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table);
extern void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
extern void via_init_irq_routing(uint8 []);
extern void via_init_afterscan(void);
#define cfgfunc_via686 1
#define cfgfunc_dummy 2
#define cfgfunc_ide_init 3
static struct pci_config_table config_table[] =
{
{
0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
(void *)cfgfunc_via686, {0, 0, 0}
},
{
0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4,
(void *)cfgfunc_dummy, {0,0,0}
},
{
0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID,
(void *)cfgfunc_dummy, {0,0,0}
},
{
0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1,
(void *)cfgfunc_ide_init, {0,0,0}
},
{
0,
}
};
void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
{
}
unsigned long irq_penalties[16] =
{
1000, /* 0:timer */
1000, /* 1:keyboard */
1000, /* 2:cascade */
50, /* 3:serial (COM2) */
50, /* 4:serial (COM1) */
4, /* 5:USB2 */
100, /* 6:floppy */
3, /* 7:parallel */
50, /* 8:AC97/MC97 */
0, /* 9: */
3, /* 10:: */
0, /* 11: */
3, /* 12: USB1 */
0, /* 13: */
100, /* 14: ide0 */
100, /* 15: ide1 */
};
/*
* The following defines a hard-coded interrupt mapping for the
* know devices on the board.
* If a device isn't found here, assumed to be a device that's
* plugged into a PCI or AGP slot
* NOTE: This table is machine dependant.
*/
struct pci_irq_fixup_table
{
uint8 bus; /* Bus number */
uint8 device; /* Device number */
uint8 func; /* Function number */
uint8 interrupt; /* Interrupt to use (0xff to disable) */
};
struct pci_irq_fixup_table fixuptab [] =
{
{ 0, 0, 0, 0xff}, /* Articia S host bridge */
{ 0, 1, 0, 0xff}, /* Articia S AGP bridge */
/* { 0, 6, 0, 0x05}, /###* 3COM ethernet */
{ 0, 7, 0, 0xff}, /* VIA southbridge */
{ 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */
/* { 0, 7, 2, 0x05}, /###* First USB controller */
/* { 0, 7, 3, 0x0c}, /###* Second USB controller (shares interrupt with ethernet) */
{ 0, 7, 4, 0xff}, /* ACPI Power Management */
/* { 0, 7, 5, 0x08}, /###* AC97 */
/* { 0, 7, 6, 0x08}, /###* MC97 */
{ 0xff, 0xff, 0xff, 0xff}
};
/*
* This table maps IRQ's to PCI interrupts
*/
uint8 pci_intmap[4] = {0, 0, 0, 0};
/*
* Map PCI slots to interrupt routings
* This table lists the device number assigned to a card inserted
* into the slot, along with a permutation for the slot's IRQ routing.
* NOTE: This table is machine dependant.
*/
struct pci_slot_irq_routing
{
uint8 bus;
uint8 device;
uint8 ints[4];
};
struct pci_slot_irq_routing amigaone_pci_routing[] =
{
{0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */
{0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */
{0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */
{1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */
{1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */
{0, 6, {3, 3, 3, 3}}, /* On board ethernet */
{0, 7, {0, 1, 2, 3}}, /* Southbridge */
{0xff, 0, {0, 0, 0, 0}}
};
void articiaS_pci_irq_init(void)
{
char *s;
s = getenv("pci_irqa");
if (s)
pci_intmap[0] = simple_strtoul (s, NULL, 10);
else
pci_intmap[0] = pci_irq_alloc();
s = getenv("pci_irqb");
if (s)
pci_intmap[1] = simple_strtoul (s, NULL, 10);
else
pci_intmap[1] = pci_irq_alloc();
s = getenv("pci_irqc");
if (s)
pci_intmap[2] = simple_strtoul (s, NULL, 10);
else
pci_intmap[2] = pci_irq_alloc();
s = getenv("pci_irqd");
if (s)
pci_intmap[3] = simple_strtoul (s, NULL, 10);
else
pci_intmap[3] = pci_irq_alloc();
}
unsigned char pci_irq_alloc(void)
{
int i;
int interrupt = 10;
unsigned long min_penalty = 1000;
/* Search for the minimal penalty, favoring interrupts at the end */
for (i = 0; i < 16; i++)
{
if (irq_penalties[i] <= min_penalty)
{
interrupt = i;
min_penalty = irq_penalties[i];
}
}
PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt);
irq_penalties[interrupt]++;
return interrupt;
}
void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
int8 bus, device, func, pin, line;
int i;
bus = PCI_BUS(dev);
device = PCI_DEV(dev);
func = PCI_FUNC(dev);
PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func);
/* Search for the device in the table */
for (i = 0; fixuptab[i].bus != 0xff; i++)
{
if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func)
{
/* If the device needs an interrupt, write it */
if (fixuptab[i].interrupt != 0xff)
{
PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt);
}
else
{
/* Otherwise, see if it wants an interrupt, and disable it if needed */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
if (pin)
{
PRINTF("Disabling IRQ\n");
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff);
}
}
return;
}
}
/* If we get here, we have another PCI device in a slot... find the appropriate IRQ */
/* Find matching pin */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
pin--;
/* Search for it's map */
for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++)
{
if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device)
{
line = pci_intmap[amigaone_pci_routing[i].ints[pin]];
PRINTF("Assigning IRQ %d (pin %d)\n", line, pin);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line);
return;
}
}
PRINTF("Unkonwn PCI device found\n");
}
void articiaS_pci_init (void)
{
int i;
char *s;
PRINTF("atriciaS_pci_init\n");
/* Why aren't these relocated?? */
for (i=0; config_table[i].config_device; i++)
{
switch((int)config_table[i].config_device)
{
case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break;
case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break;
case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break;
default: PRINTF("Error: Unknown constant\n");
}
}
articiaS_hose.first_busno = 0;
articiaS_hose.last_busno = 0xff;
articiaS_hose.config_table = config_table;
articiaS_hose.fixup_irq = articiaS_pci_fixup_irq;
articiaS_pci_irq_init();
/* System memory */
pci_set_region(articiaS_hose.regions + 0,
ARTICIAS_SYS_BUS,
ARTICIAS_SYS_PHYS,
ARTICIAS_SYS_MAXSIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(articiaS_hose.regions + 1,
ARTICIAS_PCI_BUS,
ARTICIAS_PCI_PHYS,
ARTICIAS_PCI_MAXSIZE,
PCI_REGION_MEM);
/* PCI io space */