ERIC: drop unsupported board configuration
The ERIC board appears to be unmaintained for more than 9 years. The environment location has probably never been correct, and has been definitely broken since for at least a year. Drop it. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Swen Anderson <sand@peppercon.de> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Wolfgang Denk
parent
d4752d5d2c
commit
93b1140090
4
CREDITS
4
CREDITS
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@ -22,10 +22,6 @@ N: Guillaume Alexandre
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E: guillaume.alexandre@gespac.ch
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D: Add PCIPPC6 configuration
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N: Swen Anderson
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E: sand@peppercon.de
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D: ERIC Support
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N: Pantelis Antoniou
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E: panto@intracom.gr
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D: NETVIA & NETPHONE board support, ARTOS support.
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@ -524,8 +524,6 @@ Unknown / orphaned boards:
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RPXClassic MPC8xx
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RPXlite MPC8xx
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ERIC PPC4xx
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MOUSSE MPC824x
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RPXsuper MPC8260
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@ -1,51 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,203 +0,0 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include "eric.h"
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#include <asm/processor.h>
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#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */
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#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
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#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
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#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
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void sdram_init(void);
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the ERIC board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
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| IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
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| IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
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| indicates NO Power or HOST RESET active
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| check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
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| for real IRQ source
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| IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
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| -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
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| PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
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| else tristate)
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| Note for ERIC board:
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| An interrupt taken for the HOST (IRQ 28) indicates that
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| the HOST wrote a "1" to one of the following locations
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| - VGA CRT_GPIO0 (if R1216 is loaded)
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| - VGA CRT_GPIO1 (if R1217 is loaded)
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+-------------------------------------------------------------------------*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
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out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
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out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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char *e;
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puts ("Board: ");
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if (!s || strncmp (s, "ERIC", 9)) {
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puts ("### No HW ID - assuming ERIC");
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} else {
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/*
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initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
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the necessary info for SDRAM controller configuration
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*/
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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#ifndef CONFIG_ERIC
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int i;
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unsigned char datain[128];
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int TotalSize;
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#endif
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in arch/powerpc/cpu/ppc4xx
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*/
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sdram_init();
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#ifdef CONFIG_ERIC
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/*
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* we have no EEPROM on ERIC
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* so let init.S do the init job for SDRAM
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* and simply return 32MByte here
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*/
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return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
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#else
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/* Read Serial Presence Detect Information */
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for (i = 0; i < 128; i++)
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datain[i] = 127;
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i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
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printf ("\nReading DIMM...\n");
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#if 0
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for (i = 0; i < 128; i++) {
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printf ("%d=0x%x ", i, datain[i]);
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if (((i + 1) % 10) == 0)
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printf ("\n");
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}
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printf ("\n");
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#endif
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/*****************************/
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/* Retrieve interesting data */
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/*****************************/
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/* size of a SDRAM bank */
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/* Number of bytes per side / number of banks per side */
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if (datain[31] == 0x08)
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TotalSize = 32;
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else if (datain[31] == 0x10)
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TotalSize = 64;
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else {
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printf ("IIC READ ERROR!!!\n");
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TotalSize = 32;
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}
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/* single-sided DIMM or double-sided DIMM? */
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if (datain[5] != 1) {
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/* double-sided DIMM => SDRAM banks 0..3 are valid */
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printf ("double-sided DIMM\n");
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TotalSize *= 2;
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}
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/* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
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else {
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printf ("single-sided DIMM\n");
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}
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/* return size in Mb unit => *(1024*1024) */
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return (TotalSize * 1024 * 1024);
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#endif
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: xxx MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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@ -1,44 +0,0 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor:
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*
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* Start Address Length
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* +-----------------------+ 0x4000_0000 Start of Flash -----------------
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* | MON8xx code | 0x4000_0100 Reset Vector
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* +-----------------------+ 0x400?_????
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* | (unused) |
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* +-----------------------+ 0x4001_FF00
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* | Ethernet Addresses | 0x78
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* +-----------------------+ 0x4001_FF78
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* | (Reserved for MON8xx) | 0x44
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* +-----------------------+ 0x4001_FFBC
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* | Lock Address | 0x04
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* +-----------------------+ 0x4001_FFC0 ^
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* | Hardware Information | 0x40 | MON8xx
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* +=======================+ 0x4002_0000 (sector border) -----------------
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* | Autostart Header | | Applications
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* | ... | v
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*
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*****************************************************************************/
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1131
board/eric/flash.c
1131
board/eric/flash.c
File diff suppressed because it is too large
Load Diff
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@ -1,359 +0,0 @@
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/*------------------------------------------------------------------------------+ */
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/* */
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/* This source code is dual-licensed. You may use it under the terms */
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/* of the GNU General Public License version 2, or under the license */
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/* below. */
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/* */
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/* This source code has been made available to you by IBM on an AS-IS */
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/* basis. Anyone receiving this source is licensed under IBM */
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/* copyrights to use it in any way he or she deems fit, including */
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/* copying it, modifying it, compiling it, and redistributing it either */
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/* with or without modifications. No license under IBM patents or */
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/* patent applications is to be implied by the copyright license. */
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/* */
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/* Any user of this software should understand that IBM cannot provide */
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/* technical support for this software and will not be responsible for */
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/* any consequences resulting from the use of this software. */
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/* */
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/* Any person who transfers this source code or any derivative work */
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/* must include the IBM copyright notice, this paragraph, and the */
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/* preceding two paragraphs in the transferred software. */
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/* */
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/* COPYRIGHT I B M CORPORATION 1995 */
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/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
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/*------------------------------------------------------------------------------- */
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/*----------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* */
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/*----------------------------------------------------------------------------- */
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#include <config.h>
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 10; used to prefetch */
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mtctr r4 /* 10 cache lines to fit this function */
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/* in cache (gives us 8x10=80 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 10 cache lines */
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/*------------------------------------------------------------------- */
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/* Delay to ensure all accesses to ROM are complete before changing */
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/* bank 0 timings. 200usec should be enough. */
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/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
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/*------------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*----------------------------------------------------------------------- */
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/* Memory Bank 0 (Flash) initialization (from openbios) */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS0_AP@h
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ori r4,r4,CS0_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS0_CR@h
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ori r4,r4,CS0_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS1_AP@h
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ori r4,r4,CS1_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB1CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS1_CR@h
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ori r4,r4,CS1_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 2 (A/D converter) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB2AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS2_AP@h
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ori r4,r4,CS2_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB2CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS2_CR@h
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ori r4,r4,CS2_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 3 (Ethernet PHY Reset) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB3AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS3_AP@h
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ori r4,r4,CS3_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB3CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS3_CR@h
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ori r4,r4,CS3_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
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/*----------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,PB4AP
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS4_AP@h
|
||||
ori r4,r4,CS4_AP@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
addi r4,0,PB4CR
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS4_CR@h
|
||||
ori r4,r4,CS4_CR@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,PB5AP
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS5_AP@h
|
||||
ori r4,r4,CS5_AP@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
addi r4,0,PB5CR
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS5_CR@h
|
||||
ori r4,r4,CS5_CR@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* Memory Bank 6 (CPU LED0) initialization */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,PB6AP
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS6_AP@h
|
||||
ori r4,r4,CS6_AP@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
addi r4,0,PB6CR
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS6_CR@h
|
||||
ori r4,r4,CS5_CR@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* Memory Bank 7 (CPU LED1) initialization */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,PB7AP
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS7_AP@h
|
||||
ori r4,r4,CS7_AP@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
addi r4,0,PB7CR
|
||||
mtdcr EBC0_CFGADDR,r4
|
||||
addis r4,0,CS7_CR@h
|
||||
ori r4,r4,CS7_CR@l
|
||||
mtdcr EBC0_CFGDATA,r4
|
||||
|
||||
/* addis r4,r0,FPGA_BRDC@h */
|
||||
/* ori r4,r4,FPGA_BRDC@l */
|
||||
/* lbz r3,0(r4) /###*get FPGA board control reg */
|
||||
/* eieio */
|
||||
/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */
|
||||
/* stb r3,0(r4) */
|
||||
|
||||
nop /* pass2 DCR errata #8 */
|
||||
blr
|
||||
|
||||
/*----------------------------------------------------------------------------- */
|
||||
/* Function: sdram_init */
|
||||
/* Description: Configures SDRAM memory banks on ERIC. */
|
||||
/* We do manually init our SDRAM. */
|
||||
/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
|
||||
/* It is assumed that a 32MB 12x8(2) SDRAM is used. */
|
||||
/*----------------------------------------------------------------------------- */
|
||||
.globl sdram_init
|
||||
|
||||
sdram_init:
|
||||
|
||||
mflr r31
|
||||
|
||||
#ifdef CONFIG_SYS_SDRAM_MANUALLY
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,SDRAM0_B0CR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
addis r4,0,MB0CF@h
|
||||
ori r4,r4,MB0CF@l
|
||||
mtdcr SDRAM0_CFGDATA,r4
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,SDRAM0_B1CR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
addis r4,0,MB1CF@h
|
||||
ori r4,r4,MB1CF@l
|
||||
mtdcr SDRAM0_CFGDATA,r4
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set MB2CF for bank 2. off */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,SDRAM0_B2CR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
addis r4,0,MB2CF@h
|
||||
ori r4,r4,MB2CF@l
|
||||
mtdcr SDRAM0_CFGDATA,r4
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set MB3CF for bank 3. off */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
addi r4,0,SDRAM0_B3CR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
addis r4,0,MB3CF@h
|
||||
ori r4,r4,MB3CF@l
|
||||
mtdcr SDRAM0_CFGDATA,r4
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
|
||||
/* To set the appropriate timings, we need to know the SDRAM speed. */
|
||||
/* We can use the PLB speed since the SDRAM speed is the same as */
|
||||
/* the PLB speed. The PLB speed is the FBK divider times the */
|
||||
/* 405GP reference clock, which on the Walnut board is 33Mhz. */
|
||||
/* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
|
||||
/* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
|
||||
/* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
|
||||
/* maybe 133Mhz. */
|
||||
/*------------------------------------------------------------------- */
|
||||
|
||||
mfdcr r5,CPC0_PSR /* determine FBK divider */
|
||||
/* via STRAP reg to calc PLB speed. */
|
||||
/* SDRAM speed is the same as the PLB */
|
||||
/* speed. */
|
||||
rlwinm r4,r5,4,0x3 /* get FBK divide bits */
|
||||
|
||||
..chk_66:
|
||||
cmpi %cr0,0,r4,0x1
|
||||
bne ..chk_100
|
||||
addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */
|
||||
ori r6,r6,SDTR_66@l
|
||||
addis r7,0,RTR_66 /* RTR value for 66Mhz */
|
||||
b ..sdram_ok
|
||||
..chk_100:
|
||||
cmpi %cr0,0,r4,0x2
|
||||
bne ..chk_133
|
||||
addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
|
||||
ori r6,r6,SDTR_100@l
|
||||
addis r7,0,RTR_100 /* RTR value for 100Mhz */
|
||||
b ..sdram_ok
|
||||
..chk_133:
|
||||
addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
|
||||
ori r6,r6,0x4015
|
||||
addis r7,0,0x07F0 /* RTR value for 133Mhz */
|
||||
|
||||
..sdram_ok:
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set SDTR1 */
|
||||
/*------------------------------------------------------------------- */
|
||||
addi r4,0,SDRAM0_TR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
mtdcr SDRAM0_CFGDATA,r6
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set RTR */
|
||||
/*------------------------------------------------------------------- */
|
||||
addi r4,0,SDRAM0_RTR
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
mtdcr SDRAM0_CFGDATA,r7
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Delay to ensure 200usec have elapsed since reset. Assume worst */
|
||||
/* case that the core is running 200Mhz: */
|
||||
/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
|
||||
/*------------------------------------------------------------------- */
|
||||
addis r3,0,0x0000
|
||||
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
|
||||
mtctr r3
|
||||
..spinlp2:
|
||||
bdnz ..spinlp2 /* spin loop */
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Set memory controller options reg, MCOPT1. */
|
||||
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
|
||||
/* read/prefetch. */
|
||||
/*------------------------------------------------------------------- */
|
||||
addi r4,0,SDRAM0_CFG
|
||||
mtdcr SDRAM0_CFGADDR,r4
|
||||
addis r4,0,0x8080 /* set DC_EN=1 */
|
||||
ori r4,r4,0x0000
|
||||
mtdcr SDRAM0_CFGDATA,r4
|
||||
|
||||
/*------------------------------------------------------------------- */
|
||||
/* Delay to ensure 10msec have elapsed since reset. This is */
|
||||
/* required for the MPC952 to stabalize. Assume worst */
|
||||
/* case that the core is running 200Mhz: */
|
||||
/* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
|
||||
/* This delay should occur before accessing SDRAM. */
|
||||
/*------------------------------------------------------------------- */
|
||||
addis r3,0,0x001E
|
||||
ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
|
||||
mtctr r3
|
||||
..spinlp3:
|
||||
bdnz ..spinlp3 /* spin loop */
|
||||
|
||||
#else
|
||||
/*fixme: do SDRAM Autoconfig from EEPROM here */
|
||||
|
||||
#endif
|
||||
mtlr r31 /* restore lr */
|
||||
blr
|
||||
|
|
@ -270,7 +270,6 @@ TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01
|
|||
wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U
|
||||
csb272 powerpc ppc4xx
|
||||
csb472 powerpc ppc4xx
|
||||
ERIC powerpc ppc4xx eric
|
||||
G2000 powerpc ppc4xx g2000
|
||||
JSE powerpc ppc4xx jse
|
||||
korat powerpc ppc4xx
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU removed Commit last known maintainer/contact
|
||||
=============================================================================
|
||||
VoVPN-GW_100MHz powerpc MPC8260 - 2010-10-24 Juergen Selent <j.selent@elmeg.de>
|
||||
ERIC powerpc 405GP - 2010-11-21 Swen Anderson <sand@peppercon.de>
|
||||
VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de>
|
||||
NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
|
||||
CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
|
||||
logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl <august.hoerandl@gmx.at>
|
||||
|
|
|
|||
|
|
@ -1,369 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
|
||||
#define CONFIG_ERIC 1 /* ...on a ERIC board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#endif
|
||||
#if 0
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
#endif
|
||||
#if 0
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
|
||||
#endif /* total size of a X1240 is 2048 bytes */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
|
||||
#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#undef CONFIG_ENV_IS_IN_NVRAM
|
||||
#undef CONFIG_ENV_IS_IN_EEPROM
|
||||
#else
|
||||
#ifdef CONFIG_ENV_IS_IN_NVRAM
|
||||
#undef CONFIG_ENV_IS_IN_FLASH
|
||||
#undef CONFIG_ENV_IS_IN_EEPROM
|
||||
#else
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#undef CONFIG_ENV_IS_IN_NVRAM
|
||||
#undef CONFIG_ENV_IS_IN_FLASH
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
|
||||
"nfsroot=192.168.1.2:/eric_root_devel " \
|
||||
"ip=192.168.1.22:192.168.1.2"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_FLASH
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
|
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External peripheral base address
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
|
||||
/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
|
||||
/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
|
||||
/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
|
||||
/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
|
||||
/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
|
||||
/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
|
||||
/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
|
||||
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 0 (Flash) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS0_AP 0x9B015480
|
||||
#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 2 (A/D converter) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 3 (Ethernet PHY Reset) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 6 (CPU LED0) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* Memory Bank 7 (CPU LED1) initialization */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
|
||||
#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
|
||||
#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
|
||||
#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
|
||||
#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
|
||||
#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
|
||||
#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
|
||||
#define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
|
||||
#define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
|
||||
|
||||
|
||||
/* SDRAM CONFIG */
|
||||
#define CONFIG_SYS_SDRAM_MANUALLY 1
|
||||
#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
|
||||
|
||||
#ifdef CONFIG_SYS_SDRAM_MANUALLY
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define MB0CF 0x00062001 /* 32MB @ 0 */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
|
||||
*----------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
|
||||
#define MB1CF 0x0 /* 0MB @ 32MB */
|
||||
#else
|
||||
#define MB1CF 0x02062001 /* 32MB @ 32MB */
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB2CF for bank 2. off
|
||||
*----------------------------------------------------------------------*/
|
||||
#define MB2CF 0x0 /* 0MB */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set MB3CF for bank 3. off
|
||||
*----------------------------------------------------------------------*/
|
||||
#define MB3CF 0x0 /* 0MB */
|
||||
|
||||
#define SDTR_100 0x0086400D
|
||||
#define RTR_100 0x05F0
|
||||
#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
|
||||
#define RTR_66 0x03f8
|
||||
|
||||
#endif /* CONFIG_SYS_SDRAM_MANUALLY */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE 32
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
|
||||
/*#define CONFIG_SYS_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
|
||||
#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/* BEG ENVIRONNEMENT FLASH */
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (128*1024)
|
||||
|
||||
#if 0 /* force ENV to be NOT embedded */
|
||||
#define CONFIG_ENV_ADDR 0xfffa0000
|
||||
#else /* force ENV to be embedded */
|
||||
#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
|
||||
/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* END ENVIRONNEMENT FLASH */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NVRAM
|
||||
#define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
|
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
|
||||
|
||||
|
||||
/* Configuration Port location */
|
||||
/* #define CONFIG_PORT_ADDR 0xF0000500 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address
|
||||
* (to get SDRAM settings)
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x50
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue