Add test tool to exercise SDRAM accesses in burst mode
(as standalone program, MPC8xx/PowerPC only)
This commit is contained in:
wdenk
parent
412babe304
commit
931da93e0f
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@ -2,6 +2,9 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Add test tool to exercise SDRAM accesses in burst mode
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(as standalone program, MPC8xx/PowerPC only)
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* Increase CFG_MONITOR_LEN for Rattler board to match actual code
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size.
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@ -58,6 +58,11 @@ include $(TOPDIR)/config.mk
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SREC = hello_world.srec
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BIN = hello_world.bin hello_world
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ifeq ($(ARCH),ppc)
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SREC = test_burst.srec
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BIN = test_burst.bin test_burst
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endif
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ifeq ($(ARCH),i386)
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SREC += 82559_eeprom.srec
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BIN += 82559_eeprom.bin 82559_eeprom
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@ -96,6 +101,7 @@ LIB = libstubs.a
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LIBAOBJS=
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ifeq ($(ARCH),ppc)
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LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
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LIBAOBJS+= test_burst_lib.o
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endif
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LIBCOBJS= stubs.o
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LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
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@ -0,0 +1,275 @@
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/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* The test exercises SDRAM accesses in burst mode
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*/
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#include <common.h>
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#include <exports.h>
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#include <commproc.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <serial.h>
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#include <watchdog.h>
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#include "test_burst.h"
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/* 8 MB test region of physical RAM */
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#define TEST_PADDR 0x00800000
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/* The uncached virtual region */
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#define TEST_VADDR_NC 0x00800000
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/* The cached virtual region */
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#define TEST_VADDR_C 0x01000000
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/* When an error is detected, the address where the error has been found,
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and also the current and the expected data will be written to
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the following flash address
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*/
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#define TEST_FLASH_ADDR 0x40100000
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static void test_prepare (void);
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static int test_burst_start (unsigned long size, unsigned long pattern);
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static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
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static int test_mmu_is_on(void);
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static void test_desc(unsigned long size);
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static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
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static void signal_start(void);
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static void signal_error(void);
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static void test_usage(void);
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static unsigned long test_pattern [] = {
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0x00000000,
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0xffffffff,
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0x55555555,
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0xaaaaaaaa,
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};
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int test_burst (int argc, char *argv[])
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{
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unsigned long size = CACHE_LINE_SIZE;
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int res;
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int i;
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if (argc == 2) {
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char * d;
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for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
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size *= 10;
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size += *d - '0';
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}
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if (size == 0 || *d) {
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test_usage();
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return 1;
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}
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} else if (argc > 2) {
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test_usage();
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return 1;
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}
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size += (CACHE_LINE_SIZE - 1);
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size &= ~(CACHE_LINE_SIZE - 1);
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if (!test_mmu_is_on()) {
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test_prepare();
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}
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test_desc(size);
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for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
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res = test_burst_start(size, test_pattern[i]);
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if (res != 0) {
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goto Done;
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}
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}
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Done:
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return res;
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}
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static void test_prepare (void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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printf ("\n");
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caches_init();
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disable_interrupts();
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mmu_init();
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printf ("Interrupts are disabled\n");
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printf ("I-Cache is ON\n");
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printf ("D-Cache is ON\n");
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printf ("MMU is ON\n");
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printf ("\n");
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test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
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test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
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test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
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/* Configure PD.8 and PD.9 as general purpose output */
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immr->im_ioport.iop_pdpar &= ~0x00C0;
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immr->im_ioport.iop_pddir |= 0x00C0;
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}
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static int test_burst_start (unsigned long size, unsigned long pattern)
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{
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volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
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volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
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int i, n;
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int res = 1;
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printf ("Test pattern %08x ...", pattern);
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n = size / 4;
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for (i = 0; i < n; i ++) {
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vaddr_c [i] = pattern;
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}
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signal_start();
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flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_nc [i];
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if (tmp != pattern) {
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test_error("2a", vaddr_nc + i, tmp, pattern);
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goto Done;
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}
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}
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_c [i];
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if (tmp != pattern) {
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test_error("2b", vaddr_c + i, tmp, pattern);
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goto Done;
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}
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}
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for (i = 0; i < n; i ++) {
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vaddr_nc [i] = pattern;
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}
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_nc [i];
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if (tmp != pattern) {
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test_error("3a", vaddr_nc + i, tmp, pattern);
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goto Done;
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}
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}
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signal_start();
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for (i = 0; i < n; i ++) {
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register unsigned long tmp = vaddr_c [i];
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if (tmp != pattern) {
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test_error("3b", vaddr_c + i, tmp, pattern);
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goto Done;
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}
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}
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res = 0;
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Done:
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printf(" %s\n", res == 0 ? "OK" : "");
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return res;
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}
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static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
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{
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mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
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mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
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mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
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mtspr (MD_AP, MI_Kp);
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}
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static int test_mmu_is_on(void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr & MSR_DR;
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}
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static void test_desc(unsigned long size)
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{
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printf(
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"The following tests will be conducted:\n"
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"1) Map %d-byte region of physical RAM at 0x%08x\n"
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" into two virtual regions:\n"
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" one cached at 0x%08x and\n"
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" the the other uncached at 0x%08x.\n",
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size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
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puts(
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"2) Fill the cached region with a pattern, and flush the cache\n"
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"2a) Check the uncached region to match the pattern\n"
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"2b) Check the cached region to match the pattern\n"
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"3) Fill the uncached region with a pattern\n"
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"3a) Check the cached region to match the pattern\n"
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"3b) Check the uncached region to match the pattern\n"
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"2b) Change the patterns and go to step 2\n"
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"\n"
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);
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}
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static void test_error(
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char * step, volatile void * addr, unsigned long val, unsigned long pattern)
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{
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volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
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signal_error();
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p[0] = (unsigned long)addr;
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p[1] = val;
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p[2] = pattern;
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printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
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step, addr, val, pattern);
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}
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static void signal_start(void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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if (immr->im_ioport.iop_pddat & 0x0080) {
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immr->im_ioport.iop_pddat &= ~0x0080;
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} else {
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immr->im_ioport.iop_pddat |= 0x0080;
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}
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}
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static void signal_error(void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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if (immr->im_ioport.iop_pddat & 0x0040) {
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immr->im_ioport.iop_pddat &= ~0x0040;
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} else {
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immr->im_ioport.iop_pddat |= 0x0040;
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}
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}
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static void test_usage(void)
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{
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printf("Usage: go 0x40004 [size]\n");
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}
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@ -0,0 +1,38 @@
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/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEST_BURST_H
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#define _TEST_BURST_H
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/* Cache line size */
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#define CACHE_LINE_SIZE 16
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/* Binary logarithm of the cache line size */
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#define LG_CACHE_LINE_SIZE 4
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#ifndef __ASSEMBLY__
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extern void mmu_init(void);
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extern void caches_init(void);
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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#endif
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#endif /* _TEST_BURST_H */
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@ -0,0 +1,170 @@
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/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include "test_burst.h"
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.text
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/*
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* void mmu_init(void);
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*
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* This function turns the MMU on
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*
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* Three 8 MByte regions are mapped 1:1, uncached
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* - SDRAM lower 8 MByte
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* - SDRAM higher 8 MByte
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* - IMMR
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*/
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.global mmu_init
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mmu_init:
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tlbia /* Invalidate all TLB entries */
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li r8, 0
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mtspr MI_CTR, r8 /* Set instruction control to zero */
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lis r8, MD_RESETVAL@h
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mtspr MD_CTR, r8 /* Set data TLB control */
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/* Now map the lower 8 Meg into the TLBs. For this quick hack,
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* we can load the instruction and data TLB registers with the
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* same values.
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*/
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li r8, MI_EVALID /* Create EPN for address 0 */
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mtspr MI_EPN, r8
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mtspr MD_EPN, r8
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li r8, MI_PS8MEG /* Set 8M byte page */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr MI_TWC, r8
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mtspr MD_TWC, r8
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li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
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mtspr MI_RPN, r8 /* Store TLB entry */
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mtspr MD_RPN, r8
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lis r8, MI_Kp@h /* Set the protection mode */
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mtspr MI_AP, r8
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mtspr MD_AP, r8
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/* Now map the higher 8 Meg into the TLBs. For this quick hack,
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* we can load the instruction and data TLB registers with the
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* same values.
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*/
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lwz r9,20(r29) /* gd->ram_size */
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addis r9,r9,-0x80
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mr r8, r9 /* Higher 8 Meg in SDRAM */
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ori r8, r8, MI_EVALID /* Mark page valid */
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mtspr MI_EPN, r8
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mtspr MD_EPN, r8
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li r8, MI_PS8MEG /* Set 8M byte page */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr MI_TWC, r8
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mtspr MD_TWC, r8
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mr r8, r9
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ori r8, r8, MI_BOOTINIT|0x2
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mtspr MI_RPN, r8 /* Store TLB entry */
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mtspr MD_RPN, r8
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lis r8, MI_Kp@h /* Set the protection mode */
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mtspr MI_AP, r8
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mtspr MD_AP, r8
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/* Map another 8 MByte at the IMMR to get the processor
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* internal registers (among other things).
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*/
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mfspr r9, 638 /* Get current IMMR */
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andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
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mr r8, r9 /* Create vaddr for TLB */
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ori r8, r8, MD_EVALID /* Mark it valid */
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mtspr MD_EPN, r8
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li r8, MD_PS8MEG /* Set 8M byte page */
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ori r8, r8, MD_SVALID /* Make it valid */
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mtspr MD_TWC, r8
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mr r8, r9 /* Create paddr for TLB */
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ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
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mtspr MD_RPN, r8
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/* We now have the lower and higher 8 Meg mapped into TLB entries,
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* and the caches ready to work.
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*/
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mfmsr r0
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ori r0,r0,MSR_DR|MSR_IR
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mtspr SRR1,r0
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mflr r0
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mtspr SRR0,r0
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SYNC
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rfi /* enables MMU */
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/*
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* void caches_init(void);
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*/
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.globl caches_init
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caches_init:
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sync
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mfspr r3, IC_CST /* Clear error bits */
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mfspr r3, DC_CST
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lis r3, IDC_UNALL@h /* Unlock all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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lis r3, IDC_INVALL@h /* Invalidate all */
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mtspr IC_CST, r3
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||||
mtspr DC_CST, r3
|
||||
|
||||
lis r3, IDC_ENABLE@h /* Enable all */
|
||||
mtspr IC_CST, r3
|
||||
mtspr DC_CST, r3
|
||||
|
||||
blr
|
||||
|
||||
/*
|
||||
* void flush_dcache_range(unsigned long start, unsigned long stop);
|
||||
*/
|
||||
.global flush_dcache_range
|
||||
flush_dcache_range:
|
||||
li r5,CACHE_LINE_SIZE-1
|
||||
andc r3,r3,r5
|
||||
subf r4,r3,r4
|
||||
add r4,r4,r5
|
||||
srwi. r4,r4,LG_CACHE_LINE_SIZE
|
||||
beqlr
|
||||
mtctr r4
|
||||
|
||||
1: dcbf 0,r3
|
||||
addi r3,r3,CACHE_LINE_SIZE
|
||||
bdnz 1b
|
||||
sync /* wait for dcbf's to get to ram */
|
||||
blr
|
||||
|
||||
/*
|
||||
* void disable_interrupts(void);
|
||||
*/
|
||||
.global disable_interrupts
|
||||
disable_interrupts:
|
||||
mfmsr r0
|
||||
rlwinm r0,r0,0,17,15
|
||||
mtmsr r0
|
||||
blr
|
||||
Loading…
Reference in New Issue