TI DA8xx: Add DA8xx cpu functions
Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com Provides: Low level initialisation. System clock API. Timer control. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
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@ -23,7 +23,7 @@
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#include <common.h>
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#include <common.h>
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#include <netdev.h>
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#include <netdev.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/* offsets from PLL controller base */
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/* offsets from PLL controller base */
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#define PLLC_PLLCTL 0x100
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#define PLLC_PLLCTL 0x100
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@ -60,6 +60,54 @@
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#define DDR_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#endif
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#ifdef CONFIG_SOC_DA8XX
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const dv_reg * const sysdiv[7] = {
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&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
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&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
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&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
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&davinci_pllc_regs->plldiv7
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};
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int clk_get(enum davinci_clk_ids id)
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{
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int pre_div;
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int pllm;
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int post_div;
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int pll_out;
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pll_out = CONFIG_SYS_OSCIN_FREQ;
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if (id == DAVINCI_AUXCLK_CLKID)
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goto out;
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/*
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* Lets keep this simple. Combining operations can result in
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* unexpected approximations
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*/
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pre_div = (readl(&davinci_pllc_regs->prediv) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pllm = readl(&davinci_pllc_regs->pllm) + 1;
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pll_out /= pre_div;
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pll_out *= pllm;
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if (id == DAVINCI_PLLM_CLKID)
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goto out;
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post_div = (readl(&davinci_pllc_regs->postdiv) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= post_div;
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if (id == DAVINCI_PLLC_CLKID)
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goto out;
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pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
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out:
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return pll_out;
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}
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#endif /* CONFIG_SOC_DA8XX */
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#ifdef CONFIG_DISPLAY_CPUINFO
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#ifdef CONFIG_DISPLAY_CPUINFO
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@ -25,6 +25,7 @@
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#include <common.h>
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/*
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/*
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* The PSC manages three inputs to a "module" which may be a peripheral or
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* The PSC manages three inputs to a "module" which may be a peripheral or
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@ -47,21 +48,45 @@
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/* Works on Always On power domain only (no PD argument) */
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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void lpsc_on(unsigned int id)
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{
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{
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dv_reg_p mdstat, mdctl;
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dv_reg_p mdstat, mdctl, ptstat, ptcmd;
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#ifdef CONFIG_SOC_DA8XX
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struct davinci_psc_regs *psc_regs;
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#endif
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#ifndef CONFIG_SOC_DA8XX
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if (id >= DAVINCI_LPSC_GEM)
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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ptstat = REG_P(PSC_PTSTAT);
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ptcmd = REG_P(PSC_PTCMD);
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#else
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if (id < DAVINCI_LPSC_PSC1_BASE) {
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if (id >= PSC_PSC0_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc0_regs;
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mdstat = &psc_regs->psc0.mdstat[id];
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mdctl = &psc_regs->psc0.mdctl[id];
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} else {
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id -= DAVINCI_LPSC_PSC1_BASE;
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if (id >= PSC_PSC1_MODULE_ID_CNT)
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return;
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psc_regs = davinci_psc1_regs;
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mdstat = &psc_regs->psc1.mdstat[id];
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mdctl = &psc_regs->psc1.mdctl[id];
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}
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ptstat = &psc_regs->ptstat;
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ptcmd = &psc_regs->ptcmd;
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#endif
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while (REG(PSC_PTSTAT) & 0x01)
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while (readl(ptstat) & 0x01)
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continue;
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continue;
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if ((*mdstat & 0x1f) == 0x03)
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if ((readl(mdstat) & 0x1f) == 0x03)
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return; /* Already on and enabled */
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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writel(readl(mdctl) | 0x03, mdctl);
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switch (id) {
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switch (id) {
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#ifdef CONFIG_SOC_DM644X
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#ifdef CONFIG_SOC_DM644X
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@ -80,16 +105,16 @@ void lpsc_on(unsigned int id)
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case DAVINCI_LPSC_MEMSTICK:
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case DAVINCI_LPSC_MEMSTICK:
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case DAVINCI_LPSC_McBSP:
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case DAVINCI_LPSC_McBSP:
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case DAVINCI_LPSC_GPIO:
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case DAVINCI_LPSC_GPIO:
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*mdctl |= 0x200;
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writel(readl(mdctl) | 0x200, mdctl);
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break;
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break;
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#endif
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#endif
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}
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}
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REG(PSC_PTCMD) = 0x01;
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writel(0x01, ptcmd);
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while (REG(PSC_PTSTAT) & 0x03)
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while (readl(ptstat) & 0x01)
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continue;
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continue;
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while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */
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while ((readl(mdstat) & 0x1f) != 0x03)
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continue;
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continue;
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}
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}
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