Merged and added more pxa-regs.h stuff, especially the GPIO Control
Register Definitions.
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
57dc57f14d
commit
8fb1857b40
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@ -72,7 +72,7 @@
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#define NO_AUTOPROBE
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#define SMC_DEBUG 0
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#define SMC_DEBUG 3
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#if SMC_DEBUG > 1
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static const char version[] =
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@ -961,12 +961,217 @@ typedef void (*ExcpHndlr) (void) ;
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#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
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#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
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#ifdef CONFIG_CPU_MONAHANS
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#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
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#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
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#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
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#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
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#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
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#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
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#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
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#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
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#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
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#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
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#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
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#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
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#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
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#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
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#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
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#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
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#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
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#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
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#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
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#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
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#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
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#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
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#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
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#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
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#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
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#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
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#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
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#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
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#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
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#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
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#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
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#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
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#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
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/* Multi-funktion Pin Registers, uncomplete, only GPIO relevant pins for now */
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#define GPIO0 __REG(0x40e10124)
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#define GPIO1 __REG(0x40e10128)
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#define GPIO2 __REG(0x40e1012c)
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#define GPIO3 __REG(0x40e10130)
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#define GPIO4 __REG(0x40e10134)
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#define GPIO5 __REG(0x40e1028c)
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#define GPIO6 __REG(0x40e10290)
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#define GPIO7 __REG(0x40e10294)
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#define GPIO8 __REG(0x40e10298)
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#define GPIO9 __REG(0x40e1029c)
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#define GPIO11 __REG(0x40e102a0)
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#define GPIO12 __REG(0x40e102a4)
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#define GPIO13 __REG(0x40e102a8)
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#define GPIO14 __REG(0x40e102ac)
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#define GPIO15 __REG(0x40e102b0)
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#define GPIO16 __REG(0x40e102b4)
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#define GPIO17 __REG(0x40e102b8)
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#define GPIO18 __REG(0x40e102bc)
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#define GPIO19 __REG(0x40e102c0)
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#define GPIO20 __REG(0x40e102c4)
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#define GPIO21 __REG(0x40e102c8)
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#define GPIO22 __REG(0x40e102cc)
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#define GPIO23 __REG(0x40e102d0)
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#define GPIO24 __REG(0x40e102d4)
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#define GPIO25 __REG(0x40e102d8)
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#define GPIO26 __REG(0x40e102dc)
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#define GPIO27 __REG(0x40e10400)
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#define GPIO28 __REG(0x40e10404)
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#define GPIO29 __REG(0x40e10408)
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#define GPIO30 __REG(0x40e1040c)
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#define GPIO31 __REG(0x40e10410)
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#define GPIO32 __REG(0x40e10414)
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#define GPIO33 __REG(0x40e10418)
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#define GPIO34 __REG(0x40e1041c)
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#define GPIO35 __REG(0x40e10420)
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#define GPIO36 __REG(0x40e10424)
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#define GPIO37 __REG(0x40e10428)
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#define GPIO38 __REG(0x40e1042c)
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#define GPIO39 __REG(0x40e10430)
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#define GPIO40 __REG(0x40e10434)
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#define GPIO41 __REG(0x40e10438)
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#define GPIO42 __REG(0x40e1043c)
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#define GPIO43 __REG(0x40e10440)
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#define GPIO44 __REG(0x40e10444)
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#define GPIO45 __REG(0x40e10448)
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#define GPIO46 __REG(0x40e1044c)
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#define GPIO47 __REG(0x40e10450)
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#define GPIO48 __REG(0x40e10454)
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#define GPIO10 __REG(0x40e10458)
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#define GPIO49 __REG(0x40e1045c)
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#define GPIO50 __REG(0x40e10460)
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#define GPIO51 __REG(0x40e10464)
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#define GPIO52 __REG(0x40e10468)
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#define GPIO53 __REG(0x40e1046c)
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#define GPIO54 __REG(0x40e10470)
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#define GPIO55 __REG(0x40e10474)
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#define GPIO56 __REG(0x40e10478)
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#define GPIO57 __REG(0x40e1047c)
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#define GPIO58 __REG(0x40e10480)
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#define GPIO59 __REG(0x40e10484)
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#define GPIO60 __REG(0x40e10488)
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#define GPIO61 __REG(0x40e1048c)
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#define GPIO62 __REG(0x40e10490)
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#define GPIO6_2 __REG(0x40e10494)
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#define GPIO7_2 __REG(0x40e10498)
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#define GPIO8_2 __REG(0x40e1049c)
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#define GPIO9_2 __REG(0x40e104a0)
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#define GPIO10_2 __REG(0x40e104a4)
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#define GPIO11_2 __REG(0x40e104a8)
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#define GPIO12_2 __REG(0x40e104ac)
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#define GPIO13_2 __REG(0x40e104b0)
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#define GPIO63 __REG(0x40e104b4)
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#define GPIO64 __REG(0x40e104b8)
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#define GPIO65 __REG(0x40e104bc)
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#define GPIO66 __REG(0x40e104c0)
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#define GPIO67 __REG(0x40e104c4)
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#define GPIO68 __REG(0x40e104c8)
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#define GPIO69 __REG(0x40e104cc)
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#define GPIO70 __REG(0x40e104d0)
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#define GPIO71 __REG(0x40e104d4)
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#define GPIO72 __REG(0x40e104d8)
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#define GPIO73 __REG(0x40e104dc)
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#define GPIO14_2 __REG(0x40e104e0)
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#define GPIO15_2 __REG(0x40e104e4)
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#define GPIO16_2 __REG(0x40e104e8)
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#define GPIO17_2 __REG(0x40e104ec)
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#define GPIO74 __REG(0x40e104f0)
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#define GPIO75 __REG(0x40e104f4)
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#define GPIO76 __REG(0x40e104f8)
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#define GPIO77 __REG(0x40e104fc)
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#define GPIO78 __REG(0x40e10500)
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#define GPIO79 __REG(0x40e10504)
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#define GPIO80 __REG(0x40e10508)
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#define GPIO81 __REG(0x40e1050c)
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#define GPIO82 __REG(0x40e10510)
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#define GPIO83 __REG(0x40e10514)
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#define GPIO84 __REG(0x40e10518)
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#define GPIO85 __REG(0x40e1051c)
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#define GPIO86 __REG(0x40e10520)
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#define GPIO87 __REG(0x40e10524)
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#define GPIO88 __REG(0x40e10528)
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#define GPIO89 __REG(0x40e1052c)
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#define GPIO90 __REG(0x40e10530)
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#define GPIO91 __REG(0x40e10534)
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#define GPIO92 __REG(0x40e10538)
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#define GPIO93 __REG(0x40e1053c)
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#define GPIO94 __REG(0x40e10540)
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#define GPIO95 __REG(0x40e10544)
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#define GPIO96 __REG(0x40e10548)
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#define GPIO97 __REG(0x40e1054c)
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#define GPIO98 __REG(0x40e10550)
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#define GPIO99 __REG(0x40e10600)
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#define GPIO100 __REG(0x40e10604)
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#define GPIO101 __REG(0x40e10608)
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#define GPIO102 __REG(0x40e1060c)
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#define GPIO103 __REG(0x40e10610)
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#define GPIO104 __REG(0x40e10614)
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#define GPIO105 __REG(0x40e10618)
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#define GPIO106 __REG(0x40e1061c)
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#define GPIO107 __REG(0x40e10620)
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#define GPIO108 __REG(0x40e10624)
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#define GPIO109 __REG(0x40e10628)
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#define GPIO110 __REG(0x40e1062c)
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#define GPIO111 __REG(0x40e10630)
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#define GPIO112 __REG(0x40e10634)
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#define GPIO113 __REG(0x40e10638)
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#define GPIO114 __REG(0x40e1063c)
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#define GPIO115 __REG(0x40e10640)
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#define GPIO116 __REG(0x40e10644)
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#define GPIO117 __REG(0x40e10648)
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#define GPIO118 __REG(0x40e1064c)
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#define GPIO119 __REG(0x40e10650)
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#define GPIO120 __REG(0x40e10654)
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#define GPIO121 __REG(0x40e10658)
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#define GPIO122 __REG(0x40e1065c)
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#define GPIO123 __REG(0x40e10660)
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#define GPIO124 __REG(0x40e10664)
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#define GPIO125 __REG(0x40e10668)
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#define GPIO126 __REG(0x40e1066c)
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#define GPIO127 __REG(0x40e10670)
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#define GPIO0_2 __REG(0x40e10674)
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#define GPIO1_2 __REG(0x40e10678)
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#define GPIO2_2 __REG(0x40e1067c)
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#define GPIO3_2 __REG(0x40e10680)
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#define GPIO4_2 __REG(0x40e10684)
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#define GPIO5_2 __REG(0x40e10688)
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#else /* CONFIG_CPU_MONAHANS */
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#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
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#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
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#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
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#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
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#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
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#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
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#endif /* CONFIG_CPU_MONAHANS */
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/* More handy macros. The argument is a literal GPIO number. */
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@ -63,7 +63,7 @@
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# define CONFIG_SMC91111_BASE 0x14000300
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# define CONFIG_SMC91111_EXT_PHY
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# define CONFIG_SMC_USE_32_BIT
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# undef CONFIG_SMC_USE_IOFUNCS
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# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
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#endif
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/*
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@ -78,7 +78,7 @@
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/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
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#ifdef TURN_ON_ETHERNET
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# define CONFIG_COMMANDS (CONFIG_CMD_DFL)
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# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
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#else
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# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
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#endif
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@ -87,7 +87,7 @@
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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