* Patches by Richard Woodruff, 01 Oct 2004:
add support for the TI OMAP2420 processor and its H4 reference board * Patch by Christian Pellegrin, 24 Sep 2004: Added support for NE2000 compatible (DP8390, DP83902) NICs.master
wdenk
parent
ff36fd8591
commit
8ed9604613
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patches by Richard Woodruff, 01 Oct 2004:
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add support for the TI OMAP2420 processor and its H4 reference
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board
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* Patch by Christian Pellegrin, 24 Sep 2004:
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Added support for NE2000 compatible (DP8390, DP83902) NICs.
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* Patch by Leif Lindholm, 23 Sep 2004:
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add support for the AMD db1550 board
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@ -382,6 +382,10 @@ Rishi Bhattacharya <rishi@ti.com>
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omap5912osk ARM926EJS
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Richard Woodruff <r-woodruff2@ti.com>
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omap2420h4 ARM1136EJS
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David Müller <d.mueller@elsoft.ch>
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smdk2410 ARM920T
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13
MAKEALL
13
MAKEALL
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@ -157,6 +157,11 @@ LIST_ARM9=" \
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versatile \
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"
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#########################################################################
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## ARM11 Systems
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#########################################################################
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LIST_ARM11="omap2420h4"
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#########################################################################
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## Xscale Systems
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#########################################################################
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@ -170,7 +175,11 @@ LIST_pxa=" \
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LIST_ixp="ixdp425"
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LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"
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LIST_arm=" \
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${LIST_SA} \
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${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11} \
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${LIST_pxa} ${LIST_ixp} \
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"
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#########################################################################
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## MIPS Systems
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@ -238,7 +247,7 @@ for arg in $@
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do
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case "$arg" in
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ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
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arm|SA|ARM7|ARM9|pxa|ixp| \
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arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
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microblaze| \
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mips| \
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nios|nios2| \
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6
Makefile
6
Makefile
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@ -1403,6 +1403,12 @@ xm250_config : unconfig
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xsengine_config : unconfig
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@./mkconfig $(@:_config=) arm pxa xsengine
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#########################################################################
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## ARM1136 Systems
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#########################################################################
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omap2420h4_config : unconfig
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@./mkconfig $(@:_config=) arm arm1136 omap2420h4
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#========================================================================
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# i386
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#========================================================================
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17
README
17
README
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@ -130,6 +130,7 @@ Directory Hierarchy:
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- s3c24x0 Files specific to Samsung S3C24X0 CPUs
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- arm925t Files specific to ARM 925 CPUs
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- arm926ejs Files specific to ARM 926 CPUs
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- arm1136 Files specific to ARM 1136 CPUs
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- at91rm9200 Files specific to Atmel AT91RM9200 CPUs
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- i386 Files specific to i386 CPUs
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- ixp Files specific to Intel XScale IXP CPUs
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@ -301,13 +302,13 @@ The following options need to be configured:
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ARM based boards:
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-----------------
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CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110,
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CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
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CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
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CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK,
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CONFIG_OSK_OMAP5912, CONFIG_SHANNON, CONFIG_P2_OMAP730,
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CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
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CONFIG_VCMA9
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CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110,
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CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
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CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
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CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK,
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CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON,
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CONFIG_P2_OMAP730, CONFIG_SMDK2400, CONFIG_SMDK2410,
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CONFIG_TRAB, CONFIG_VCMA9
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MicroBlaze based boards:
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------------------------
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@ -2177,7 +2178,7 @@ configurations; the following names are supported:
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FADS850SAR_config omap1610h2_config TQM850L_config
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FADS860T_config omap1610inn_config TQM855L_config
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FPS850L_config omap5912osk_config TQM860L_config
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WALNUT405_config
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omap2420h4_config WALNUT405_config
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Yukon8220_config
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ZPC1900_config
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := omap2420h4.o flash.o mem.o sys_info.o
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SOBJS := platform.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $^
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,26 @@
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#
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# (C) Copyright 2004
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# Texas Instruments, <www.ti.com>
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#
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# TI H4 board with OMAP2420 (ARM1136) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
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# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1) ES2 will be configurable
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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# For use with external or internal boots.
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# CONFIG_PARTIAL_SRAM must be defined to use this.
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TEXT_BASE = 0x80e80000
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# Used with full SRAM boot.
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# This is either with a GP system or a signed boot image.
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# easiest, and safest way to go if you can.
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# Comment out //CONFIG_PARTIAL_SRAM for this one.
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#
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#TEXT_BASE = 0x40280000
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@ -0,0 +1,536 @@
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/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/sizes.h>
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#include <linux/byteorder/swab.h>
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#define PHYS_FLASH_SECT_SIZE SZ_128K
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* Board support for 1 or 2 flash devices */
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#undef FLASH_PORT_WIDTH32
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#define FLASH_PORT_WIDTH16
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#ifdef FLASH_PORT_WIDTH16
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# define FLASH_PORT_WIDTH ushort
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# define FLASH_PORT_WIDTHV vu_short
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# define SWAP(x) __swab16(x)
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#else
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# define FLASH_PORT_WIDTH ulong
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# define FLASH_PORT_WIDTHV vu_long
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# define SWAP(x) __swab32(x)
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#endif
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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/* Flash Organization Structure */
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typedef struct OrgDef {
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unsigned int sector_number;
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unsigned int sector_size;
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} OrgDef;
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/* Flash Organizations */
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OrgDef OrgIntel_28F256L18T[] = {
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{4, SZ_32K}, /* 4 * 32kBytes sectors */
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{255, SZ_128K}, /* 255 * 128kBytes sectors */
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};
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/*-----------------------------------------------------------------------
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* Functions
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*/
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unsigned long flash_init (void);
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static ulong flash_get_size (FPW * addr, flash_info_t * info);
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static int write_data (flash_info_t * info, ulong dest, FPW data);
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static void flash_get_offsets (ulong base, flash_info_t * info);
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void inline spin_wheel (void);
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void flash_print_info (flash_info_t * info);
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void flash_unprotect_sectors (FPWV * addr);
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int flash_erase (flash_info_t * info, int s_first, int s_last);
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
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void flash_unlock(flash_info_t * info, int bank);
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int flash_probe(void);
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/*-----------------------------------------------------------------------
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*/
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/* see if flash is ok */
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int flash_probe(void)
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{
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return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0]));
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}
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unsigned long flash_init (void)
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{
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int i;
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ulong size = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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switch (i) {
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case 0:
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
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/* to reset the lock bit */
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flash_unlock(&flash_info[i],i);
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break;
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case 1:
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flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
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flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
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/* to reset the lock bit */
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flash_unlock(&flash_info[i],i);
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break;
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||||
|
||||
default:
|
||||
panic ("configured too many flash banks!\n");
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||||
break;
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}
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size += flash_info[i].size;
|
||||
}
|
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/
|
||||
flash_protect (FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
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||||
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
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||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
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||||
*/
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void flash_unlock(flash_info_t * info, int bank)
|
||||
{
|
||||
int j;
|
||||
if (!bank)
|
||||
j=2; /* leave 0,1 locked for boot bank */
|
||||
else
|
||||
j=0; /* get the whole bank for #2 */
|
||||
|
||||
for (;j<CFG_MAX_FLASH_SECT;j++) {
|
||||
FPWV *addr = (FPWV *) (info->start[j]);
|
||||
if (addr == NULL) {
|
||||
printf("Warning Flash probe failed\n");
|
||||
break;
|
||||
}
|
||||
flash_unprotect_sectors (addr);
|
||||
*addr = (FPW) 0x00500050;/* clear status register */
|
||||
*addr = (FPW) 0x00FF00FF;/* resest to read mode */
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if (i > 254) { /* 255,256,257,258 */
|
||||
r=i;
|
||||
info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE));
|
||||
info->protect[i] = 0;
|
||||
} else {
|
||||
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_INTEL:
|
||||
printf ("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F256L18T:
|
||||
printf ("FLASH 28F256L18T\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i], info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (FPW * addr, flash_info_t * info)
|
||||
{
|
||||
volatile FPW value;
|
||||
/* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0x5555] = (FPW) 0x00AA00AA;
|
||||
addr[0x2AAA] = (FPW) 0x00550055;
|
||||
addr[0x5555] = (FPW) 0x00900090;
|
||||
|
||||
mb ();
|
||||
value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (FPW) INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return(0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
mb ();
|
||||
value = addr[1]; /* device ID */
|
||||
switch (value) {
|
||||
|
||||
case (FPW) (INTEL_ID_28F256L18T): /* 880D */
|
||||
info->flash_id += FLASH_28F256L18T;
|
||||
info->sector_count = 259; /*0-258*/
|
||||
info->size = SZ_32M;
|
||||
break; /* => 32 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) {
|
||||
printf ("** ERROR: sector count %d > max (%d) **\n",
|
||||
info->sector_count, CFG_MAX_FLASH_SECT);
|
||||
info->sector_count = CFG_MAX_FLASH_SECT;
|
||||
}
|
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return(info->size);
|
||||
}
|
||||
|
||||
|
||||
/* unprotects a sector for write and erase
|
||||
* on some intel parts, this unprotects the entire chip, but it
|
||||
* wont hurt to call this additional times per sector...
|
||||
*/
|
||||
void flash_unprotect_sectors (FPWV * addr)
|
||||
{
|
||||
#define PD_FINTEL_WSMS_READY_MASK 0x0080
|
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */
|
||||
|
||||
/* this sends the clear lock bit command */
|
||||
*addr = (FPW) 0x00600060;
|
||||
*addr = (FPW) 0x00D000D0;
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int prot, sect;
|
||||
ulong type, start, last;
|
||||
int rcode = 0;
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
int iflag;
|
||||
#endif
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK);
|
||||
if ((type != FLASH_MAN_INTEL)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
iflag = disable_interrupts ();
|
||||
#endif
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
FPWV *addr = (FPWV *) (info->start[sect]);
|
||||
FPW status;
|
||||
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
flash_unprotect_sectors (addr);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
*addr = (FPW) 0x00500050;/* clear status register */
|
||||
*addr = (FPW) 0x00200020;/* erase setup */
|
||||
*addr = (FPW) 0x00D000D0;/* erase confirm */
|
||||
|
||||
while (((status =
|
||||
*addr) & (FPW) 0x00800080) !=
|
||||
(FPW) 0x00800080) {
|
||||
if (get_timer_masked () >
|
||||
CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
/* suspend erase */
|
||||
*addr = (FPW) 0x00B000B0;
|
||||
/* reset to read mode */
|
||||
*addr = (FPW) 0x00FF00FF;
|
||||
rcode = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear status register cmd. */
|
||||
*addr = (FPW) 0x00500050;
|
||||
*addr = (FPW) 0x00FF00FF;/* resest to read mode */
|
||||
printf (" done\n");
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
#endif
|
||||
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
* 4 - Flash not identified
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
||||
FPW data;
|
||||
int count, i, l, rc, port_width;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return 4;
|
||||
}
|
||||
/* get lower word aligned address */
|
||||
#ifdef FLASH_PORT_WIDTH16
|
||||
wp = (addr & ~1);
|
||||
port_width = 2;
|
||||
#else
|
||||
wp = (addr & ~3);
|
||||
port_width = 4;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
for (; i < port_width && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return(rc);
|
||||
}
|
||||
wp += port_width;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= port_width) {
|
||||
data = 0;
|
||||
for (i = 0; i < port_width; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return(rc);
|
||||
}
|
||||
wp += port_width;
|
||||
cnt -= port_width;
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel ();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return(write_data (info, wp, SWAP (data)));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_data (flash_info_t * info, ulong dest, FPW data)
|
||||
{
|
||||
FPWV *addr = (FPWV *) dest;
|
||||
ulong status;
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
int iflag;
|
||||
#endif
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
|
||||
return(2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
iflag = disable_interrupts ();
|
||||
#endif
|
||||
*addr = (FPW) 0x00400040; /* write setup */
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
/* wait while polling the status register */
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return(1);
|
||||
}
|
||||
}
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
if (iflag)
|
||||
enable_interrupts();
|
||||
#endif
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
void inline spin_wheel (void)
|
||||
{
|
||||
static int p = 0;
|
||||
static char w[] = "\\/-";
|
||||
|
||||
printf ("\010%c", w[p]);
|
||||
(++p == 3) ? (p = 0) : 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
|
||||
/************************************************************
|
||||
* sdelay() - simple spin loop. Will be constant time as
|
||||
* its generally used in 12MHz bypass conditions only. This
|
||||
* is necessary until timers are accessible.
|
||||
*
|
||||
* not inline to increase chances its in cache when called
|
||||
*************************************************************/
|
||||
void sdelay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
/*********************************************************************************
|
||||
* prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
|
||||
* -- called from SRAM, or Flash (using temp SRAM stack).
|
||||
*********************************************************************************/
|
||||
void prcm_init(void)
|
||||
{
|
||||
u32 rev,div;
|
||||
#ifdef CONFIG_PARTIAL_SRAM
|
||||
void (*f_lock_pll) (u32, u32, u32, u32);
|
||||
extern void *_end_vect, *_start;
|
||||
|
||||
f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
|
||||
#endif
|
||||
|
||||
__raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
|
||||
__raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
|
||||
__raw_writel(0, CM_ICLKEN1_CORE);
|
||||
__raw_writel(0, CM_ICLKEN2_CORE);
|
||||
|
||||
__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
|
||||
__raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
|
||||
__raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
|
||||
__raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
|
||||
|
||||
rev = get_cpu_rev();
|
||||
if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
|
||||
div = BUS_DIV_ES1;
|
||||
else
|
||||
div = BUS_DIV;
|
||||
__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
|
||||
sdelay(1000);
|
||||
|
||||
#ifndef CONFIG_PARTIAL_SRAM
|
||||
/* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
|
||||
* but then comes back. If running from Flash this sequence kills you, thus you need
|
||||
* to run it using CONFIG_PARTIAL_SRAM.
|
||||
*/
|
||||
__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
|
||||
wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
|
||||
|
||||
/* set clock selection and dpll dividers. */
|
||||
__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */
|
||||
__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
|
||||
sdelay(10000);
|
||||
__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
|
||||
sdelay(10000);
|
||||
wait_on_value(BIT0|BIT1, BIT2, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */
|
||||
#else
|
||||
/* if running from flash, need to jump to small relocated code area in SRAM.
|
||||
* This is the only safe spot to do configurations from.
|
||||
*/
|
||||
(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
|
||||
#endif
|
||||
|
||||
__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
|
||||
wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */
|
||||
sdelay(1000);
|
||||
}
|
||||
|
||||
/***********************************************
|
||||
* memif_init() - init the gpmc and sdrc
|
||||
* - early init routines, called from flash or
|
||||
* SRAM.
|
||||
***********************************************/
|
||||
void memif_init(void)
|
||||
{
|
||||
sdrc_init();
|
||||
#ifndef CONFIG_PARTIAL_SRAM /* don't init if calling from flash */
|
||||
gpmc_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* mem_ok() - test used to see if timings are correct
|
||||
* for a part. Helps in gussing which part
|
||||
* we are currently using.
|
||||
*******************************************************/
|
||||
u32 mem_ok(void)
|
||||
{ u32 val;
|
||||
__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */
|
||||
__raw_writel(0x12345678, OMAP2420_SDRC_CS0);/* pattern to pos B */
|
||||
val = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
|
||||
if (val != 0) /* see if pos A value changed*/
|
||||
return(0);
|
||||
else
|
||||
return(1);
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* sdrc_init() - init the sdrc chip selects CS0 and CS1
|
||||
* - early init routines, called from flash or
|
||||
* SRAM.
|
||||
*******************************************************/
|
||||
void sdrc_init(void)
|
||||
{
|
||||
#define EARLY_INIT 1
|
||||
do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* do_sdrc_init(): initialize the SDRAM for use.
|
||||
* -called from low level code with stack only.
|
||||
* -code sets up SDRAM timing and muxing for 2422 or 2420.
|
||||
* -optimal settings can be placed here, or redone after i2c
|
||||
* inspection of board info
|
||||
*
|
||||
* !!! When ES1 comes out need to conditionalize RFR value!!!
|
||||
**********************************************************/
|
||||
void do_sdrc_init(u32 offset, u32 early)
|
||||
{
|
||||
u32 cpu, bug=0, rev, shared=0, cs0=0, pmask=0,first=1;
|
||||
sdrc_data_t *sdata; /* do not change type */
|
||||
|
||||
static const sdrc_data_t sdrc_2422 =
|
||||
{
|
||||
H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0, H4_2422_SDRC_ACTIM_CTRLA_0,
|
||||
H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0,
|
||||
H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL
|
||||
};
|
||||
static const sdrc_data_t sdrc_2420 =
|
||||
{
|
||||
H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0, H4_2420_SDRC_ACTIM_CTRLA_0,
|
||||
H4_2420_SDRC_ACTIM_CTRLB_0, H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0,
|
||||
H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL
|
||||
};
|
||||
|
||||
if (offset == SDRC_CS0_OSET)
|
||||
cs0 = shared = 1; /* int regs shared between both chip select */
|
||||
|
||||
cpu = get_cpu_type();
|
||||
|
||||
/* warning generated, though code generation is correct. this may bite later, but is ok for now.
|
||||
* there is only so much C code you can do on stack only operation.
|
||||
*/
|
||||
if (cpu == CPU_2422)
|
||||
sdata = &sdrc_2422;
|
||||
else
|
||||
sdata = &sdrc_2420;
|
||||
__asm__ __volatile__("": : :"memory");
|
||||
#ifdef CONFIG_PARTIAL_SRAM
|
||||
/* u-boot is compiled to run in DDR at 8xxxxxxx. If we use data here which is not pc relative
|
||||
* we need to get the address correct. We need to find the current flash mapping to dress up
|
||||
* the initial pointer load. As long as this is const data we should be ok.
|
||||
*/
|
||||
if(early)
|
||||
sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
|
||||
#endif
|
||||
|
||||
men_combo:
|
||||
|
||||
if (!early && get_mem_type() == DDR_COMBO) { /* combo part has a shared CKE signal, can't use feature */
|
||||
pmask = BIT2;
|
||||
first = 0; /* trigger ddr_combo init */
|
||||
}
|
||||
|
||||
if (shared) {
|
||||
__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
|
||||
__raw_writel(SMART_IDLE|SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */
|
||||
wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
|
||||
__raw_writel(SMART_IDLE, SDRC_SYSCONFIG); /* clear soft reset */
|
||||
__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
|
||||
__raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER);
|
||||
}
|
||||
if (first)
|
||||
__raw_writel(sdata->sdrc_mdcfg_0, SDRC_MCFG_0+offset);
|
||||
else {
|
||||
__raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER);
|
||||
__raw_writel(H4_2420_COMBO_MDCFG_0,SDRC_MCFG_0+offset);
|
||||
}
|
||||
|
||||
if (cs0) {
|
||||
__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_0);
|
||||
__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_0);
|
||||
} else {
|
||||
__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_1);
|
||||
__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_1);
|
||||
}
|
||||
|
||||
__raw_writel(sdata->sdrc_rfr_ctrl, SDRC_RFR_CTRL+offset);
|
||||
|
||||
/* init sequence for _mDDR_ using manual commands (DDR is a bit different) */
|
||||
__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
|
||||
sdelay(5000); /* susposed to be 100us per design spec for mddr*/
|
||||
__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
|
||||
__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
|
||||
__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
|
||||
|
||||
/*
|
||||
* CSx SDRC Mode Register
|
||||
* Burst length = 4 - DDR memory
|
||||
* Serial mode
|
||||
* CAS latency = x
|
||||
*/
|
||||
__raw_writel(sdata->sdrc_mr_0, SDRC_MR_0+offset);
|
||||
|
||||
/* NOTE: ES1 242x _BUG_ DLL */
|
||||
rev = get_cpu_rev();
|
||||
if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
|
||||
bug = BIT0;
|
||||
/* enable & load up DLL with good value for 75MHz, and set phase to 90% */
|
||||
if (shared) {
|
||||
__raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL);
|
||||
__raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL);
|
||||
__raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL);
|
||||
__raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL);
|
||||
}
|
||||
sdelay(9000);
|
||||
if (!first || mem_ok()) /* passed test or 2nd bank init */
|
||||
return;
|
||||
else {
|
||||
first = 0;
|
||||
goto men_combo;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************
|
||||
* gpmc_init(): init gpmc bus
|
||||
* Init GPMC for x16, MuxMode (SDRAM in x32).
|
||||
* This code can only be executed from SRAM or SDRAM.
|
||||
*****************************************************/
|
||||
void gpmc_init(void)
|
||||
{
|
||||
u32 mux=0, mtype, mwidth;
|
||||
|
||||
/* global settings */
|
||||
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
|
||||
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
|
||||
__raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */
|
||||
__raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
|
||||
|
||||
/* discover bus connection from sysboot */
|
||||
if (is_gpmc_muxed() == GPMC_MUXED)
|
||||
mux = BIT9;
|
||||
mtype = get_gpmc0_type();
|
||||
mwidth = get_gpmc0_width();
|
||||
|
||||
/* setup cs0 */
|
||||
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
|
||||
sdelay(1000);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
|
||||
//__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
|
||||
//__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
|
||||
sdelay(2000);
|
||||
|
||||
/* setup cs1 */
|
||||
__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
|
||||
sdelay(1000);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
|
||||
__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
|
||||
sdelay(2000);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,834 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/omap2420.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bits.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/sys_info.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
static void wait_for_command_complete(unsigned int wd_base);
|
||||
|
||||
/*******************************************************
|
||||
* Routine: delay
|
||||
* Description: spinning delay to use before udelay works
|
||||
******************************************************/
|
||||
static inline void delay (unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************/
|
||||
int board_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#ifndef CONFIG_PARTIAL_SRAM
|
||||
s_init(0x0); /* full sram build, never skip clock and sdrc, no point */
|
||||
#else
|
||||
gpmc_init();
|
||||
#endif
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
|
||||
gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: s_init
|
||||
* Description: Does early system init of muxing and clocks.
|
||||
* - Called at time when only stack is available.
|
||||
**********************************************************/
|
||||
void s_init(int skip)
|
||||
{
|
||||
watchdog_init();
|
||||
set_muxconf_regs();
|
||||
delay(100);
|
||||
|
||||
if (!skip)
|
||||
prcm_init();
|
||||
|
||||
peripheral_enable();
|
||||
icache_enable();
|
||||
#ifndef CONFIG_APTIX
|
||||
if (!skip)
|
||||
memif_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Init ethernet (done here so udelay works)
|
||||
********************************************************/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
ether_init(); /* better done here so timers are init'ed */
|
||||
return(0);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: watchdog_init
|
||||
* Description: Shut down watch dogs
|
||||
*****************************************/
|
||||
void watchdog_init(void)
|
||||
{
|
||||
int mode;
|
||||
#define GP (BIT8|BIT9)
|
||||
|
||||
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
|
||||
* I would expect that the ROM takes care of the secure one,
|
||||
* but we will try also. Of the 3 GP ones, 1 can reset us
|
||||
* directly, the other 2 only generate MPU interrupts.
|
||||
*/
|
||||
mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
|
||||
if (mode == GP) {
|
||||
__raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
|
||||
wait_for_command_complete(WD1_BASE);
|
||||
__raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
|
||||
}
|
||||
__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
|
||||
wait_for_command_complete(WD2_BASE);
|
||||
__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
|
||||
|
||||
#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
|
||||
__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
|
||||
wait_for_command_complete(WD3_BASE);
|
||||
__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
|
||||
|
||||
__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
|
||||
wait_for_command_complete(WD4_BASE);
|
||||
__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************************************************
|
||||
* Routine: wait_for_command_complete
|
||||
* Description: Wait for posting to finish on watchdog
|
||||
******************************************************/
|
||||
static void wait_for_command_complete(unsigned int wd_base)
|
||||
{
|
||||
int pending = 1;
|
||||
do {
|
||||
pending = __raw_readl(wd_base+WWPS);
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* Routine:ether_init
|
||||
* Description: take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete.
|
||||
******************************************************************/
|
||||
void ether_init (void)
|
||||
{
|
||||
#ifdef CONFIG_DRIVER_LAN91C96
|
||||
int cnt = 20;
|
||||
|
||||
__raw_writew(0x0, LAN_RESET_REGISTER);
|
||||
do {
|
||||
__raw_writew(0x1, LAN_RESET_REGISTER);
|
||||
udelay (100);
|
||||
if (cnt == 0)
|
||||
goto h4reset_err_out;
|
||||
--cnt;
|
||||
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
|
||||
|
||||
cnt = 20;
|
||||
|
||||
do {
|
||||
__raw_writew(0x0, LAN_RESET_REGISTER);
|
||||
udelay (100);
|
||||
if (cnt == 0)
|
||||
goto h4reset_err_out;
|
||||
--cnt;
|
||||
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
|
||||
udelay (1000);
|
||||
|
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
|
||||
udelay (1000);
|
||||
|
||||
h4reset_err_out:
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
* Routine: dram_init
|
||||
* Description: sets uboots idea of sdram size
|
||||
**********************************************/
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
unsigned int size0=0,size1=0;
|
||||
u32 mtype, btype;
|
||||
#define NOT_EARLY 0
|
||||
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
|
||||
|
||||
btype = get_board_type();
|
||||
mtype = get_mem_type();
|
||||
|
||||
display_board_info(btype);
|
||||
if (btype == BOARD_H4_MENELAUS)
|
||||
update_mux(btype,mtype);
|
||||
|
||||
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
|
||||
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
|
||||
size0 = size1 = SZ_32M;
|
||||
} else
|
||||
size0 = SZ_64M;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = size0;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = size1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**********************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers
|
||||
* specific to the hardware
|
||||
*********************************************************/
|
||||
void set_muxconf_regs (void)
|
||||
{
|
||||
muxSetupSDRC();
|
||||
muxSetupGPMC();
|
||||
muxSetupUsb0();
|
||||
muxSetupUart3();
|
||||
muxSetupI2C1();
|
||||
muxSetupUART1();
|
||||
muxSetupLCD();
|
||||
muxSetupCamera();
|
||||
muxSetupMMCSD();
|
||||
muxSetupTouchScreen();
|
||||
muxSetupHDQ();
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* Routine: peripheral_enable
|
||||
* Description: Enable the clks & power for perifs (GPT2, UART1,...)
|
||||
******************************************************************/
|
||||
void peripheral_enable(void)
|
||||
{
|
||||
unsigned int v, if_clks=0, func_clks=0;
|
||||
|
||||
/* Enable GP2 timer.*/
|
||||
if_clks |= BIT4;
|
||||
func_clks |= BIT4;
|
||||
v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
|
||||
__raw_writel(v, CM_CLKSEL2_CORE);
|
||||
__raw_writel(0x1, CM_CLKSEL_WKUP);
|
||||
|
||||
#ifdef CFG_NS16550
|
||||
/* Enable UART1 clock */
|
||||
func_clks |= BIT21;
|
||||
if_clks |= BIT21;
|
||||
#endif
|
||||
v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
|
||||
__raw_writel(v,CM_ICLKEN1_CORE );
|
||||
v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
|
||||
__raw_writel(v, CM_FCLKEN1_CORE);
|
||||
delay(1000);
|
||||
|
||||
#ifndef KERNEL_UPDATED
|
||||
{
|
||||
#define V1 0xffffffff
|
||||
#define V2 0x00000007
|
||||
|
||||
__raw_writel(V1, CM_FCLKEN1_CORE);
|
||||
__raw_writel(V2, CM_FCLKEN2_CORE);
|
||||
__raw_writel(V1, CM_ICLKEN1_CORE);
|
||||
__raw_writel(V1, CM_ICLKEN2_CORE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUsb0 (ostboot)
|
||||
* Description: Setup usb muxing
|
||||
*****************************************/
|
||||
void muxSetupUsb0(void)
|
||||
{
|
||||
volatile uint8 *MuxConfigReg;
|
||||
volatile uint32 *otgCtrlReg;
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
/* setup for USB VBus detection */
|
||||
otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
|
||||
*otgCtrlReg |= 0x00040000; /* bit 18 */
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUart3 (ostboot)
|
||||
* Description: Setup uart3 muxing
|
||||
*****************************************/
|
||||
void muxSetupUart3(void)
|
||||
{
|
||||
volatile uint8 *MuxConfigReg;
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
|
||||
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
|
||||
*MuxConfigReg &= (uint8)(~0x1F);
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupI2C1 (ostboot)
|
||||
* Description: Setup i2c muxing
|
||||
*****************************************/
|
||||
void muxSetupI2C1(void)
|
||||
{
|
||||
volatile unsigned char *MuxConfigReg;
|
||||
|
||||
/* I2C1 Clock pin configuration, PIN = M19 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* I2C1 Data pin configuration, PIN = L15 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* Pull-up required on data line */
|
||||
/* external pull-up already present. */
|
||||
/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupUART1 (ostboot)
|
||||
* Description: Set up uart1 muxing
|
||||
*****************************************/
|
||||
void muxSetupUART1(void)
|
||||
{
|
||||
volatile unsigned char *MuxConfigReg;
|
||||
|
||||
/* UART1_CTS pin configuration, PIN = D21 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
|
||||
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
||||
|
||||
/* UART1_RTS pin configuration, PIN = H21 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
|
||||
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
||||
|
||||
/* UART1_TX pin configuration, PIN = L20 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
|
||||
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
||||
|
||||
/* UART1_RX pin configuration, PIN = T21 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
|
||||
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
||||
}
|
||||
|
||||
/****************************************
|
||||
* Routine: muxSetupLCD (ostboot)
|
||||
* Description: Setup lcd muxing
|
||||
*****************************************/
|
||||
void muxSetupLCD(void)
|
||||
{
|
||||
volatile unsigned char *MuxConfigReg;
|
||||
|
||||
/* LCD_D0 pin configuration, PIN = Y7 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D1 pin configuration, PIN = P10 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D2 pin configuration, PIN = V8 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D3 pin configuration, PIN = Y8 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D4 pin configuration, PIN = W8 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D5 pin configuration, PIN = R10 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D6 pin configuration, PIN = Y9 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D7 pin configuration, PIN = V9 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D8 pin configuration, PIN = W9 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D9 pin configuration, PIN = P11 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D10 pin configuration, PIN = V10 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D11 pin configuration, PIN = Y10 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D12 pin configuration, PIN = W10 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D13 pin configuration, PIN = R11 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D14 pin configuration, PIN = V11 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D15 pin configuration, PIN = W11 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
|
||||
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
|
||||
|
||||
/* LCD_D16 pin configuration, PIN = P12 */
|
||||
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
|
||||