TI DaVinci: Driver for the davinci SPI controller
This adds a driver for the SPI controller found on davinci based SoCs from Texas Instruments. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sekhar Nori
Tom Rix
parent
44d8025622
commit
8ed5885693
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@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
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COBJS-$(CONFIG_CF_SPI) += cf_spi.o
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COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
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COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
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COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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@ -0,0 +1,223 @@
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Driver for SPI controller on DaVinci. Based on atmel_spi.c
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* by Atmel Corporation
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include "davinci_spi.h"
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct davinci_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = malloc(sizeof(*ds));
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if (!ds)
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return NULL;
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ds->slave.bus = bus;
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ds->slave.cs = cs;
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ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
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ds->freq = max_hz;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int scalar, data1_reg_val = 0;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* clock signal delayed by half clk cycle,
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* clock low in idle state - Mode 0,
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* MSB shifted out first
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*/
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/* hold cs active at end of transfer until explicitly de-asserted */
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data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT);
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writel(data1_reg_val, &ds->regs->dat1);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int len, data1_reg_val = readl(&ds->regs->dat1);
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int ret, i;
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const u8 *txp = dout; /* dout can be NULL for read operation */
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u8 *rxp = din; /* din can be NULL for write operation */
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ret = 0;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* It's not clear how non-8-bit-aligned transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface - here we terminate on receiving such a
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* transfer request.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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/* do an empty read to clear the current contents */
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readl(&ds->regs->buf);
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/* keep writing and reading 1 byte until done */
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for (i = 0; i < len; i++) {
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/* wait till TXFULL is asserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK);
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/* write the data */
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data1_reg_val &= ~0xFFFF;
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if (txp) {
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data1_reg_val |= *txp;
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txp++;
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}
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/*
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* Write to DAT1 is required to keep the serial transfer going.
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* We just terminate when we reach the end.
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*/
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if ((i == (len - 1)) && (flags & SPI_XFER_END)) {
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/* clear CS hold */
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writel(data1_reg_val &
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~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1);
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} else {
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/* enable CS hold */
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data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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writel(data1_reg_val, &ds->regs->dat1);
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}
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/* read the data - wait for data availability */
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while (readl(&ds->regs->buf) & SPIBUF_RXEMPTY_MASK);
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if (rxp) {
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*rxp = readl(&ds->regs->buf) & 0xFF;
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rxp++;
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} else {
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/* simply drop the read character */
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readl(&ds->regs->buf);
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}
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}
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return 0;
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out:
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if (flags & SPI_XFER_END) {
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writel(data1_reg_val &
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~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1);
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}
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return 0;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Register definitions for the DaVinci SPI Controller
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _DAVINCI_SPI_H_
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#define _DAVINCI_SPI_H_
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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#define BIT(x) (1 << (x))
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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#define SPIGCR0_SPIRST_MASK 0x0
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/* SPIGCR0 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_EN0FUN_MASK BIT(0)
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/* SPIFMT0 */
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#define SPIFMT_SHIFTDIR_SHIFT 20
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#define SPIFMT_POLARITY_SHIFT 17
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#define SPIFMT_PHASE_SHIFT 16
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSNR_SHIFT 16
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/* SPIDELAY */
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#define SPI_C2TDELAY_SHIFT 24
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#define SPI_T2CDELAY_SHIFT 16
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/* SPIBUF */
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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#define SPIBUF_TXFULL_MASK BIT(29)
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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unsigned int freq;
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};
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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#endif /* _DAVINCI_SPI_H_ */
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