diff --git a/CREDITS b/CREDITS
index 7af1b806a..8558a4012 100644
--- a/CREDITS
+++ b/CREDITS
@@ -479,3 +479,9 @@ N: Michal Simek
 E: monstr@monstr.eu
 D: Support for Microblaze, ML401, XUPV2P board
 W: www.monstr.eu
+
+N: TsiChung Liew
+E: Tsi-Chung.Liew@freescale.com
+D: Support for ColdFire MCF532x
+W: www.freescale.com
+
diff --git a/MAKEALL b/MAKEALL
old mode 100755
new mode 100644
index 0e4e74409..22c6c6da2
--- a/MAKEALL
+++ b/MAKEALL
@@ -306,7 +306,7 @@ LIST_microblaze="	\
 LIST_coldfire="	\
 	cobra5272	EB+MCF-EV123	EB+MCF-EV123_internal		\
 	idmr		M5271EVB	M5272C3		M5282EVB	\
-	TASREG		r5200		M5271EVB			\
+	TASREG		r5200		M5271EVB 	M5329EVB	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
old mode 100644
new mode 100755
index d5e220aad..8a728a432
--- a/Makefile
+++ b/Makefile
@@ -207,9 +207,11 @@ LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/net/libnet.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
 endif
+LIBS += drivers/serial/libserial.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/drivers/libpostdrivers.a
 LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
@@ -1637,6 +1639,18 @@ TASREG_config :		unconfig
 r5200_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
 
+M5329AFEE_config \
+M5329BFEE_config :	unconfig
+	@case "$@" in \
+	M5329AFEE_config)	NAND=0;; \
+	M5329BFEE_config)	NAND=16;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${NAND}" != "0" ] ; then \
+		echo "#define NANDFLASH_SIZE	$${NAND}" >> include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
+
 #########################################################################
 ## MPC83xx Systems
 #########################################################################
diff --git a/README b/README
index bb5b46e33..dd12cd7ee 100644
--- a/README
+++ b/README
@@ -136,6 +136,7 @@ Directory Hierarchy:
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
+  - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
   - mips	Files specific to MIPS CPUs
   - mpc5xx	Files specific to Freescale MPC5xx  CPUs
   - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
@@ -251,6 +252,10 @@ The following options need to be configured:
 		CONFIG_PXA250
 		CONFIG_CPU_MONAHANS
 
+		ColdFire based CPUs:
+		--------------------
+		CONFIG_M5329
+
 		MicroBlaze based CPUs:
 		----------------------
 		CONFIG_MICROBLAZE
diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile
new file mode 100644
index 000000000..f94ee9d13
--- /dev/null
+++ b/board/freescale/m5329evb/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk
new file mode 100644
index 000000000..ce014edca
--- /dev/null
+++ b/board/freescale/m5329evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0
diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c
new file mode 100644
index 000000000..7d3b0e84d
--- /dev/null
+++ b/board/freescale/m5329evb/flash.c
@@ -0,0 +1,643 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef CFG_FLASH_CFI
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM   0x00100010
+#define INTEL_ERASE     0x00200020
+#define INTEL_WRSETUP	0x00400040
+#define INTEL_CLEAR     0x00500050
+#define INTEL_LOCKBIT   0x00600060
+#define INTEL_PROTECT   0x00010001
+#define INTEL_STATUS    0x00700070
+#define INTEL_READID    0x00900090
+#define INTEL_CFIQRY	0x00980098
+#define INTEL_SUSERASE	0x00B000B0
+#define INTEL_PROTPROG	0x00C000C0
+#define INTEL_CONFIRM   0x00D000D0
+#define INTEL_RESET     0x00FF00FF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED  0x00800080
+#define INTEL_OK        0x00800080
+#define INTEL_ERASESUS  0x00600060
+#define INTEL_WSM_SUS   (INTEL_FINISHED | INTEL_ERASESUS)
+
+/* 28F160C3B CFI Data offset - This could vary */
+#define INTEL_CFI_MFG	0x00	/* Manufacturer ID */
+#define INTEL_CFI_PART	0x01	/* Product ID */
+#define INTEL_CFI_LOCK  0x02	/* */
+#define INTEL_CFI_TWPRG 0x1F	/* Typical Single Word Program Timeout 2^n us */
+#define INTEL_CFI_MBUFW 0x20	/* Typical Max Buffer Write Timeout 2^n us */
+#define INTEL_CFI_TERB	0x21	/* Typical Block Erase Timeout 2^n ms */
+#define INTEL_CFI_MWPRG 0x23	/* Maximum Word program timeout 2^n us */
+#define INTEL_CFI_MERB  0x25	/* Maximum Block Erase Timeout 2^n s */
+#define INTEL_CFI_SIZE	0x27	/* Device size 2^n bytes */
+#define INTEL_CFI_BANK	0x2C	/* Number of Bank */
+#define INTEL_CFI_SZ1A	0x2F	/* Block Region Size */
+#define INTEL_CFI_SZ1B	0x30
+#define INTEL_CFI_SZ2A	0x33
+#define INTEL_CFI_SZ2B	0x34
+#define INTEL_CFI_BLK1	0x2D	/* Number of Blocks */
+#define INTEL_CFI_BLK2	0x31
+
+#define WR_BLOCK        0x20
+
+#define SYNC			__asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int flash_cmd_rd(FPWV * addr, int index);
+int write_data(flash_info_t * info, ulong dest, FPW data);
+void flash_sync_real_protect(flash_info_t * info);
+uchar intel_sector_protected(flash_info_t * info, ushort sector);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+	FPWV *flash_addr[CFG_MAX_FLASH_BANKS];
+	ulong size;
+	int i;
+
+	flash_addr[0] = (FPW *) CFG_FLASH0_BASE;
+#ifdef CFG_FLASH1_BASE
+	flash_addr[1] = (FPW *) CFG_FLASH1_BASE;
+#endif
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		size = flash_get_size(flash_addr[i], &flash_info[i]);
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			      flash_info[i].start[0] + size - 1,
+			      &flash_info[0]);
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf("28F160C3B\n");
+		break;
+	case FLASH_28F160C3T:
+		printf("28F160C3T\n");
+		break;
+	case FLASH_28F320C3B:
+		printf("28F320C3B\n");
+		break;
+	case FLASH_28F320C3T:
+		printf("28F320C3T\n");
+		break;
+	case FLASH_28F640C3B:
+		printf("28F640C3B\n");
+		break;
+	case FLASH_28F640C3T:
+		printf("28F640C3T\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		return;
+	}
+
+	if (info->size > 0x100000) {
+		int remainder;
+
+		printf("  Size: %ld", info->size >> 20);
+
+		remainder = (info->size % 0x100000);
+		if (remainder) {
+			remainder >>= 10;
+			remainder = (int)((float)
+					  (((float)remainder / (float)1024) *
+					   10000));
+			printf(".%d ", remainder);
+		}
+
+		printf("MB in %d Sectors\n", info->sector_count);
+	} else
+		printf("  Size: %ld KB in %d Sectors\n",
+		       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	int intel = 0;
+	u16 value;
+	static int bank = 0;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+	*addr = (FPW) INTEL_READID;
+
+	switch (addr[INTEL_CFI_MFG] & 0xff) {
+	case (ushort) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		value = addr[INTEL_CFI_PART];
+		intel = 1;
+		break;
+	default:
+		printf("Unknown Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = (FPW) INTEL_RESET;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+	case (u16) INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		break;
+	case (u16) INTEL_ID_28F160C3T:
+		info->flash_id += FLASH_28F160C3T;
+		break;
+	case (u16) INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		break;
+	case (u16) INTEL_ID_28F320C3T:
+		info->flash_id += FLASH_28F320C3T;
+		break;
+	case (u16) INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		break;
+	case (u16) INTEL_ID_28F640C3T:
+		info->flash_id += FLASH_28F640C3T;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (intel) {
+		/* Intel spec. under CFI section */
+		u32 sz, size, offset;
+		int sec, sectors, bs;
+		int part, i, j, cnt;
+
+		part = flash_cmd_rd(addr, INTEL_CFI_BANK);
+
+		/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
+		 * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
+		 * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
+		 */
+		offset = (u32) addr;
+		sectors = sec = 0;
+		size = sz = cnt = 0;
+		for (i = 0; i < part; i++) {
+			bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) |
+			       addr[INTEL_CFI_SZ1A + i * 4]) * 0x100);
+			sec = addr[INTEL_CFI_BLK1 + i * 4] + 1;
+			sz = bs * sec;
+
+			for (j = 0; j < sec; j++) {
+				info->start[cnt++] = offset;
+				offset += bs;
+			}
+
+			sectors += sec;
+			size += sz;
+		}
+		info->sector_count = sectors;
+		info->size = size;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+
+	return (info->size);
+}
+
+int flash_cmd_rd(FPWV * addr, int index)
+{
+	return (int)addr[index];
+}
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+void flash_sync_real_protect(flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+uchar intel_sector_protected(flash_info_t * info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	/*udelay(1); */
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer(0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			*addr = (FPW) INTEL_RESET;	/* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector];
+	ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		type = (info->flash_id & FLASH_VENDMASK);
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	start = get_timer(0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			int min = 0;
+
+			printf("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			*addr = (FPW) INTEL_READID;
+			min = addr[INTEL_CFI_TERB];
+			min = 1 << min;	/* ms */
+			min = (min / info->sector_count) * 1000;
+
+			/* start erase block */
+			*addr = (FPW) INTEL_CLEAR;	/* clear status register */
+			*addr = (FPW) INTEL_ERASE;	/* erase setup */
+			*addr = (FPW) INTEL_CONFIRM;	/* erase confirm */
+
+			while ((*addr & (FPW) INTEL_FINISHED) !=
+			       (FPW) INTEL_FINISHED) {
+
+				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = (FPW) INTEL_SUSERASE;	/* suspend erase     */
+					*addr = (FPW) INTEL_RESET;	/* reset to read mode */
+
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) INTEL_RESET;	/* resest to read mode          */
+
+			printf(" done\n");
+		}
+	}
+
+	return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		{
+			ulong cp, wp;
+			FPW data;
+			int i, l, rc, port_width;
+
+			/* get lower word aligned address */
+			wp = addr;
+			port_width = 1;
+
+			/*
+			 * handle unaligned start bytes
+			 */
+			if ((l = addr - wp) != 0) {
+				data = 0;
+				for (i = 0, cp = wp; i < l; ++i, ++cp) {
+					data = (data << 8) | (*(uchar *) cp);
+				}
+
+				for (; i < port_width && cnt > 0; ++i) {
+					data = (data << 8) | *src++;
+					--cnt;
+					++cp;
+				}
+
+				for (; cnt == 0 && i < port_width; ++i, ++cp)
+					data = (data << 8) | (*(uchar *) cp);
+
+				if ((rc = write_data(info, wp, data)) != 0)
+					return (rc);
+
+				wp += port_width;
+			}
+
+			/* handle word aligned part */
+			while (cnt >= 2) {
+				data = *((FPW *) src);
+
+				if ((rc =
+				     write_data(info, (ulong) ((FPWV *) wp),
+						(FPW) data)) != 0) {
+					return (rc);
+				}
+
+				src += sizeof(FPW);
+				wp += sizeof(FPW);
+				cnt -= sizeof(FPW);
+			}
+
+			if (cnt == 0)
+				return ERR_OK;
+
+			/*
+			 * handle unaligned tail bytes
+			 */
+			data = 0;
+			for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+				data = (data >> 8) | (*src++ << 8);
+				--cnt;
+			}
+			for (; i < 2; ++i, ++cp) {
+				data |= (*(uchar *) cp);
+			}
+
+			return write_data(info, (ulong) ((FPWV *) wp),
+					  (FPW) data);
+
+		}		/* case FLASH_MAN_INTEL */
+
+	}			/* switch */
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_data(flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%lx)\n", (ulong) addr,
+		       (ulong) * addr);
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = (int)disable_interrupts();
+
+	*addr = (FPW) INTEL_CLEAR;
+	*addr = (FPW) INTEL_RESET;
+
+	*addr = (FPW) INTEL_WRSETUP;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) INTEL_SUSERASE;	/* suspend mode */
+			*addr = (FPW) INTEL_CLEAR;	/* clear status */
+			*addr = (FPW) INTEL_RESET;	/* reset */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) INTEL_CLEAR;	/* clear status */
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		*addr = (FPW) INTEL_RESET;	/* make sure in read mode */
+		*addr = (FPW) INTEL_LOCKBIT;	/* lock command setup */
+
+		if (prot)
+			*addr = (FPW) INTEL_PROTECT;	/* lock sector */
+		else
+			*addr = (FPW) INTEL_CONFIRM;	/* unlock sector */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) INTEL_READID;
+
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) INTEL_PROTECT;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) INTEL_PROTECT)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif				/* CFG_FLASH_PROTECTION */
+#endif				/* CFG_FLASH_CFI */
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
new file mode 100644
index 000000000..4ccea30d6
--- /dev/null
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale FireEngine 5329 EVB\n");
+	return 0;
+};
+
+long int initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CFG_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CFG_SDRAM_BASE | i);
+	sdram->cfg1 = CFG_SDRAM_CFG1;
+	sdram->cfg2 = CFG_SDRAM_CFG2;
+
+	/* Issue PALL */
+	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+
+	/* Issue LEMR */
+	sdram->mode = CFG_SDRAM_EMOD;
+	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+
+	sdram->mode = CFG_SDRAM_MODE;
+
+	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_CFI
+void sync(void)
+{
+	/* This sync function is PowerPC intruction,
+	   coldfire does not have this instruction. Dummy function */
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+	} else {
+		gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		gpio->par_feci2c &=
+		    ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | \
+						(REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
+						(REG & 0x1f) << 18) | \
+						(VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+	volatile fec_t *fecp = (fec_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	volatile fec_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fec_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_s *info = dev->priv;
+	int phyaddr, pass;
+	uint phyno, phytype;
+
+	if (info->phyname_init)
+		return info->phy_addr;
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_DP83848VV:
+					strcpy(info->phy_name,
+					       STR_ID_DP83848VV);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_DP83848VV:
+					printf(STR_ID_DP83848VV);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+void mii_init(void)
+{
+	volatile fec_t *fecp;
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fec_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr,
+		       unsigned char reg, unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr,
+			unsigned char reg, unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CFG_CMD_NET, FEC_ENET & NET_MULTI */
diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds
new file mode 100644
index 000000000..9b994a09d
--- /dev/null
+++ b/board/freescale/m5329evb/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf532x/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    lib_m68k/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index d97c09e88..9651b3097 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -207,6 +207,59 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_M68K) /* M68K */
+
+int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+	print_num ("memstart",		(ulong)bd->bi_memstart);
+	print_num ("memsize",		(ulong)bd->bi_memsize);
+	print_num ("flashstart",	(ulong)bd->bi_flashstart);
+	print_num ("flashsize",		(ulong)bd->bi_flashsize);
+	print_num ("flashoffset",	(ulong)bd->bi_flashoffset);
+#if defined(CFG_INIT_RAM_ADDR)
+	print_num ("sramstart",	    (ulong)bd->bi_sramstart);
+	print_num ("sramsize",	    (ulong)bd->bi_sramsize);
+#endif
+#if defined(CFG_MBAR)
+	print_num ("mbar",	    bd->bi_mbar_base	);
+#endif
+#if defined(CFG_CMD_NET)
+	puts ("ethaddr     =");
+	for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+	}
+
+#if defined(CONFIG_HAS_ETH1)
+	puts ("\neth1addr    =");
+	for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
+	}
+#endif
+
+#if defined(CONFIG_HAS_ETH2)
+       puts ("\neth2addr    =");
+       for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+	}
+#endif
+
+#if defined(CONFIG_HAS_ETH3)
+       puts ("\neth3addr    =");
+       for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
+	}
+#endif
+
+	puts ("\nip_addr     = ");
+	print_IPaddr (bd->bi_ip_addr);
+#endif	/* CFG_CMD_NET */
+	printf ("\nbaudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else /* ! PPC, which leaves MIPS */
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
diff --git a/common/cmd_mii.c b/common/cmd_mii.c
index e6595360c..c3f43d7f4 100644
--- a/common/cmd_mii.c
+++ b/common/cmd_mii.c
@@ -438,7 +438,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	int		rcode = 0;
 	char		*devname;
 
-#ifdef CONFIG_8xx
+#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x)
 	mii_init ();
 #endif
 
diff --git a/cpu/mcf532x/Makefile b/cpu/mcf532x/Makefile
new file mode 100644
index 000000000..452848d32
--- /dev/null
+++ b/cpu/mcf532x/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB	= lib$(CPU).a
+
+START	=
+COBJS	= cpu.o speed.o cpu_init.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk
new file mode 100644
index 000000000..ba324a894
--- /dev/null
+++ b/cpu/mcf532x/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+PLATFORM_CPPFLAGS += -m5307 -fPIC
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
new file mode 100644
index 000000000..071c50304
--- /dev/null
+++ b/cpu/mcf532x/cpu.c
@@ -0,0 +1,134 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+
+#include <asm/immap_5329.h>
+#include <asm/m5329.h>
+
+int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	wdp->cr = 0;
+	udelay(1000);
+
+	/* enable watchdog, set timeout to 0 and wait */
+	wdp->cr = WTM_WCR_EN;
+	while (1) ;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+	u16 msk;
+	u16 id = 0;
+	u8 ver;
+
+	puts("CPU:   ");
+	msk = (ccm->cir >> 6);
+	ver = (ccm->cir & 0x003f);
+	switch (msk) {
+	case 0x54:
+		id = 5329;
+		break;
+	case 0x59:
+		id = 5328;
+		break;
+	case 0x61:
+		id = 5327;
+		break;
+	}
+
+	if (id) {
+		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
+		       ver);
+		printf("       CPU CLK %d Mhz BUS CLK %d Mhz\n",
+		       (int)(gd->cpu_clk / 1000000),
+		       (int)(gd->bus_clk / 1000000));
+	}
+
+	return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	wdp->sr = 0x5555;	/* Count register */
+}
+
+int watchdog_disable(void)
+{
+	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+
+	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
+	wdp->cr |= WTM_WCR_HALTED;	/* halted watchdog timer */
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	u32 wdog_module = 0;
+
+	/* set timeout and enable watchdog */
+	wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+	wdog_module |= (wdog_module / 8192);
+	wdp->mr = wdog_module;
+
+	wdp->cr = WTM_WCR_EN;
+	puts("WATCHDOG:enabled\n");
+
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+
+#ifdef CONFIG_MCFINTC
+int interrupt_init(void)
+{
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	/* Make sure all interrupts are disabled */
+	intp->imrh0 |= 0xFFFFFFFF;
+	intp->imrl0 |= 0xFFFFFFFF;
+
+	enable_interrupts();
+	return 0;
+}
+#endif				/* CONFIG_MCFINTC */
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
new file mode 100644
index 000000000..6319658c0
--- /dev/null
+++ b/cpu/mcf532x/cpu_init.c
@@ -0,0 +1,126 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+
+	/* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+	wdog->cr = 0;
+#endif
+
+	scm1->mpr0 = 0x77777777;
+	scm2->pacra = 0;
+	scm2->pacrb = 0;
+	scm2->pacrc = 0;
+	scm2->pacrd = 0;
+	scm2->pacre = 0;
+	scm2->pacrf = 0;
+	scm2->pacrg = 0;
+	scm1->pacrh = 0;
+
+	/* Setup Ports: */
+	switch (CFG_UART_PORT) {
+	case 0:
+		gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		break;
+	case 1:
+		gpio->par_uart =
+		    (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		break;
+	case 2:
+		gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+		break;
+	}
+
+	/* Port configuration */
+	gpio->par_cs = 0x3E;
+
+#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
+	fbcs->csar0 = CFG_CS0_BASE;
+	fbcs->cscr0 = CFG_CS0_CTRL;
+	fbcs->csmr0 = CFG_CS0_MASK;
+#endif
+
+#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+	/* Latch chipselect */
+	fbcs->csar1 = CFG_CS1_BASE;
+	fbcs->cscr1 = CFG_CS1_CTRL;
+	fbcs->csmr1 = CFG_CS1_MASK;
+#endif
+
+#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+	fbcs->csar2 = CFG_CS2_BASE;
+	fbcs->cscr2 = CFG_CS2_CTRL;
+	fbcs->csmr2 = CFG_CS2_MASK;
+#endif
+
+#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+	fbcs->csar3 = CFG_CS3_BASE;
+	fbcs->cscr3 = CFG_CS3_CTRL;
+	fbcs->csmr3 = CFG_CS3_MASK;
+#endif
+
+#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+	fbcs->csar4 = CFG_CS4_BASE;
+	fbcs->cscr4 = CFG_CS4_CTRL;
+	fbcs->csmr4 = CFG_CS4_MASK;
+#endif
+
+#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+	fbcs->csar5 = CFG_CS5_BASE;
+	fbcs->cscr5 = CFG_CS5_CTRL;
+	fbcs->csmr5 = CFG_CS5_MASK;
+#endif
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	/*icache_enable(); */
+	return (0);
+}
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
new file mode 100644
index 000000000..c4ba7ec66
--- /dev/null
+++ b/cpu/mcf532x/speed.c
@@ -0,0 +1,222 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+
+/* PLL min/max specifications */
+#define MAX_FVCO            500000	/* KHz */
+#define MAX_FSYS            80000	/* KHz */
+#define MIN_FSYS            58333	/* KHz */
+#define FREF    	        16000	/* KHz */
+#define MAX_MFD             135	/* Multiplier */
+#define MIN_MFD             88	/* Multiplier */
+#define BUSDIV  	        6	/* Divider */
+/*
+ * Low Power Divider specifications
+ */
+#define MIN_LPD     (1 << 0)	/* Divider (not encoded) */
+#define MAX_LPD     (1 << 15)	/* Divider (not encoded) */
+#define DEFAULT_LPD (1 << 1)	/* Divider (not encoded) */
+
+/*
+ * Get the value of the current system clock
+ *
+ * Parameters:
+ *  none
+ *
+ * Return Value:
+ *  The current output system frequency
+ */
+int get_sys_clock(void)
+{
+	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	int divider;
+
+	/* Test to see if device is in LIMP mode */
+	if (ccm->misccr & CCM_MISCCR_LIMP) {
+		divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+		return (FREF / (2 << divider));
+	} else {
+		return ((FREF * pll->pfdr) / (BUSDIV * 4));
+	}
+}
+
+/*
+ * Initialize the Low Power Divider circuit
+ *
+ * Parameters:
+ *  div     Desired system frequency divider
+ *
+ * Return Value:
+ *  The resulting output system frequency
+ */
+int clock_limp(int div)
+{
+	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+	u32 temp;
+
+	/* Check bounds of divider */
+	if (div < MIN_LPD)
+		div = MIN_LPD;
+	if (div > MAX_LPD)
+		div = MAX_LPD;
+
+	/* Save of the current value of the SSIDIV so we don't overwrite the value */
+	temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+
+	/* Apply the divider to the system clock */
+	ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+
+	ccm->misccr |= CCM_MISCCR_LIMP;
+
+	return (FREF / (3 * (1 << div)));
+}
+
+/*
+ * Exit low power LIMP mode
+ *
+ * Parameters:
+ *  div     Desired system frequency divider
+ *
+ * Return Value:
+ *  The resulting output system frequency
+ */
+int clock_exit_limp(void)
+{
+	volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+	int fout;
+
+	/* Exit LIMP mode */
+	ccm->misccr &= (~CCM_MISCCR_LIMP);
+
+	/* Wait for PLL to lock */
+	while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
+
+	fout = get_sys_clock();
+
+	return fout;
+}
+
+/* Initialize the PLL
+ *
+ * Parameters:
+ *  fref    PLL reference clock frequency in KHz
+ *  fsys    Desired PLL output frequency in KHz
+ *  flags   Operating parameters
+ *
+ * Return Value:
+ *  The resulting output system frequency
+ */
+int clock_pll(int fsys, int flags)
+{
+	volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	int fref, temp, fout, mfd;
+	u32 i;
+
+	fref = FREF;
+
+	if (fsys == 0) {
+		/* Return current PLL output */
+		mfd = pll->pfdr;
+
+		return (fref * mfd / (BUSDIV * 4));
+	}
+
+	/* Check bounds of requested system clock */
+	if (fsys > MAX_FSYS)
+		fsys = MAX_FSYS;
+
+	if (fsys < MIN_FSYS)
+		fsys = MIN_FSYS;
+
+	/* Multiplying by 100 when calculating the temp value,
+	   and then dividing by 100 to calculate the mfd allows
+	   for exact values without needing to include floating
+	   point libraries. */
+	temp = (100 * fsys) / fref;
+	mfd = (4 * BUSDIV * temp) / 100;
+
+	/* Determine the output frequency for selected values */
+	fout = ((fref * mfd) / (BUSDIV * 4));
+
+	/*
+	 * Check to see if the SDRAM has already been initialized.
+	 * If it has then the SDRAM needs to be put into self refresh
+	 * mode before reprogramming the PLL.
+	 */
+	/* Put SDRAM into self refresh mode */
+/*	if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/
+
+	/*
+	 * Initialize the PLL to generate the new system clock frequency.
+	 * The device must be put into LIMP mode to reprogram the PLL.
+	 */
+
+	/* Enter LIMP mode */
+	clock_limp(DEFAULT_LPD);
+
+	/* Reprogram PLL for desired fsys */
+	pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+
+	pll->pfdr = mfd;
+
+	/* Exit LIMP mode */
+	clock_exit_limp();
+
+	/*
+	 * Return the SDRAM to normal operation if it is in use.
+	 */
+	/* Exit self refresh mode */
+/*	if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
+	MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/
+
+	/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
+	*sdram_workaround = CFG_SDRAM_BASE;
+	/* wait for DQS logic to relock */
+	for (i = 0; i < 0x200; i++) ;
+
+	return fout;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock and gd->bus_clk
+ */
+int get_clocks(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
+	gd->cpu_clk = (gd->bus_clk * 3);
+	return (0);
+}
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
new file mode 100644
index 000000000..d36d076cf
--- /dev/null
+++ b/cpu/mcf532x/start.S
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
+ * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include "version.h"
+
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
+#endif
+
+#define _START	_start
+#define _FAULT	_fault
+
+
+#define SAVE_ALL						\
+	move.w	#0x2700,%sr;		/* disable intrs */	\
+	subl	#60,%sp;		/* space for 15 regs */ \
+	moveml	%d0-%d7/%a0-%a6,%sp@;
+
+#define RESTORE_ALL						\
+	moveml	%sp@,%d0-%d7/%a0-%a6;				\
+	addl	#60,%sp;		/* space for 15 regs */ \
+	rte;
+
+
+.text
+/*
+ *	Vector table. This is used for initial platform startup.
+ *	These vectors are to catch any un-intended traps.
+ */
+_vectors:
+
+INITSP:     .long	0x00000000  /* Initial SP */
+INITPC:     .long   _START      /* Initial PC */
+vector02:	.long	_FAULT		/* Access Error			*/
+vector03:	.long	_FAULT		/* Address Error		*/
+vector04:	.long	_FAULT		/* Illegal Instruction	*/
+vector05:	.long	_FAULT		/* Reserved				*/
+vector06:	.long	_FAULT		/* Reserved				*/
+vector07:	.long	_FAULT		/* Reserved				*/
+vector08:	.long	_FAULT		/* Privilege Violation	*/
+vector09:	.long	_FAULT		/* Trace				*/
+vector0A:	.long	_FAULT		/* Unimplemented A-Line	*/
+vector0B:	.long	_FAULT		/* Unimplemented F-Line	*/
+vector0C:	.long	_FAULT		/* Debug Interrupt		*/
+vector0D:	.long	_FAULT		/* Reserved				*/
+vector0E:	.long	_FAULT		/* Format Error			*/
+vector0F:	.long	_FAULT		/* Unitialized Int.		*/
+
+/* Reserved	*/
+vector10_17:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector18:	.long	_FAULT		/* Spurious Interrupt	*/
+vector19:	.long	_FAULT		/* Autovector Level 1	*/
+vector1A:	.long	_FAULT		/* Autovector Level 2	*/
+vector1B:	.long	_FAULT		/* Autovector Level 3	*/
+vector1C:	.long	_FAULT		/* Autovector Level 4	*/
+vector1D:	.long	_FAULT		/* Autovector Level 5	*/
+vector1E:	.long	_FAULT		/* Autovector Level 6	*/
+vector1F:	.long	_FAULT		/* Autovector Level 7	*/
+
+/* TRAP #0 - #15 */
+vector20_2F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+/* Reserved	*/
+vector30_3F:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector64_127:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector128_191:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+vector192_255:
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+
+	.text
+
+	.globl	_start
+_start:
+	nop
+	nop
+	move.w #0x2700,%sr                  /* Mask off Interrupt */
+
+    /* Set vector base register at the beginning of the Flash */
+	move.l	#CFG_FLASH_BASE, %d0
+	movec	%d0, %VBR
+
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR0
+
+	/* invalidate and disable cache */
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+
+	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
+	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	move.l #__got_start, %a5		/* put relocation table address to a5 */
+
+	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
+	bsr board_init_f			/* run low-level board init code (from flash) */
+
+	/* board_init_f() does not return */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	link.w %a6,#0
+	move.l 8(%a6), %sp		/* set new stack pointer */
+
+	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
+	move.l 16(%a6), %a0		/* Save copy of Destination Address */
+
+	move.l #CFG_MONITOR_BASE, %a1
+	move.l #__init_end, %a2
+	move.l %a0, %a3
+
+	/* copy the code to RAM */
+1:
+	move.l (%a1)+, (%a3)+
+	cmp.l  %a1,%a2
+	bgt.s	 1b
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	move.l	%a0, %a1
+	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	jmp	(%a1)
+
+in_ram:
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	move.l	%a0, %a1
+	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	move.l	%a0, %d1
+	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+6:
+	clr.l	(%a1)+
+	cmp.l	%a1,%d1
+	bgt.s	6b
+
+	/*
+	 * fix got table in RAM
+	 */
+	move.l	%a0, %a1
+	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	move.l	%a1,%a5		/* * fix got pointer register a5 */
+
+	move.l	%a0, %a2
+	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+
+7:
+	move.l	(%a1),%d1
+	sub.l	#_start,%d1
+	add.l	%a0,%d1
+	move.l	%d1,(%a1)+
+	cmp.l	%a2, %a1
+	bne	7b
+
+	/* calculate relative jump to board_init_r in ram */
+	move.l %a0, %a1
+	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+
+	/* set parameters for board_init_r */
+	move.l %a0,-(%sp)		/* dest_addr */
+	move.l %d0,-(%sp)		/* gd */
+	jsr	(%a1)
+
+/*------------------------------------------------------------------------------*/
+/* exception code */
+	.globl _fault
+_fault:
+	jmp _fault
+	.globl	_exc_handler
+
+_exc_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr exc_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+	.globl	_int_handler
+_int_handler:
+	SAVE_ALL
+	movel	%sp,%sp@-
+	bsr int_handler
+	addql	#4,%sp
+	RESTORE_ALL
+
+/*------------------------------------------------------------------------------*/
+/* cache functions */
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#(CFG_SDRAM_BASE + 0xc000), %d0		/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#(CFG_CS0_BASE + 0xc000), %d0		/* Setup cache mask */
+	movec	%d0, %ACR1			/* Enable cache */
+
+	/*move.l	#0x81000100, %d0*/		/* Setup cache mask */
+	move.l	#0x81000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_disable
+icache_disable:
+	move.l	#0x00000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	clr.l	%d0				/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	movec	%d0, %ACR1			/* Enable cache */
+
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	icache_status
+icache_status:
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+	move.l	(%a1), %d0
+	rts
+
+	.globl	icache_invalid
+icache_invalid:
+	move.l	#0x00000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	rts
+
+	.globl	dcache_enable
+dcache_enable:
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+
+    /* No dcache, just a dummy function */
+	.globl	dcache_disable
+dcache_disable:
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+	moveq	#0, %d0
+	move.l	%d0, (%a1)
+	rts
+
+	.globl	dcache_status
+dcache_status:
+	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
+	move.l	(%a1), %d0
+	rts
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii CONFIG_IDENT_STRING, "\0"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
new file mode 100644
index 000000000..37d69b994
--- /dev/null
+++ b/drivers/net/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)libnet.a
+
+COBJS 	:= mcffec.o
+
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
new file mode 100644
index 000000000..d1c84caee
--- /dev/null
+++ b/drivers/net/mcffec.c
@@ -0,0 +1,594 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#include <asm/fec.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_MCFFEC
+#undef	ET_DEBUG
+#undef	MII_DEBUG
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH  1520
+
+#define TX_BUF_CNT 2
+
+/*
+ NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE,
+	   see M54455 User Manual for MAX_FL of Receive Control Register for more
+	   description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will
+	   reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE
+	   will not make any improvement on speed
+*/
+#define PKT_MAXBUF_SIZE		1518
+#define PKT_MINBUF_SIZE		64
+#define PKT_MAXBLR_SIZE		1520
+#define LAST_PKTBUFSRX		PKTBUFSRX - 1
+#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
+#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+struct fec_info_s fec_info[] = {
+#ifdef CFG_FEC0_IOBASE
+	{
+	 0,			/* index */
+	 CFG_FEC0_IOBASE,	/* io base */
+	 CFG_FEC0_PINMUX,	/* gpio pin muxing */
+	 CFG_FEC0_MIIBASE,	/* mii base */
+	 -1,			/* phy_addr */
+	 0,			/* duplex and speed */
+	 0,			/* phy name */
+	 0,			/* phyname init */
+	 0,			/* RX BD */
+	 0,			/* TX BD */
+	 0,			/* rx Index */
+	 0,			/* tx Index */
+	 0,			/* tx buffer */
+	 0,			/* initialized flag */
+	 },
+#endif
+#ifdef CFG_FEC1_IOBASE
+	{
+	 1,			/* index */
+	 CFG_FEC1_IOBASE,	/* io base */
+	 CFG_FEC1_PINMUX,	/* gpio pin muxing */
+	 CFG_FEC1_MIIBASE,	/* mii base */
+	 -1,			/* phy_addr */
+	 0,			/* duplex and speed */
+	 0,			/* phy name */
+	 0,			/* phy name init */
+	 0,			/* RX BD */
+	 0,			/* TX BD */
+	 0,			/* rx Index */
+	 0,			/* tx Index */
+	 0,			/* tx buffer */
+	 0,			/* initialized flag */
+	 }
+#endif
+};
+
+/*
+  * FEC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+
+int fec_send(struct eth_device *dev, volatile void *packet, int length);
+int fec_recv(struct eth_device *dev);
+int fec_init(struct eth_device *dev, bd_t * bd);
+void fec_halt(struct eth_device *dev);
+void fec_reset(struct eth_device *dev);
+
+extern int fecpin_setclear(struct eth_device *dev, int setclear);
+
+#ifdef CFG_DISCOVER_PHY
+extern void mii_init(void);
+extern uint mii_send(uint mii_cmd);
+extern int mii_discover_phy(struct eth_device *dev);
+extern int mcffec_miiphy_read(char *devname, unsigned char addr,
+			      unsigned char reg, unsigned short *value);
+extern int mcffec_miiphy_write(char *devname, unsigned char addr,
+			       unsigned char reg, unsigned short value);
+#endif
+
+void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
+{
+	if ((dup_spd >> 16) == FULL) {
+		/* Set maximum frame length */
+		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
+		    FEC_RCR_PROM | 0x100;
+		fecp->tcr = FEC_TCR_FDEN;
+	} else {
+		/* Half duplex mode */
+		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
+		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
+		fecp->tcr &= ~FEC_TCR_FDEN;
+	}
+
+	if ((dup_spd & 0xFFFF) == _100BASET) {
+#ifdef MII_DEBUG
+		printf("100Mbps\n");
+#endif
+		bd->bi_ethspeed = 100;
+	} else {
+#ifdef MII_DEBUG
+		printf("10Mbps\n");
+#endif
+		bd->bi_ethspeed = 10;
+	}
+}
+
+int fec_send(struct eth_device *dev, volatile void *packet, int length)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+	int j, rc;
+	u16 phyStatus;
+
+	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+
+	/* section 16.9.23.3
+	 * Wait for ready
+	 */
+	j = 0;
+	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
+	       (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("TX not ready\n");
+	}
+
+	info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
+	info->txbd[info->txIdx].cbd_datlen = length;
+	info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
+
+	/* Activate transmit Buffer Descriptor polling */
+	fecp->tdar = 0x01000000;	/* Descriptor polling active    */
+
+	j = 0;
+	while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
+	       (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("TX timeout\n");
+	}
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
+	       __FILE__, __LINE__, __FUNCTION__, j,
+	       info->txbd[info->txIdx].cbd_sc,
+	       (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
+#endif
+
+	/* return only status bits */ ;
+	rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
+	info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
+
+	return rc;
+}
+
+int fec_recv(struct eth_device *dev)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+	int length;
+
+	for (;;) {
+		/* section 16.9.23.2 */
+		if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		length = info->rxbd[info->rxIdx].cbd_datlen;
+
+		if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
+			printf("%s[%d] err: %x\n",
+			       __FUNCTION__, __LINE__,
+			       info->rxbd[info->rxIdx].cbd_sc);
+#ifdef ET_DEBUG
+			printf("%s[%d] err: %x\n",
+			       __FUNCTION__, __LINE__,
+			       info->rxbd[info->rxIdx].cbd_sc);
+#endif
+		} else {
+
+			length -= 4;
+			/* Pass the packet up to the protocol layers. */
+			NetReceive(NetRxPackets[info->rxIdx], length);
+
+			fecp->eir |= FEC_EIR_RXF;
+		}
+
+		/* Give the buffer back to the FEC. */
+		info->rxbd[info->rxIdx].cbd_datlen = 0;
+
+		/* wrap around buffer index when necessary */
+		if (info->rxIdx == LAST_PKTBUFSRX) {
+			info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
+			info->rxIdx = 0;
+		} else {
+			info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+			info->rxIdx++;
+		}
+
+		/* Try to fill Buffer Descriptors */
+		fecp->rdar = 0x01000000;	/* Descriptor polling active    */
+	}
+
+	return length;
+}
+
+/**************************************************************
+ *
+ * FEC Ethernet Initialization Routine
+ *
+ *************************************************************/
+
+#ifdef ET_DEBUG
+void dbgFecRegs(struct eth_device *dev)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+
+	printf("=====\n");
+	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
+	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
+	printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
+	printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
+	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
+	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
+	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
+	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
+	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
+	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
+	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
+	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
+	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
+	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
+	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
+	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
+	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
+	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
+	printf("r_bound      %x - %x\n", (int)&fecp->frbr, fecp->frbr);
+	printf("r_fstart     %x - %x\n", (int)&fecp->frsr, fecp->frsr);
+	printf("r_drng       %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
+	printf("x_drng       %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
+	printf("r_bufsz      %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
+
+	printf("\n");
+	printf("rmon_t_drop        %x - %x\n", (int)&fecp->rmon_t_drop,
+	       fecp->rmon_t_drop);
+	printf("rmon_t_packets     %x - %x\n", (int)&fecp->rmon_t_packets,
+	       fecp->rmon_t_packets);
+	printf("rmon_t_bc_pkt      %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
+	       fecp->rmon_t_bc_pkt);
+	printf("rmon_t_mc_pkt      %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
+	       fecp->rmon_t_mc_pkt);
+	printf("rmon_t_crc_align   %x - %x\n", (int)&fecp->rmon_t_crc_align,
+	       fecp->rmon_t_crc_align);
+	printf("rmon_t_undersize   %x - %x\n", (int)&fecp->rmon_t_undersize,
+	       fecp->rmon_t_undersize);
+	printf("rmon_t_oversize    %x - %x\n", (int)&fecp->rmon_t_oversize,
+	       fecp->rmon_t_oversize);
+	printf("rmon_t_frag        %x - %x\n", (int)&fecp->rmon_t_frag,
+	       fecp->rmon_t_frag);
+	printf("rmon_t_jab         %x - %x\n", (int)&fecp->rmon_t_jab,
+	       fecp->rmon_t_jab);
+	printf("rmon_t_col         %x - %x\n", (int)&fecp->rmon_t_col,
+	       fecp->rmon_t_col);
+	printf("rmon_t_p64         %x - %x\n", (int)&fecp->rmon_t_p64,
+	       fecp->rmon_t_p64);
+	printf("rmon_t_p65to127    %x - %x\n", (int)&fecp->rmon_t_p65to127,
+	       fecp->rmon_t_p65to127);
+	printf("rmon_t_p128to255   %x - %x\n", (int)&fecp->rmon_t_p128to255,
+	       fecp->rmon_t_p128to255);
+	printf("rmon_t_p256to511   %x - %x\n", (int)&fecp->rmon_t_p256to511,
+	       fecp->rmon_t_p256to511);
+	printf("rmon_t_p512to1023  %x - %x\n", (int)&fecp->rmon_t_p512to1023,
+	       fecp->rmon_t_p512to1023);
+	printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
+	       fecp->rmon_t_p1024to2047);
+	printf("rmon_t_p_gte2048   %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
+	       fecp->rmon_t_p_gte2048);
+	printf("rmon_t_octets      %x - %x\n", (int)&fecp->rmon_t_octets,
+	       fecp->rmon_t_octets);
+
+	printf("\n");
+	printf("ieee_t_drop      %x - %x\n", (int)&fecp->ieee_t_drop,
+	       fecp->ieee_t_drop);
+	printf("ieee_t_frame_ok  %x - %x\n", (int)&fecp->ieee_t_frame_ok,
+	       fecp->ieee_t_frame_ok);
+	printf("ieee_t_1col      %x - %x\n", (int)&fecp->ieee_t_1col,
+	       fecp->ieee_t_1col);
+	printf("ieee_t_mcol      %x - %x\n", (int)&fecp->ieee_t_mcol,
+	       fecp->ieee_t_mcol);
+	printf("ieee_t_def       %x - %x\n", (int)&fecp->ieee_t_def,
+	       fecp->ieee_t_def);
+	printf("ieee_t_lcol      %x - %x\n", (int)&fecp->ieee_t_lcol,
+	       fecp->ieee_t_lcol);
+	printf("ieee_t_excol     %x - %x\n", (int)&fecp->ieee_t_excol,
+	       fecp->ieee_t_excol);
+	printf("ieee_t_macerr    %x - %x\n", (int)&fecp->ieee_t_macerr,
+	       fecp->ieee_t_macerr);
+	printf("ieee_t_cserr     %x - %x\n", (int)&fecp->ieee_t_cserr,
+	       fecp->ieee_t_cserr);
+	printf("ieee_t_sqe       %x - %x\n", (int)&fecp->ieee_t_sqe,
+	       fecp->ieee_t_sqe);
+	printf("ieee_t_fdxfc     %x - %x\n", (int)&fecp->ieee_t_fdxfc,
+	       fecp->ieee_t_fdxfc);
+	printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
+	       fecp->ieee_t_octets_ok);
+
+	printf("\n");
+	printf("rmon_r_drop        %x - %x\n", (int)&fecp->rmon_r_drop,
+	       fecp->rmon_r_drop);
+	printf("rmon_r_packets     %x - %x\n", (int)&fecp->rmon_r_packets,
+	       fecp->rmon_r_packets);
+	printf("rmon_r_bc_pkt      %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
+	       fecp->rmon_r_bc_pkt);
+	printf("rmon_r_mc_pkt      %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
+	       fecp->rmon_r_mc_pkt);
+	printf("rmon_r_crc_align   %x - %x\n", (int)&fecp->rmon_r_crc_align,
+	       fecp->rmon_r_crc_align);
+	printf("rmon_r_undersize   %x - %x\n", (int)&fecp->rmon_r_undersize,
+	       fecp->rmon_r_undersize);
+	printf("rmon_r_oversize    %x - %x\n", (int)&fecp->rmon_r_oversize,
+	       fecp->rmon_r_oversize);
+	printf("rmon_r_frag        %x - %x\n", (int)&fecp->rmon_r_frag,
+	       fecp->rmon_r_frag);
+	printf("rmon_r_jab         %x - %x\n", (int)&fecp->rmon_r_jab,
+	       fecp->rmon_r_jab);
+	printf("rmon_r_p64         %x - %x\n", (int)&fecp->rmon_r_p64,
+	       fecp->rmon_r_p64);
+	printf("rmon_r_p65to127    %x - %x\n", (int)&fecp->rmon_r_p65to127,
+	       fecp->rmon_r_p65to127);
+	printf("rmon_r_p128to255   %x - %x\n", (int)&fecp->rmon_r_p128to255,
+	       fecp->rmon_r_p128to255);
+	printf("rmon_r_p256to511   %x - %x\n", (int)&fecp->rmon_r_p256to511,
+	       fecp->rmon_r_p256to511);
+	printf("rmon_r_p512to1023  %x - %x\n", (int)&fecp->rmon_r_p512to1023,
+	       fecp->rmon_r_p512to1023);
+	printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
+	       fecp->rmon_r_p1024to2047);
+	printf("rmon_r_p_gte2048   %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
+	       fecp->rmon_r_p_gte2048);
+	printf("rmon_r_octets      %x - %x\n", (int)&fecp->rmon_r_octets,
+	       fecp->rmon_r_octets);
+
+	printf("\n");
+	printf("ieee_r_drop      %x - %x\n", (int)&fecp->ieee_r_drop,
+	       fecp->ieee_r_drop);
+	printf("ieee_r_frame_ok  %x - %x\n", (int)&fecp->ieee_r_frame_ok,
+	       fecp->ieee_r_frame_ok);
+	printf("ieee_r_crc       %x - %x\n", (int)&fecp->ieee_r_crc,
+	       fecp->ieee_r_crc);
+	printf("ieee_r_align     %x - %x\n", (int)&fecp->ieee_r_align,
+	       fecp->ieee_r_align);
+	printf("ieee_r_macerr    %x - %x\n", (int)&fecp->ieee_r_macerr,
+	       fecp->ieee_r_macerr);
+	printf("ieee_r_fdxfc     %x - %x\n", (int)&fecp->ieee_r_fdxfc,
+	       fecp->ieee_r_fdxfc);
+	printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
+	       fecp->ieee_r_octets_ok);
+
+	printf("\n\n\n");
+}
+#endif
+
+int fec_init(struct eth_device *dev, bd_t * bd)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+	int i;
+	u8 *ea;
+
+	fecpin_setclear(dev, 1);
+
+	fec_reset(dev);
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \
+	defined (CFG_DISCOVER_PHY)
+
+	mii_init();
+
+	setFecDuplexSpeed(fecp, bd, info->dup_spd);
+#else
+#ifndef CFG_DISCOVER_PHY
+	setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
+#endif				/* ifndef CFG_DISCOVER_PHY */
+#endif				/* CFG_CMD_MII || CONFIG_MII */
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set station address   */
+	if ((u32) fecp == CFG_FEC0_IOBASE) {
+		ea = &bd->bi_enetaddr[0];
+	} else {
+#ifdef CFG_FEC1_IOBASE
+		ea = &bd->bi_enet1addr[0];
+#endif
+	}
+
+	fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+	fecp->paur = (ea[4] << 24) | (ea[5] << 16);
+#ifdef ET_DEBUG
+	printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
+#endif
+
+	/* Clear unicast address hash table */
+	fecp->iaur = 0;
+	fecp->ialr = 0;
+
+	/* Clear multicast address hash table */
+	fecp->gaur = 0;
+	fecp->galr = 0;
+
+	/* Set maximum receive buffer size. */
+	fecp->emrbr = PKT_MAXBLR_SIZE;
+
+	/*
+	 * Setup Buffers and Buffer Desriptors
+	 */
+	info->rxIdx = 0;
+	info->txIdx = 0;
+
+	/*
+	 * Setup Receiver Buffer Descriptors (13.14.24.18)
+	 * Settings:
+	 *     Empty, Wrap
+	 */
+	for (i = 0; i < PKTBUFSRX; i++) {
+		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+		info->rxbd[i].cbd_datlen = 0;	/* Reset */
+		info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+	}
+	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+	/*
+	 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
+	 * Settings:
+	 *    Last, Tx CRC
+	 */
+	for (i = 0; i < TX_BUF_CNT; i++) {
+		info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
+		info->txbd[i].cbd_datlen = 0;	/* Reset */
+		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
+	}
+	info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+	/* Set receive and transmit descriptor base */
+	fecp->erdsr = (unsigned int)(&info->rxbd[0]);
+	fecp->etdsr = (unsigned int)(&info->txbd[0]);
+
+	/* Now enable the transmit and receive processing */
+	fecp->ecr |= FEC_ECR_ETHER_EN;
+
+	/* And last, try to fill Rx Buffer Descriptors */
+	fecp->rdar = 0x01000000;	/* Descriptor polling active    */
+
+	return 1;
+}
+
+void fec_reset(struct eth_device *dev)
+{
+	struct fec_info_s *info = dev->priv;
+	volatile fec_t *fecp = (fec_t *) (info->iobase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+void fec_halt(struct eth_device *dev)
+{
+	struct fec_info_s *info = dev->priv;
+
+	fec_reset(dev);
+
+	fecpin_setclear(dev, 0);
+
+	info->rxIdx = info->txIdx = 0;
+	memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
+	memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
+	memset(info->txbuf, 0, DBUF_LENGTH);
+}
+
+int mcffec_initialize(bd_t * bis)
+{
+	struct eth_device *dev;
+	int i;
+
+	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
+
+		dev = (struct eth_device *)malloc(sizeof *dev);
+		if (dev == NULL)
+			hang();
+
+		memset(dev, 0, sizeof(*dev));
+
+		sprintf(dev->name, "FEC%d", fec_info[i].index);
+
+		dev->priv = &fec_info[i];
+		dev->init = fec_init;
+		dev->halt = fec_halt;
+		dev->send = fec_send;
+		dev->recv = fec_recv;
+
+		/* setup Receive and Transmit buffer descriptor */
+		fec_info[i].rxbd =
+		    (cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31));
+		fec_info[i].txbd =
+		    (cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31));
+		fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31);
+#ifdef ET_DEBUG
+		printf("rxbd %x txbd %x\n",
+		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
+#endif
+
+		fec_info[i].phy_name = (char *)malloc(32);
+
+		eth_register(dev);
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+		miiphy_register(dev->name,
+				mcffec_miiphy_read, mcffec_miiphy_write);
+#endif
+	}
+
+	/* default speed */
+	bis->bi_ethspeed = 10;
+
+	return 1;
+}
+
+#endif				/* CFG_CMD_NET, FEC_ENET & NET_MULTI */
+#endif				/* CONFIG_MCFFEC */
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
new file mode 100644
index 000000000..2208a08a7
--- /dev/null
+++ b/drivers/serial/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)libserial.a
+
+COBJS 	:= mcfserial.o
+
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/serial/mcfserial.c b/drivers/serial/mcfserial.c
new file mode 100644
index 000000000..a8ca78ad8
--- /dev/null
+++ b/drivers/serial/mcfserial.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2004, Freescale, Inc
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Minimal serial functions needed to use one of the uart ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <asm/mcfuart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_MCFSERIAL
+int serial_init(void)
+{
+	volatile uart_t *uart;
+	u32 counter;
+
+	uart = (volatile uart_t *)(CFG_UART_BASE);
+
+	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+	uart->ucr = UART_UCR_RESET_RX;
+	uart->ucr = UART_UCR_RESET_TX;
+	uart->ucr = UART_UCR_RESET_ERROR;
+	uart->ucr = UART_UCR_RESET_MR;
+	__asm__("nop");
+
+	uart->uimr = 0;
+
+	/* write to CSR: RX/TX baud rate from timers */
+	uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+
+	uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
+	uart->umr = UART_UMR_SB_STOP_BITS_1;
+
+	/* Setting up BaudRate */
+	counter = (u32) (gd->bus_clk / (gd->baudrate));
+	counter >>= 5;
+
+	/* write to CTUR: divide counter upper byte */
+	uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+	/* write to CTLR: divide counter lower byte */
+	uart->ubg2 = (u8) (counter & 0x00ff);
+
+	uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+
+	return (0);
+}
+
+void serial_putc(const char c)
+{
+	volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+	if (c == '\n')
+		serial_putc('\r');
+
+	/* Wait for last character to go. */
+	while (!(uart->usr & UART_USR_TXRDY)) ;
+
+	uart->utb = c;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+int serial_getc(void)
+{
+	volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+	/* Wait for a character to arrive. */
+	while (!(uart->usr & UART_USR_RXRDY)) ;
+	return uart->urb;
+}
+
+int serial_tstc(void)
+{
+	volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+
+	return (uart->usr & UART_USR_RXRDY);
+}
+
+void serial_setbrg(void)
+{
+	volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE);
+	u32 counter;
+
+	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
+	counter++;
+
+	/* write to CTUR: divide counter upper byte */
+	uart->ubg1 = ((counter & 0xff00) >> 8);
+	/* write to CTLR: divide counter lower byte */
+	uart->ubg2 = (counter & 0x00ff);
+
+	uart->ucr = UART_UCR_RESET_RX;
+	uart->ucr = UART_UCR_RESET_TX;
+
+	uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+}
+#endif				/* CONFIG_MCFSERIAL */
diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h
index ce613ac38..0e2a0ed8c 100644
--- a/include/asm-m68k/byteorder.h
+++ b/include/asm-m68k/byteorder.h
@@ -1,7 +1,107 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #ifndef _M68K_BYTEORDER_H
 #define _M68K_BYTEORDER_H
 
 #include <asm/types.h>
+
+#ifdef __GNUC__
+#define __sw16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define __sw32(x) \
+	((__u32)( \
+		(((__u32)(x)) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x)) >> 24) ))
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	unsigned result = *addr;
+	return __sw16(result);
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr,
+			       const unsigned val)
+{
+	*addr = __sw16(val);
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	unsigned result = *addr;
+	return __sw32(result);
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	*addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+	return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+	return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif				/* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif				/* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
 #include <linux/byteorder/big_endian.h>
 
-#endif /* _M68K_BYTEORDER_H */
+#endif				/* _M68K_BYTEORDER_H */
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
index 5bbbfb245..9a5e7d5ab 100644
--- a/include/asm-m68k/fec.h
+++ b/include/asm-m68k/fec.h
@@ -5,6 +5,10 @@
  * MPC8xx Communication Processor Module.
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  *
+ * Add FEC Structure and definitions
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -30,9 +34,9 @@
 /* Buffer descriptors used FEC.
 */
 typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
+	ushort cbd_sc;		/* Status and Control */
+	ushort cbd_datlen;	/* Data length in buffer */
+	uint cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
 #define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
@@ -53,28 +57,36 @@ typedef struct cpm_buf_desc {
 /* Buffer descriptor control/status used by Ethernet receive.
 */
 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_RO1		((ushort)0x4000)
 #define BD_ENET_RX_WRAP		((ushort)0x2000)
 #define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_RO2		BD_ENET_RX_INTR
 #define BD_ENET_RX_LAST		((ushort)0x0800)
 #define BD_ENET_RX_FIRST	((ushort)0x0400)
 #define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_BC		((ushort)0x0080)
+#define BD_ENET_RX_MC		((ushort)0x0040)
 #define BD_ENET_RX_LG		((ushort)0x0020)
 #define BD_ENET_RX_NO		((ushort)0x0010)
 #define BD_ENET_RX_SH		((ushort)0x0008)
 #define BD_ENET_RX_CR		((ushort)0x0004)
 #define BD_ENET_RX_OV		((ushort)0x0002)
 #define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_TR		BD_ENET_RX_CL
 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
 
 /* Buffer descriptor control/status used by Ethernet transmit.
 */
 #define BD_ENET_TX_READY	((ushort)0x8000)
 #define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_TO1		BD_ENET_TX_PAD
 #define BD_ENET_TX_WRAP		((ushort)0x2000)
 #define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_TO2		BD_ENET_TX_INTR_
 #define BD_ENET_TX_LAST		((ushort)0x0800)
 #define BD_ENET_TX_TC		((ushort)0x0400)
 #define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_ABC		BD_ENET_TX_DEF
 #define BD_ENET_TX_HB		((ushort)0x0100)
 #define BD_ENET_TX_LC		((ushort)0x0080)
 #define BD_ENET_TX_RL		((ushort)0x0040)
@@ -83,4 +95,225 @@ typedef struct cpm_buf_desc {
 #define BD_ENET_TX_CSL		((ushort)0x0001)
 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
 
-#endif	/* fec_h */
+#ifdef CONFIG_MCFFEC
+/*********************************************************************
+*
+* Fast Ethernet Controller (FEC)
+*
+*********************************************************************/
+/* FEC private information */
+struct fec_info_s {
+	int index;
+	u32 iobase;
+	u32 pinmux;
+	u32 miibase;
+	int phy_addr;
+	int dup_spd;
+	char *phy_name;
+	int phyname_init;
+	cbd_t *rxbd;		/* Rx BD */
+	cbd_t *txbd;		/* Tx BD */
+	uint rxIdx;
+	uint txIdx;
+	char *txbuf;
+	int initialized;
+};
+
+/* Register read/write struct */
+typedef struct fec {
+	u8 resv0[0x4];
+	u32 eir;
+	u32 eimr;
+	u8 resv1[0x4];
+	u32 rdar;
+	u32 tdar;
+	u8 resv2[0xC];
+	u32 ecr;
+	u8 resv3[0x18];
+	u32 mmfr;
+	u32 mscr;
+	u8 resv4[0x1C];
+	u32 mibc;
+	u8 resv5[0x1C];
+	u32 rcr;
+	u8 resv6[0x3C];
+	u32 tcr;
+	u8 resv7[0x1C];
+	u32 palr;
+	u32 paur;
+	u32 opd;
+	u8 resv8[0x28];
+	u32 iaur;
+	u32 ialr;
+	u32 gaur;
+	u32 galr;
+	u8 resv9[0x1C];
+	u32 tfwr;
+	u8 resv10[0x4];
+	u32 frbr;
+	u32 frsr;
+	u8 resv11[0x2C];
+	u32 erdsr;
+	u32 etdsr;
+	u32 emrbr;
+	u8 resv12[0x74];
+
+	u32 rmon_t_drop;
+	u32 rmon_t_packets;
+	u32 rmon_t_bc_pkt;
+	u32 rmon_t_mc_pkt;
+	u32 rmon_t_crc_align;
+	u32 rmon_t_undersize;
+	u32 rmon_t_oversize;
+	u32 rmon_t_frag;
+	u32 rmon_t_jab;
+	u32 rmon_t_col;
+	u32 rmon_t_p64;
+	u32 rmon_t_p65to127;
+	u32 rmon_t_p128to255;
+	u32 rmon_t_p256to511;
+	u32 rmon_t_p512to1023;
+	u32 rmon_t_p1024to2047;
+	u32 rmon_t_p_gte2048;
+	u32 rmon_t_octets;
+
+	u32 ieee_t_drop;
+	u32 ieee_t_frame_ok;
+	u32 ieee_t_1col;
+	u32 ieee_t_mcol;
+	u32 ieee_t_def;
+	u32 ieee_t_lcol;
+	u32 ieee_t_excol;
+	u32 ieee_t_macerr;
+	u32 ieee_t_cserr;
+	u32 ieee_t_sqe;
+	u32 ieee_t_fdxfc;
+	u32 ieee_t_octets_ok;
+	u8 resv13[0x8];
+
+	u32 rmon_r_drop;
+	u32 rmon_r_packets;
+	u32 rmon_r_bc_pkt;
+	u32 rmon_r_mc_pkt;
+	u32 rmon_r_crc_align;
+	u32 rmon_r_undersize;
+	u32 rmon_r_oversize;
+	u32 rmon_r_frag;
+	u32 rmon_r_jab;
+	u32 rmon_r_resvd_0;
+	u32 rmon_r_p64;
+	u32 rmon_r_p65to127;
+	u32 rmon_r_p128to255;
+	u32 rmon_r_p256to511;
+	u32 rmon_r_p512to1023;
+	u32 rmon_r_p1024to2047;
+	u32 rmon_r_p_gte2048;
+	u32 rmon_r_octets;
+
+	u32 ieee_r_drop;
+	u32 ieee_r_frame_ok;
+	u32 ieee_r_crc;
+	u32 ieee_r_align;
+	u32 ieee_r_macerr;
+	u32 ieee_r_fdxfc;
+	u32 ieee_r_octets_ok;
+} fec_t;
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* Bit definitions and macros for FEC_EIR */
+#define FEC_EIR_CLEAR_ALL	(0xFFF80000)
+#define FEC_EIR_HBERR		(0x80000000)
+#define FEC_EIR_BABR		(0x40000000)
+#define FEC_EIR_BABT		(0x20000000)
+#define FEC_EIR_GRA		(0x10000000)
+#define FEC_EIR_TXF		(0x08000000)
+#define FEC_EIR_TXB		(0x04000000)
+#define FEC_EIR_RXF		(0x02000000)
+#define FEC_EIR_RXB		(0x01000000)
+#define FEC_EIR_MII		(0x00800000)
+#define FEC_EIR_EBERR		(0x00400000)
+#define FEC_EIR_LC		(0x00200000)
+#define FEC_EIR_RL		(0x00100000)
+#define FEC_EIR_UN		(0x00080000)
+
+/* Bit definitions and macros for FEC_RDAR */
+#define FEC_RDAR_R_DES_ACTIVE	(0x01000000)
+
+/* Bit definitions and macros for FEC_TDAR */
+#define FEC_TDAR_X_DES_ACTIVE	(0x01000000)
+
+/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_ETHER_EN	(0x00000002)
+#define FEC_ECR_RESET		(0x00000001)
+
+/* Bit definitions and macros for FEC_MMFR */
+#define FEC_MMFR_DATA(x)	(((x)&0xFFFF))
+#define FEC_MMFR_ST(x)		(((x)&0x03)<<30)
+#define FEC_MMFR_ST_01		(0x40000000)
+#define FEC_MMFR_OP_RD		(0x20000000)
+#define FEC_MMFR_OP_WR		(0x10000000)
+#define FEC_MMFR_PA(x)		(((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x)		(((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x)		(((x)&0x03)<<16)
+#define FEC_MMFR_TA_10		(0x00020000)
+
+/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_DIS_PREAMBLE	(0x00000080)
+#define FEC_MSCR_MII_SPEED(x)	(((x)&0x3F)<<1)
+
+/* Bit definitions and macros for FEC_MIBC */
+#define FEC_MIBC_MIB_DISABLE	(0x80000000)
+#define FEC_MIBC_MIB_IDLE	(0x40000000)
+
+/* Bit definitions and macros for FEC_RCR */
+#define FEC_RCR_MAX_FL(x)	(((x)&0x7FF)<<16)
+#define FEC_RCR_FCE		(0x00000020)
+#define FEC_RCR_BC_REJ		(0x00000010)
+#define FEC_RCR_PROM		(0x00000008)
+#define FEC_RCR_MII_MODE	(0x00000004)
+#define FEC_RCR_DRT		(0x00000002)
+#define FEC_RCR_LOOP		(0x00000001)
+
+/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_RFC_PAUSE	(0x00000010)
+#define FEC_TCR_TFC_PAUSE	(0x00000008)
+#define FEC_TCR_FDEN		(0x00000004)
+#define FEC_TCR_HBC		(0x00000002)
+#define FEC_TCR_GTS		(0x00000001)
+
+/* Bit definitions and macros for FEC_PAUR */
+#define FEC_PAUR_PADDR2(x)	(((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x)	((x)&0xFFFF)
+
+/* Bit definitions and macros for FEC_OPD */
+#define FEC_OPD_PAUSE_DUR(x)	(((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x)	(((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for FEC_TFWR */
+#define FEC_TFWR_X_WMRK(x)	((x)&0x03)
+#define FEC_TFWR_X_WMRK_64	(0x01)
+#define FEC_TFWR_X_WMRK_128	(0x02)
+#define FEC_TFWR_X_WMRK_192	(0x03)
+
+/* Bit definitions and macros for FEC_FRBR */
+#define FEC_FRBR_R_BOUND(x)	(((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_FRSR */
+#define FEC_FRSR_R_FSTART(x)	(((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_ERDSR */
+#define FEC_ERDSR_R_DES_START(x)(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_ETDSR */
+#define FEC_ETDSR_X_DES_START(x)(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_EMRBR */
+#define FEC_EMRBR_R_BUF_SIZE(x)	(((x)&0x7F)<<4)
+
+#define	FEC_RESET_DELAY		100
+#define FEC_RX_TOUT			100
+
+#endif				/* CONFIG_MCFFEC */
+#endif				/* fec_h */
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
new file mode 100644
index 000000000..5ef1265f8
--- /dev/null
+++ b/include/asm-m68k/immap_5329.h
@@ -0,0 +1,793 @@
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5329__
+#define __IMMAP_5329__
+
+#define MMAP_SCM1       0xEC000000
+#define MMAP_MDHA       0xEC080000
+#define MMAP_SKHA       0xEC084000
+#define MMAP_RNG        0xEC088000
+#define MMAP_SCM2       0xFC000000
+#define MMAP_XBS        0xFC004000
+#define MMAP_FBCS       0xFC008000
+#define MMAP_CAN        0xFC020000
+#define MMAP_FEC        0xFC030000
+#define MMAP_SCM3       0xFC040000
+#define MMAP_EDMA       0xFC044000
+#define MMAP_TCD        0xFC045000
+#define MMAP_INTC0      0xFC048000
+#define MMAP_INTC1      0xFC04C000
+#define MMAP_INTCACK    0xFC054000
+#define MMAP_I2C        0xFC058000
+#define MMAP_QSPI       0xFC05C000
+#define MMAP_UART0      0xFC060000
+#define MMAP_UART1      0xFC064000
+#define MMAP_UART2      0xFC068000
+#define MMAP_DTMR0      0xFC070000
+#define MMAP_DTMR1      0xFC074000
+#define MMAP_DTMR2      0xFC078000
+#define MMAP_DTMR3      0xFC07C000
+#define MMAP_PIT0       0xFC080000
+#define MMAP_PIT1       0xFC084000
+#define MMAP_PIT2       0xFC088000
+#define MMAP_PIT3       0xFC08C000
+#define MMAP_PWM        0xFC090000
+#define MMAP_EPORT      0xFC094000
+#define MMAP_WDOG       0xFC098000
+#define MMAP_CCM        0xFC0A0000
+#define MMAP_GPIO       0xFC0A4000
+#define MMAP_RTC        0xFC0A8000
+#define MMAP_LCDC       0xFC0AC000
+#define MMAP_USBOTG     0xFC0B0000
+#define MMAP_USBH       0xFC0B4000
+#define MMAP_SDRAM      0xFC0B8000
+#define MMAP_SSI        0xFC0BC000
+#define MMAP_PLL        0xFC0C0000
+
+/* System control module registers */
+typedef struct scm1_ctrl {
+	u32 mpr0;		/* 0x00 Master Privilege Register 0 */
+	u32 res1[15];		/* 0x04 - 0x3F */
+	u32 pacrh;		/* 0x40 Peripheral Access Control Register H */
+	u32 res2[3];		/* 0x44 - 0x53 */
+	u32 bmt0;		/*0x54 Bus Monitor Timeout 0 */
+} scm1_t;
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+	u32 mdmr;		/* 0x00 MDHA Mode Register */
+	u32 mdcr;		/* 0x04 Control register */
+	u32 mdcmr;		/* 0x08 Command Register */
+	u32 mdsr;		/* 0x0C Status Register */
+	u32 mdisr;		/* 0x10 Interrupt Status Register */
+	u32 mdimr;		/* 0x14 Interrupt Mask Register */
+	u32 mddsr;		/* 0x1C Data Size Register */
+	u32 mdin;		/* 0x20 Input FIFO */
+	u32 res1[3];		/* 0x24 - 0x2F */
+	u32 mdao;		/* 0x30 Message Digest AO Register */
+	u32 mdbo;		/* 0x34 Message Digest BO Register */
+	u32 mdco;		/* 0x38 Message Digest CO Register */
+	u32 mddo;		/* 0x3C Message Digest DO Register */
+	u32 mdeo;		/* 0x40 Message Digest EO Register */
+	u32 mdmds;		/* 0x44 Message Data Size Register */
+	u32 res[10];		/* 0x48 - 0x6F */
+	u32 mda1;		/* 0x70 Message Digest A1 Register */
+	u32 mdb1;		/* 0x74 Message Digest B1 Register */
+	u32 mdc1;		/* 0x78 Message Digest C1 Register */
+	u32 mdd1;		/* 0x7C Message Digest D1 Register */
+	u32 mde1;		/* 0x80 Message Digest E1 Register */
+} mdha_t;
+
+/* Symmetric Key Hardware Accelerator */
+typedef struct skha_ctrl {
+	u32 mr;			/* 0x00 Mode Register */
+	u32 cr;			/* 0x04 Control Register */
+	u32 cmr;		/* 0x08 Command Register */
+	u32 sr;			/* 0x0C Status Register */
+	u32 esr;		/* 0x10 Error Status Register */
+	u32 emr;		/* 0x14 Error Status Mask Register) */
+	u32 ksr;		/* 0x18 Key Size Register */
+	u32 dsr;		/* 0x1C Data Size Register */
+	u32 in;			/* 0x20 Input FIFO */
+	u32 out;		/* 0x24 Output FIFO */
+	u32 res1[2];		/* 0x28 - 0x2F */
+	u32 kdr1;		/* 0x30 Key Data Register 1  */
+	u32 kdr2;		/* 0x34 Key Data Register 2 */
+	u32 kdr3;		/* 0x38 Key Data Register 3 */
+	u32 kdr4;		/* 0x3C Key Data Register 4 */
+	u32 kdr5;		/* 0x40 Key Data Register 5 */
+	u32 kdr6;		/* 0x44 Key Data Register 6 */
+	u32 res2[10];		/* 0x48 - 0x6F */
+	u32 c1;			/* 0x70 Context 1 */
+	u32 c2;			/* 0x74 Context 2 */
+	u32 c3;			/* 0x78 Context 3 */
+	u32 c4;			/* 0x7C Context 4 */
+	u32 c5;			/* 0x80 Context 5 */
+	u32 c6;			/* 0x84 Context 6 */
+	u32 c7;			/* 0x88 Context 7 */
+	u32 c8;			/* 0x8C Context 8 */
+	u32 c9;			/* 0x90 Context 9 */
+	u32 c10;		/* 0x94 Context 10 */
+	u32 c11;		/* 0x98 Context 11 */
+} skha_t;
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+	u32 rngcr;		/* 0x00 RNG Control Register */
+	u32 rngsr;		/* 0x04 RNG Status Register */
+	u32 rnger;		/* 0x08 RNG Entropy Register */
+	u32 rngout;		/* 0x0C RNG Output FIFO */
+} rng_t;
+
+/* System control module registers 2 */
+typedef struct scm2_ctrl {
+	u32 mpr1;		/* 0x00 Master Privilege Register */
+	u32 res1[7];		/* 0x04 - 0x1F */
+	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
+	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
+	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
+	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
+	u32 res2[4];		/* 0x30 - 0x3F */
+	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
+	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
+	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
+	u32 res3[2];		/* 0x4C - 0x53 */
+	u32 bmt1;		/* 0x54 Bus Monitor Timeout 1 */
+} scm2_t;
+
+/* Cross-Bar Switch Module */
+typedef struct xbs_ctrl {
+	u32 prs1;		/* 0x100 Priority Register Slave 1 */
+	u32 res1[3];		/* 0x104 - 0F */
+	u32 crs1;		/* 0x110 Control Register Slave 1 */
+	u32 res2[187];		/* 0x114 - 0x3FF */
+
+	u32 prs4;		/* 0x400 Priority Register Slave 4 */
+	u32 res3[3];		/* 0x404 - 0F */
+	u32 crs4;		/* 0x410 Control Register Slave 4 */
+	u32 res4[123];		/* 0x414 - 0x5FF */
+
+	u32 prs6;		/* 0x600 Priority Register Slave 6 */
+	u32 res5[3];		/* 0x604 - 0F */
+	u32 crs6;		/* 0x610 Control Register Slave 6 */
+	u32 res6[59];		/* 0x614 - 0x6FF */
+
+	u32 prs7;		/* 0x700 Priority Register Slave 7 */
+	u32 res7[3];		/* 0x704 - 0F */
+	u32 crs7;		/* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Flexbus module Chip select registers */
+typedef struct fbcs_ctrl {
+	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
+	u16 res0;
+	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
+	u32 cscr0;		/* 0x08 Chip-Select Control Register 0 */
+
+	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
+	u16 res1;
+	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
+	u32 cscr1;		/* 0x14 Chip-Select Control Register 1 */
+
+	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
+	u16 res2;
+	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
+	u32 cscr2;		/* 0x20 Chip-Select Control Register 2 */
+
+	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
+	u16 res3;
+	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
+	u32 cscr3;		/* 0x2C Chip-Select Control Register 3 */
+
+	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
+	u16 res4;
+	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
+	u32 cscr4;		/* 0x38 Chip-Select Control Register 4 */
+
+	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
+	u16 res5;
+	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
+	u32 cscr5;		/* 0x44 Chip-Select Control Register 5 */
+} fbcs_t;
+
+/* FlexCan module registers */
+typedef struct can_ctrl {
+	u32 mcr;		/* 0x00 Module Configuration register */
+	u32 ctrl;		/* 0x04 Control register */
+	u32 timer;		/* 0x08 Free Running Timer */
+	u32 res1;		/* 0x0C */
+	u32 rxgmask;		/* 0x10 Rx Global Mask */
+	u32 rx14mask;		/* 0x14 RxBuffer 14 Mask */
+	u32 rx15mask;		/* 0x18 RxBuffer 15 Mask */
+	u32 errcnt;		/* 0x1C Error Counter Register */
+	u32 errstat;		/* 0x20 Error and status Register */
+	u32 res2;		/* 0x24 */
+	u32 imask;		/* 0x28 Interrupt Mask Register */
+	u32 res3;		/* 0x2C */
+	u32 iflag;		/* 0x30 Interrupt Flag Register */
+	u32 res4[19];		/* 0x34 - 0x7F */
+	u32 MB0_15[2048];	/* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* System Control Module register 3 */
+typedef struct scm3_ctrl {
+	u8 res1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 wakeup control register */
+	u16 res2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 Core Watchdog Control Register */
+	u8 res3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B Core Watchdog Service Register */
+	u8 res4[2];		/* 0x1C - 0x1D */
+	u8 scmisr;		/* 0x1F Interrupt Status Register */
+	u32 res5;		/* 0x20 */
+	u32 bcr;		/* 0x24 Burst Configuration Register */
+	u32 res6[18];		/* 0x28 - 0x6F */
+	u32 cfadr;		/* 0x70 Core Fault Address Register */
+	u8 res7[4];		/* 0x71 - 0x74 */
+	u8 cfier;		/* 0x75 Core Fault Interrupt Enable Register */
+	u8 cfloc;		/* 0x76 Core Fault Location Register */
+	u8 cfatr;		/* 0x77 Core Fault Attributes Register */
+	u32 res8;		/* 0x78 */
+	u32 cfdtr;		/* 0x7C Core Fault Data Register */
+} scm3_t;
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+	u32 cr;			/* 0x00 Control Register */
+	u32 es;			/* 0x04 Error Status Register */
+	u16 res1[3];		/* 0x08 - 0x0D */
+	u16 erq;		/* 0x0E Enable Request Register */
+	u16 res2[3];		/* 0x10 - 0x15 */
+	u16 eei;		/* 0x16 Enable Error Interrupt Request */
+	u8 serq;		/* 0x18 Set Enable Request */
+	u8 cerq;		/* 0x19 Clear Enable Request */
+	u8 seei;		/* 0x1A Set Enable Error Interrupt Request */
+	u8 ceei;		/* 0x1B Clear Enable Error Interrupt Request */
+	u8 cint;		/* 0x1C Clear Interrupt Enable Register */
+	u8 cerr;		/* 0x1D Clear Error Register */
+	u8 ssrt;		/* 0x1E Set START Bit Register */
+	u8 cdne;		/* 0x1F Clear DONE Status Bit Register */
+	u16 res3[3];		/* 0x20 - 0x25 */
+	u16 intr;		/* 0x26 Interrupt Request Register */
+	u16 res4[3];		/* 0x28 - 0x2D */
+	u16 err;		/* 0x2E Error Register */
+	u32 res5[52];		/* 0x30 - 0xFF */
+	u8 dchpri0;		/* 0x100 Channel 0 Priority Register */
+	u8 dchpri1;		/* 0x101 Channel 1 Priority Register */
+	u8 dchpri2;		/* 0x102 Channel 2 Priority Register */
+	u8 dchpri3;		/* 0x103 Channel 3 Priority Register */
+	u8 dchpri4;		/* 0x104 Channel 4 Priority Register */
+	u8 dchpri5;		/* 0x105 Channel 5 Priority Register */
+	u8 dchpri6;		/* 0x106 Channel 6 Priority Register */
+	u8 dchpri7;		/* 0x107 Channel 7 Priority Register */
+	u8 dchpri8;		/* 0x108 Channel 8 Priority Register */
+	u8 dchpri9;		/* 0x109 Channel 9 Priority Register */
+	u8 dchpri10;		/* 0x110 Channel 10 Priority Register */
+	u8 dchpri11;		/* 0x111 Channel 11 Priority Register */
+	u8 dchpri12;		/* 0x112 Channel 12 Priority Register */
+	u8 dchpri13;		/* 0x113 Channel 13 Priority Register */
+	u8 dchpri14;		/* 0x114 Channel 14 Priority Register */
+	u8 dchpri15;		/* 0x115 Channel 15 Priority Register */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+	u32 saddr;		/* 0x00 Source Address */
+	u16 attr;		/* 0x04 Transfer Attributes */
+	u16 soff;		/* 0x06 Signed Source Address Offset */
+	u32 nbytes;		/* 0x08 Minor Byte Count */
+	u32 slast;		/* 0x0C Last Source Address Adjustment */
+	u32 daddr;		/* 0x10 Destination address */
+	u16 citer;		/* 0x14 Current Minor Loop Link, Major Loop Count */
+	u16 doff;		/* 0x16 Signed Destination Address Offset */
+	u32 dlast_sga;		/* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
+	u16 biter;		/* 0x1C Beginning Minor Loop Link, Major Loop Count */
+	u16 csr;		/* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+	tcd_st tcd[16];
+} tcd_t;
+
+/* Interrupt module registers */
+typedef struct int0_ctrl {
+	/* Interrupt Controller 0 */
+	u32 iprh0;		/* 0x00 Pending Register High */
+	u32 iprl0;		/* 0x04 Pending Register Low */
+	u32 imrh0;		/* 0x08 Mask Register High */
+	u32 imrl0;		/* 0x0C Mask Register Low */
+	u32 frch0;		/* 0x10 Force Register High */
+	u32 frcl0;		/* 0x14 Force Register Low */
+	u16 res1;		/* 0x18 - 0x19 */
+	u16 icfg0;		/* 0x1A Configuration Register */
+	u8 simr0;		/* 0x1C Set Interrupt Mask */
+	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
+	u8 clmask0;		/* 0x1E Current Level Mask */
+	u8 slmask;		/* 0x1F Saved Level Mask */
+	u32 res2[8];		/* 0x20 - 0x3F */
+	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 Software Interrupt Acknowledge */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack0_1;		/* 0xE4 Level n interrupt acknowledge resister */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack0_2;		/* 0xE8 Level n interrupt acknowledge resister */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 Lniack0_3;		/* 0xEC Level n interrupt acknowledge resister */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 Lniack0_4;		/* 0xF0 Level n interrupt acknowledge resister */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack0_5;		/* 0xF4 Level n interrupt acknowledge resister */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack0_6;		/* 0xF8 Level n interrupt acknowledge resister */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 Lniack0_7;		/* 0xFC Level n interrupt acknowledge resister */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+	/* Interrupt Controller 1 */
+	u32 iprh1;		/* 0x00 Pending Register High */
+	u32 iprl1;		/* 0x04 Pending Register Low */
+	u32 imrh1;		/* 0x08 Mask Register High */
+	u32 imrl1;		/* 0x0C Mask Register Low */
+	u32 frch1;		/* 0x10 Force Register High */
+	u32 frcl1;		/* 0x14 Force Register Low */
+	u16 res1;		/* 0x18 */
+	u16 icfg1;		/* 0x1A Configuration Register */
+	u8 simr1;		/* 0x1C Set Interrupt Mask */
+	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
+	u16 res2;		/* 0x1E - 0x1F */
+	u32 res3[8];		/* 0x20 - 0x3F */
+	u8 icr1[64];		/* 0x40 - 0x7F */
+	u32 res4[24];		/* 0x80 - 0xDF */
+	u8 swiack1;		/* 0xE0 Software Interrupt Acknowledge */
+	u8 res5[3];		/* 0xE1 - 0xE3 */
+	u8 Lniack1_1;		/* 0xE4 Level n interrupt acknowledge resister */
+	u8 res6[3];		/* 0xE5 - 0xE7 */
+	u8 Lniack1_2;		/* 0xE8 Level n interrupt acknowledge resister */
+	u8 res7[3];		/* 0xE9 - 0xEB */
+	u8 Lniack1_3;		/* 0xEC Level n interrupt acknowledge resister */
+	u8 res8[3];		/* 0xED - 0xEF */
+	u8 Lniack1_4;		/* 0xF0 Level n interrupt acknowledge resister */
+	u8 res9[3];		/* 0xF1 - 0xF3 */
+	u8 Lniack1_5;		/* 0xF4 Level n interrupt acknowledge resister */
+	u8 resa[3];		/* 0xF5 - 0xF7 */
+	u8 Lniack1_6;		/* 0xF8 Level n interrupt acknowledge resister */
+	u8 resb[3];		/* 0xF9 - 0xFB */
+	u8 Lniack1_7;		/* 0xFC Level n interrupt acknowledge resister */
+	u8 resc[3];		/* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+	/* Global IACK Registers */
+	u8 swiack;		/* 0xE0 Global Software Interrupt Acknowledge */
+	u8 Lniack[7];		/* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
+} intgack_t;
+
+/*I2C module registers */
+typedef struct i2c_ctrl {
+	u8 adr;			/* 0x00 address register */
+	u8 res1[3];		/* 0x01 - 0x03 */
+	u8 fdr;			/* 0x04 frequency divider register */
+	u8 res2[3];		/* 0x05 - 0x07 */
+	u8 cr;			/* 0x08 control register */
+	u8 res3[3];		/* 0x09 - 0x0B */
+	u8 sr;			/* 0x0C status register */
+	u8 res4[3];		/* 0x0D - 0x0F */
+	u8 dr;			/* 0x10 data register */
+	u8 res5[3];		/* 0x11 - 0x13 */
+} i2c_t;
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+	u16 qmr;		/* Mode register */
+	u16 res1;
+	u16 qdlyr;		/* Delay register */
+	u16 res2;
+	u16 qwr;		/* Wrap register */
+	u16 res3;
+	u16 qir;		/* Interrupt register */
+	u16 res4;
+	u16 qar;		/* Address register */
+	u16 res5;
+	u16 qdr;		/* Data register */
+	u16 res6;
+} qspi_t;
+
+/* PWM module registers */
+typedef struct pwm_ctrl {
+	u8 en;			/* 0x00 PWM Enable Register */
+	u8 pol;			/* 0x01 Polarity Register */
+	u8 clk;			/* 0x02 Clock Select Register */
+	u8 prclk;		/* 0x03 Prescale Clock Select Register */
+	u8 cae;			/* 0x04 Center Align Enable Register */
+	u8 ctl;			/* 0x05 Control Register */
+	u8 res1[2];		/* 0x06 - 0x07 */
+	u8 scla;		/* 0x08 Scale A register */
+	u8 sclb;		/* 0x09 Scale B register */
+	u8 res2[2];		/* 0x0A - 0x0B */
+	u8 cnt0;		/* 0x0C Channel 0 Counter register */
+	u8 cnt1;		/* 0x0D Channel 1 Counter register */
+	u8 cnt2;		/* 0x0E Channel 2 Counter register */
+	u8 cnt3;		/* 0x0F Channel 3 Counter register */
+	u8 cnt4;		/* 0x10 Channel 4 Counter register */
+	u8 cnt5;		/* 0x11 Channel 5 Counter register */
+	u8 cnt6;		/* 0x12 Channel 6 Counter register */
+	u8 cnt7;		/* 0x13 Channel 7 Counter register */
+	u8 per0;		/* 0x14 Channel 0 Period register */
+	u8 per1;		/* 0x15 Channel 1 Period register */
+	u8 per2;		/* 0x16 Channel 2 Period register */
+	u8 per3;		/* 0x17 Channel 3 Period register */
+	u8 per4;		/* 0x18 Channel 4 Period register */
+	u8 per5;		/* 0x19 Channel 5 Period register */
+	u8 per6;		/* 0x1A Channel 6 Period register */
+	u8 per7;		/* 0x1B Channel 7 Period register */
+	u8 dty0;		/* 0x1C Channel 0 Duty register */
+	u8 dty1;		/* 0x1D Channel 1 Duty register */
+	u8 dty2;		/* 0x1E Channel 2 Duty register */
+	u8 dty3;		/* 0x1F Channel 3 Duty register */
+	u8 dty4;		/* 0x20 Channel 4 Duty register */
+	u8 dty5;		/* 0x21 Channel 5 Duty register */
+	u8 dty6;		/* 0x22 Channel 6 Duty register */
+	u8 dty7;		/* 0x23 Channel 7 Duty register */
+	u8 sdn;			/* 0x24 Shutdown register */
+	u8 res3[3];		/* 0x25 - 0x27 */
+} pwm_t;
+
+/* Edge Port module registers */
+typedef struct eport_ctrl {
+	u16 par;		/* 0x00 Pin Assignment Register */
+	u8 ddar;		/* 0x02 Data Direction Register */
+	u8 ier;			/* 0x03 Interrupt Enable Register */
+	u8 dr;			/* 0x04 Data Register */
+	u8 pdr;			/* 0x05 Pin Data  Register */
+	u8 fr;			/* 0x06 Flag_Register */
+	u8 res1;
+} eport_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	u16 cr;			/* 0x00 Control register */
+	u16 mr;			/* 0x02 Modulus register */
+	u16 cntr;		/* 0x04 Count register */
+	u16 sr;			/* 0x06 Service register */
+} wdog_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+	u8 rstctrl;		/* 0x00 Reset Controller register */
+	u8 rststat;		/* 0x01 Reset Status register */
+	u16 res1;		/* 0x02 - 0x03 */
+	u16 ccr;		/* 0x04 Chip configuration register */
+	u16 res2;		/* 0x06 */
+	u16 rcon;		/* 0x08 Rreset configuration register */
+	u16 cir;		/* 0x0A Chip identification register */
+	u32 res3;		/* 0x0C */
+	u16 misccr;		/* 0x10 Miscellaneous control register */
+	u16 cdr;		/* 0x12 Clock divider register */
+	u16 uhcsr;		/* 0x14 USB Host controller status register */
+	u16 uocsr;		/* 0x16 USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+	/* Port Output Data Registers */
+	u8 podr_fech;		/* 0x00 */
+	u8 podr_fecl;		/* 0x01 */
+	u8 podr_ssi;		/* 0x02 */
+	u8 podr_busctl;		/* 0x03 */
+	u8 podr_be;		/* 0x04 */
+	u8 podr_cs;		/* 0x05 */
+	u8 podr_pwm;		/* 0x06 */
+	u8 podr_feci2c;		/* 0x07 */
+	u8 res1;		/* 0x08 */
+	u8 podr_uart;		/* 0x09 */
+	u8 podr_qspi;		/* 0x0A */
+	u8 podr_timer;		/* 0x0B */
+	u8 res2;		/* 0x0C */
+	u8 podr_lcddatah;	/* 0x0D */
+	u8 podr_lcddatam;	/* 0x0E */
+	u8 podr_lcddatal;	/* 0x0F */
+	u8 podr_lcdctlh;	/* 0x10 */
+	u8 podr_lcdctll;	/* 0x11 */
+
+	/* Port Data Direction Registers */
+	u16 res3;		/* 0x12 - 0x13 */
+	u8 pddr_fech;		/* 0x14 */
+	u8 pddr_fecl;		/* 0x15 */
+	u8 pddr_ssi;		/* 0x16 */
+	u8 pddr_busctl;		/* 0x17 */
+	u8 pddr_be;		/* 0x18 */
+	u8 pddr_cs;		/* 0x19 */
+	u8 pddr_pwm;		/* 0x1A */
+	u8 pddr_feci2c;		/* 0x1B */
+	u8 res4;		/* 0x1C */
+	u8 pddr_uart;		/* 0x1D */
+	u8 pddr_qspi;		/* 0x1E */
+	u8 pddr_timer;		/* 0x1F */
+	u8 res5;		/* 0x20 */
+	u8 pddr_lcddatah;	/* 0x21 */
+	u8 pddr_lcddatam;	/* 0x22 */
+	u8 pddr_lcddatal;	/* 0x23 */
+	u8 pddr_lcdctlh;	/* 0x24 */
+	u8 pddr_lcdctll;	/* 0x25 */
+	u16 res6;		/* 0x26 - 0x27 */
+
+	/* Port Data Direction Registers */
+	u8 ppd_fech;		/* 0x28 */
+	u8 ppd_fecl;		/* 0x29 */
+	u8 ppd_ssi;		/* 0x2A */
+	u8 ppd_busctl;		/* 0x2B */
+	u8 ppd_be;		/* 0x2C */
+	u8 ppd_cs;		/* 0x2D */
+	u8 ppd_pwm;		/* 0x2E */
+	u8 ppd_feci2c;		/* 0x2F */
+	u8 res7;		/* 0x30 */
+	u8 ppd_uart;		/* 0x31 */
+	u8 ppd_qspi;		/* 0x32 */
+	u8 ppd_timer;		/* 0x33 */
+	u8 res8;		/* 0x34 */
+	u8 ppd_lcddatah;	/* 0x35 */
+	u8 ppd_lcddatam;	/* 0x36 */
+	u8 ppd_lcddatal;	/* 0x37 */
+	u8 ppd_lcdctlh;		/* 0x38 */
+	u8 ppd_lcdctll;		/* 0x39 */
+	u16 res9;		/* 0x3A - 0x3B */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_fech;		/* 0x3C */
+	u8 pclrr_fecl;		/* 0x3D */
+	u8 pclrr_ssi;		/* 0x3E */
+	u8 pclrr_busctl;	/* 0x3F */
+	u8 pclrr_be;		/* 0x40 */
+	u8 pclrr_cs;		/* 0x41 */
+	u8 pclrr_pwm;		/* 0x42 */
+	u8 pclrr_feci2c;	/* 0x43 */
+	u8 res10;		/* 0x44 */
+	u8 pclrr_uart;		/* 0x45 */
+	u8 pclrr_qspi;		/* 0x46 */
+	u8 pclrr_timer;		/* 0x47 */
+	u8 res11;		/* 0x48 */
+	u8 pclrr_lcddatah;	/* 0x49 */
+	u8 pclrr_lcddatam;	/* 0x4A */
+	u8 pclrr_lcddatal;	/* 0x4B */
+	u8 pclrr_lcdctlh;	/* 0x4C */
+	u8 pclrr_lcdctll;	/* 0x4D */
+	u16 res12;		/* 0x4E - 0x4F */
+
+	/* Pin Assignment Registers */
+	u8 par_fec;		/* 0x50 */
+	u8 par_pwm;		/* 0x51 */
+	u8 par_busctl;		/* 0x52 */
+	u8 par_feci2c;		/* 0x53 */
+	u8 par_be;		/* 0x54 */
+	u8 par_cs;		/* 0x55 */
+	u16 par_ssi;		/* 0x56 */
+	u16 par_uart;		/* 0x58 */
+	u16 par_qspi;		/* 0x5A */
+	u8 par_timer;		/* 0x5C */
+	u8 par_lcddata;		/* 0x5D */
+	u16 par_lcdctl;		/* 0x5E */
+	u16 par_irq;		/* 0x60 */
+	u16 res16;		/* 0x62 - 0x63 */
+
+	/* Mode Select Control Registers */
+	u8 mscr_flexbus;	/* 0x64 */
+	u8 mscr_sdram;		/* 0x65 */
+	u16 res17;		/* 0x66 - 0x67 */
+
+	/* Drive Strength Control Registers */
+	u8 dscr_i2c;		/* 0x68 */
+	u8 dscr_pwm;		/* 0x69 */
+	u8 dscr_fec;		/* 0x6A */
+	u8 dscr_uart;		/* 0x6B */
+	u8 dscr_qspi;		/* 0x6C */
+	u8 dscr_timer;		/* 0x6D */
+	u8 dscr_ssi;		/* 0x6E */
+	u8 dscr_lcd;		/* 0x6F */
+	u8 dscr_debug;		/* 0x70 */
+	u8 dscr_clkrst;		/* 0x71 */
+	u8 dscr_irq;		/* 0x72 */
+} gpio_t;
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+	u32 ssar;		/* 0x00 Screen Start Address Register */
+	u32 sr;			/* 0x04 LCD Size Register */
+	u32 vpw;		/* 0x08 Virtual Page Width Register */
+	u32 cpr;		/* 0x0C Cursor Position Register */
+	u32 cwhb;		/* 0x10 Cursor Width Height and Blink Register */
+	u32 ccmr;		/* 0x14 Color Cursor Mapping Register */
+	u32 pcr;		/* 0x18 Panel Configuration Register */
+	u32 hcr;		/* 0x1C Horizontal Configuration Register */
+	u32 vcr;		/* 0x20 Vertical Configuration Register */
+	u32 por;		/* 0x24 Panning Offset Register */
+	u32 scr;		/* 0x28 Sharp Configuration Register */
+	u32 pccr;		/* 0x2C PWM Contrast Control Register */
+	u32 dcr;		/* 0x30 DMA Control Register */
+	u32 rmcr;		/* 0x34 Refresh Mode Control Register */
+	u32 icr;		/* 0x38 Refresh Mode Control Register */
+	u32 ier;		/* 0x3C Interrupt Enable Register */
+	u32 isr;		/* 0x40 Interrupt Status Register */
+	u32 res[4];
+	u32 gwsar;		/* 0x50 Graphic Window Start Address Register */
+	u32 gwsr;		/* 0x54 Graphic Window Size Register */
+	u32 gwvpw;		/* 0x58 Graphic Window Virtual Page Width Register */
+	u32 gwpor;		/* 0x5C Graphic Window Panning Offset Register */
+	u32 gwpr;		/* 0x60 Graphic Window Position Register */
+	u32 gwcr;		/* 0x64 Graphic Window Control Register */
+	u32 gwdcr;		/* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+	u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+	u32 gwlut[255];
+} lcdgw_t;
+
+/* USB OTG module registers */
+typedef struct usb_otg {
+	u32 id;			/* 0x000 Identification Register */
+	u32 hwgeneral;		/* 0x004 General HW Parameters */
+	u32 hwhost;		/* 0x008 Host HW Parameters */
+	u32 hwdev;		/* 0x00C Device HW parameters */
+	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
+	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
+	u32 res1[58];		/* 0x18 - 0xFF */
+	u8 caplength;		/* 0x100 Capability Register Length */
+	u8 res2;		/* 0x101 */
+	u16 hciver;		/* 0x102 Host Interface Version Number */
+	u32 hcsparams;		/* 0x104 Host Structural Parameters */
+	u32 hccparams;		/* 0x108 Host Capability Parameters */
+	u32 res3[5];		/* 0x10C - 0x11F */
+	u16 dciver;		/* 0x120 Device Interface Version Number */
+	u16 res4;		/* 0x122 */
+	u32 dccparams;		/* 0x124 Device Capability Parameters */
+	u32 res5[6];		/* 0x128 - 0x13F */
+	u32 cmd;		/* 0x140 USB Command */
+	u32 sts;		/* 0x144 USB Status */
+	u32 intr;		/* 0x148 USB Interrupt Enable */
+	u32 frindex;		/* 0x14C USB Frame Index */
+	u32 res6;		/* 0x150 */
+	u32 prd_dev;		/* 0x154 Periodic Frame List Base or Device Address */
+	u32 aync_ep;		/* 0x158 Current Asynchronous List or Address at Endpoint List Address */
+	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control */
+	u32 burstsize;		/* 0x160 Master Interface Data Burst Size */
+	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control */
+	u32 res7[6];		/* 0x168 - 0x17F */
+	u32 cfgflag;		/* 0x180 Configure Flag Register */
+	u32 portsc1;		/* 0x184 Port Status/Control */
+	u32 res8[7];		/* 0x188 - 0x1A3 */
+	u32 otgsc;		/* 0x1A4 On The Go Status and Control */
+	u32 mode;		/* 0x1A8 USB mode register */
+	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
+	u32 eptprime;		/* 0x1B0 Endpoint initialization */
+	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
+	u32 eptstat;		/* 0x1B8 Endpoint status */
+	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
+	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
+	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
+	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
+	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
+} usbotg_t;
+
+/* USB Host module registers */
+typedef struct usb_host {
+	u32 id;			/* 0x000 Identification Register */
+	u32 hwgeneral;		/* 0x004 General HW Parameters */
+	u32 hwhost;		/* 0x008 Host HW Parameters */
+	u32 res1;		/* 0x0C */
+	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
+	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
+	u32 res2[58];		/* 0x18 - 0xFF */
+
+	/* Host Controller Capability Register */
+	u8 caplength;		/* 0x100 Capability Register Length */
+	u8 res3;		/* 0x101 */
+	u16 hciver;		/* 0x102 Host Interface Version Number */
+	u32 hcsparams;		/* 0x104 Host Structural Parameters */
+	u32 hccparams;		/* 0x108 Host Capability Parameters */
+	u32 res4[13];		/* 0x10C - 0x13F */
+
+	/* Host Controller Operational Register */
+	u32 cmd;		/* 0x140 USB Command */
+	u32 sts;		/* 0x144 USB Status */
+	u32 intr;		/* 0x148 USB Interrupt Enable */
+	u32 frindex;		/* 0x14C USB Frame Index */
+	u32 res5;		/* 0x150 (ctrl segment register in EHCI spec) */
+	u32 prdlst;		/* 0x154 Periodic Frame List Base Address */
+	u32 aynclst;		/* 0x158 Current Asynchronous List Address */
+	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
+	u32 burstsize;		/* 0x160 Master Interface Data Burst Size (non-ehci) */
+	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control  (non-ehci) */
+	u32 res6[6];		/* 0x168 - 0x17F */
+	u32 cfgflag;		/* 0x180 Configure Flag Register */
+	u32 portsc1;		/* 0x184 Port Status/Control */
+	u32 res7[8];		/* 0x188 - 0x1A7 */
+
+	/* non-ehci registers */
+	u32 mode;		/* 0x1A8 USB mode register */
+	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
+	u32 eptprime;		/* 0x1B0 Endpoint initialization */
+	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
+	u32 eptstat;		/* 0x1B8 Endpoint status */
+	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
+	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
+	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
+	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
+	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
+} usbhost_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+	u32 mode;		/* 0x00 Mode/Extended Mode register */
+	u32 ctrl;		/* 0x04 Control register */
+	u32 cfg1;		/* 0x08 Configuration register 1 */
+	u32 cfg2;		/* 0x0C Configuration register 2 */
+	u32 res1[64];		/* 0x10 - 0x10F */
+	u32 cs0;		/* 0x110 Chip Select 0 Configuration */
+	u32 cs1;		/* 0x114 Chip Select 1 Configuration */
+} sdram_t;
+
+/* Synchronous serial interface */
+typedef struct ssi_ctrl {
+	u32 tx0;		/* 0x00 Transmit Data Register 0 */
+	u32 tx1;		/* 0x04 Transmit Data Register 1 */
+	u32 rx0;		/* 0x08 Receive Data Register 0 */
+	u32 rx1;		/* 0x0C Receive Data Register 1 */
+	u32 cr;			/* 0x10 Control Register */
+	u32 isr;		/* 0x14 Interrupt Status Register */
+	u32 ier;		/* 0x18 Interrupt Enable Register */
+	u32 tcr;		/* 0x1C Transmit Configuration Register */
+	u32 rcr;		/* 0x20 Receive Configuration Register */
+	u32 ccr;		/* 0x24 Clock Control Register */
+	u32 res1;		/* 0x28 */
+	u32 fcsr;		/* 0x2C FIFO Control/Status Register */
+	u32 res2[2];		/* 0x30 - 0x37 */
+	u32 acr;		/* 0x38 AC97 Control Register */
+	u32 acadd;		/* 0x3C AC97 Command Address Register */
+	u32 acdat;		/* 0x40 AC97 Command Data Register */
+	u32 atag;		/* 0x44 AC97 Tag Register */
+	u32 tmask;		/* 0x48 Transmit Time Slot Mask Register */
+	u32 rmask;		/* 0x4C Receive Time Slot Mask Register */
+} ssi_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+	u8 podr;		/* 0x00 Output Divider Register */
+	u8 res1[3];
+	u8 pcr;			/* 0x04 Control Register */
+	u8 res2[3];
+	u8 pmdr;		/* 0x08 Modulation Divider Register */
+	u8 res3[3];
+	u8 pfdr;		/* 0x0C Feedback Divider Register */
+	u8 res4[3];
+} pll_t;
+
+#endif				/* __IMMAP_5329__ */
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 7bbdefba7..cec25d0bf 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -1,8 +1,214 @@
-#ifndef __ASM_M68K_IO_H_
-#define __ASM_M68K_IO_H_
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
-static inline void sync(void)
+ #ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include <asm/byteorder.h>
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)       in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+extern inline void _insb(volatile u8 * port, void *buf, int ns)
 {
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*data++ = *port;
 }
 
-#endif /* __ASM_M68K_IO_H_ */
+extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*port = *data++;
+}
+
+extern inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = __sw16(*port);
+}
+
+extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = __sw16(*data);
+		data++;
+	}
+}
+
+extern inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = __sw32(*port);
+}
+
+extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = __sw32(*data);
+		data++;
+	}
+}
+
+extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = *data++;
+	}
+}
+
+extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = *port;
+}
+
+extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = *data;
+		data++;
+	}
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 * addr)
+{
+	return (int)*addr;
+}
+
+extern inline void out_8(volatile u8 * addr, int val)
+{
+	*addr = (u8) val;
+}
+
+extern inline int in_le16(volatile u16 * addr)
+{
+	return __sw16(*addr);
+}
+
+extern inline int in_be16(volatile u16 * addr)
+{
+	return (*addr & 0xFFFF);
+}
+
+extern inline void out_le16(volatile u16 * addr, int val)
+{
+	*addr = __sw16(val);
+}
+
+extern inline void out_be16(volatile u16 * addr, int val)
+{
+	*addr = (u16) val;
+}
+
+extern inline unsigned in_le32(volatile u32 * addr)
+{
+	return __sw32(*addr);
+}
+
+extern inline unsigned in_be32(volatile u32 * addr)
+{
+	return (*addr);
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+	*addr = __sw32(val);
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+	*addr = val;
+}
+
+#endif				/* __ASM_M68K_IO_H__ */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
new file mode 100644
index 000000000..15bb121ed
--- /dev/null
+++ b/include/asm-m68k/m5329.h
@@ -0,0 +1,2023 @@
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5329_h
+#define mcf5329_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPROT0(x)           (((x)&0x0F)<<28)
+#define SCM_MPR_MPROT1(x)           (((x)&0x0F)<<24)
+#define SCM_MPR_MPROT2(x)           (((x)&0x0F)<<20)
+#define SCM_MPR_MPROT4(x)           (((x)&0x0F)<<12)
+#define SCM_MPR_MPROT5(x)           (((x)&0x0F)<<8)
+#define SCM_MPR_MPROT6(x)           (((x)&0x0F)<<4)
+#define MPROT_MTR                   4
+#define MPROT_MTW                   2
+#define MPROT_MPL                   1
+
+/* Bit definitions and macros for SCM_BMT */
+#define BMT_BME                     (0x08)
+#define BMT_8                       (0x07)
+#define BMT_16                      (0x06)
+#define BMT_32                      (0x05)
+#define BMT_64                      (0x04)
+#define BMT_128                     (0x03)
+#define BMT_256                     (0x02)
+#define BMT_512                     (0x01)
+#define BMT_1024                    (0x00)
+
+/* Bit definitions and macros for SCM_PACRA */
+#define SCM_PACRA_PACR0(x)          (((x)&0x0F)<<28)
+#define SCM_PACRA_PACR1(x)          (((x)&0x0F)<<24)
+#define SCM_PACRA_PACR2(x)          (((x)&0x0F)<<20)
+#define PACR_SP                     4
+#define PACR_WP                     2
+#define PACR_TP                     1
+
+/* Bit definitions and macros for SCM_PACRB */
+#define SCM_PACRB_PACR8(x)          (((x)&0x0F)<<28)
+#define SCM_PACRB_PACR12(x)         (((x)&0x0F)<<12)
+
+/* Bit definitions and macros for SCM_PACRC */
+#define SCM_PACRC_PACR16(x)         (((x)&0x0F)<<28)
+#define SCM_PACRC_PACR17(x)         (((x)&0x0F)<<24)
+#define SCM_PACRC_PACR18(x)         (((x)&0x0F)<<20)
+#define SCM_PACRC_PACR19(x)         (((x)&0x0F)<<16)
+#define SCM_PACRC_PACR21(x)         (((x)&0x0F)<<8)
+#define SCM_PACRC_PACR22(x)         (((x)&0x0F)<<4)
+#define SCM_PACRC_PACR23(x)         (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRD */
+#define SCM_PACRD_PACR24(x)         (((x)&0x0F)<<28)
+#define SCM_PACRD_PACR25(x)         (((x)&0x0F)<<24)
+#define SCM_PACRD_PACR26(x)         (((x)&0x0F)<<20)
+#define SCM_PACRD_PACR28(x)         (((x)&0x0F)<<12)
+#define SCM_PACRD_PACR29(x)         (((x)&0x0F)<<8)
+#define SCM_PACRD_PACR30(x)         (((x)&0x0F)<<4)
+#define SCM_PACRD_PACR31(x)         (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRE */
+#define SCM_PACRE_PACR32(x)         (((x)&0x0F)<<28)
+#define SCM_PACRE_PACR33(x)         (((x)&0x0F)<<24)
+#define SCM_PACRE_PACR34(x)         (((x)&0x0F)<<20)
+#define SCM_PACRE_PACR35(x)         (((x)&0x0F)<<16)
+#define SCM_PACRE_PACR36(x)         (((x)&0x0F)<<12)
+#define SCM_PACRE_PACR37(x)         (((x)&0x0F)<<8)
+#define SCM_PACRE_PACR38(x)         (((x)&0x0F)<<4)
+
+/* Bit definitions and macros for SCM_PACRF */
+#define SCM_PACRF_PACR40(x)         (((x)&0x0F)<<28)
+#define SCM_PACRF_PACR41(x)         (((x)&0x0F)<<24)
+#define SCM_PACRF_PACR42(x)         (((x)&0x0F)<<20)
+#define SCM_PACRF_PACR43(x)         (((x)&0x0F)<<16)
+#define SCM_PACRF_PACR44(x)         (((x)&0x0F)<<12)
+#define SCM_PACRF_PACR45(x)         (((x)&0x0F)<<8)
+#define SCM_PACRF_PACR46(x)         (((x)&0x0F)<<4)
+#define SCM_PACRF_PACR47(x)         (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRG */
+#define SCM_PACRG_PACR48(x)         (((x)&0x0F)<<28)
+
+/* Bit definitions and macros for SCM_PACRH */
+#define SCM_PACRH_PACR56(x)         (((x)&0x0F)<<28)
+#define SCM_PACRH_PACR57(x)         (((x)&0x0F)<<24)
+#define SCM_PACRH_PACR58(x)         (((x)&0x0F)<<20)
+
+/* PACRn Assignments */
+#define PACR0(x)                    SCM_PACRA_PACR0(x)
+#define PACR1(x)                    SCM_PACRA_PACR1(x)
+#define PACR2(x)                    SCM_PACRA_PACR2(x)
+#define PACR8(x)                    SCM_PACRB_PACR8(x)
+#define PACR12(x)                   SCM_PACRB_PACR12(x)
+#define PACR16(x)                   SCM_PACRC_PACR16(x)
+#define PACR17(x)                   SCM_PACRC_PACR17(x)
+#define PACR18(x)                   SCM_PACRC_PACR18(x)
+#define PACR19(x)                   SCM_PACRC_PACR19(x)
+#define PACR21(x)                   SCM_PACRC_PACR21(x)
+#define PACR22(x)                   SCM_PACRC_PACR22(x)
+#define PACR23(x)                   SCM_PACRC_PACR23(x)
+#define PACR24(x)                   SCM_PACRD_PACR24(x)
+#define PACR25(x)                   SCM_PACRD_PACR25(x)
+#define PACR26(x)                   SCM_PACRD_PACR26(x)
+#define PACR28(x)                   SCM_PACRD_PACR28(x)
+#define PACR29(x)                   SCM_PACRD_PACR29(x)
+#define PACR30(x)                   SCM_PACRD_PACR30(x)
+#define PACR31(x)                   SCM_PACRD_PACR31(x)
+#define PACR32(x)                   SCM_PACRE_PACR32(x)
+#define PACR33(x)                   SCM_PACRE_PACR33(x)
+#define PACR34(x)                   SCM_PACRE_PACR34(x)
+#define PACR35(x)                   SCM_PACRE_PACR35(x)
+#define PACR36(x)                   SCM_PACRE_PACR36(x)
+#define PACR37(x)                   SCM_PACRE_PACR37(x)
+#define PACR38(x)                   SCM_PACRE_PACR38(x)
+#define PACR40(x)                   SCM_PACRF_PACR40(x)
+#define PACR41(x)                   SCM_PACRF_PACR41(x)
+#define PACR42(x)                   SCM_PACRF_PACR42(x)
+#define PACR43(x)                   SCM_PACRF_PACR43(x)
+#define PACR44(x)                   SCM_PACRF_PACR44(x)
+#define PACR45(x)                   SCM_PACRF_PACR45(x)
+#define PACR46(x)                   SCM_PACRF_PACR46(x)
+#define PACR47(x)                   SCM_PACRF_PACR47(x)
+#define PACR48(x)                   SCM_PACRG_PACR48(x)
+#define PACR56(x)                   SCM_PACRH_PACR56(x)
+#define PACR57(x)                   SCM_PACRH_PACR57(x)
+#define PACR58(x)                   SCM_PACRH_PACR58(x)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define CWCR_RO                     (0x8000)
+#define CWCR_CWR_WH                 (0x0100)
+#define CWCR_CWE                    (0x0080)
+#define CWRI_WINDOW                 (0x0060)
+#define CWRI_RESET                  (0x0040)
+#define CWRI_INT_RESET              (0x0020)
+#define CWRI_INT                    (0x0000)
+#define CWCR_CWT(x)                 (((x)&0x001F))
+
+/* Bit definitions and macros for SCM_ISR */
+#define SCMISR_CFEI                 (0x02)
+#define SCMISR_CWIC                 (0x01)
+
+/* Bit definitions and macros for SCM_BCR */
+#define BCR_GBR                     (0x00000200)
+#define BCR_GBW                     (0x00000100)
+#define BCR_S7                      (0x00000080)
+#define BCR_S6                      (0x00000040)
+#define BCR_S4                      (0x00000010)
+#define BCR_S1                      (0x00000002)
+
+/* Bit definitions and macros for SCM_CFIER */
+#define CFIER_ECFEI                 (0x01)
+
+/* Bit definitions and macros for SCM_CFLOC */
+#define CFLOC_LOC                   (0x80)
+
+/* Bit definitions and macros for SCM_CFATR */
+#define CFATR_WRITE                 (0x80)
+#define CFATR_SZ32                  (0x20)
+#define CFATR_SZ16                  (0x10)
+#define CFATR_SZ08                  (0x00)
+#define CFATR_CACHE                 (0x08)
+#define CFATR_MODE                  (0x02)
+#define CFATR_TYPE                  (0x01)
+
+/*********************************************************************
+*
+* Random Number Generator (RNG)
+*
+*********************************************************************/
+/* Bit definitions and macros for RNG_RNGCR */
+#define RNGCR_CI                    (0x00000008)
+#define RNGCR_IM                    (0x00000004)
+#define RNGCR_HA                    (0x00000002)
+#define RNGCR_GO                    (0x00000001)
+
+/* Bit definitions and macros for RNG_RNGSR */
+#define RNGSR_OFS(x)                (((x)&0xFF)<<16)
+#define RNGSR_OFL(x)                (((x)&0xFF)<<8)
+#define RNGSR_EI                    (0x00000008)
+#define RNGSR_FUF                   (0x00000004)
+#define RNGSR_LRS                   (0x00000002)
+#define RNGSR_SV                    (0x00000001)
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+/* Bit definitions and macros for FBCS_CSAR */
+#define CSAR_BA(x)                  (((x)&0xFFFF)<<16)
+
+/* Bit definitions and macros for FBCS_CSMR */
+#define CSMR_BAM(x)                 (((x)&0xFFFF)<<16)
+#define CSMR_BAM_4G                 (0xFFFF0000)
+#define CSMR_BAM_2G                 (0x7FFF0000)
+#define CSMR_BAM_1G                 (0x3FFF0000)
+#define CSMR_BAM_1024M              (0x3FFF0000)
+#define CSMR_BAM_512M               (0x1FFF0000)
+#define CSMR_BAM_256M               (0x0FFF0000)
+#define CSMR_BAM_128M               (0x07FF0000)
+#define CSMR_BAM_64M                (0x03FF0000)
+#define CSMR_BAM_32M                (0x01FF0000)
+#define CSMR_BAM_16M                (0x00FF0000)
+#define CSMR_BAM_8M                 (0x007F0000)
+#define CSMR_BAM_4M                 (0x003F0000)
+#define CSMR_BAM_2M                 (0x001F0000)
+#define CSMR_BAM_1M                 (0x000F0000)
+#define CSMR_BAM_1024K              (0x000F0000)
+#define CSMR_BAM_512K               (0x00070000)
+#define CSMR_BAM_256K               (0x00030000)
+#define CSMR_BAM_128K               (0x00010000)
+#define CSMR_BAM_64K                (0x00000000)
+#define CSMR_WP                     (0x00000100)
+#define CSMR_V                      (0x00000001)
+
+/* Bit definitions and macros for FBCS_CSCR */
+#define CSCR_SWS(x)                 (((x)&0x3F)<<26)
+#define CSCR_ASET(x)                (((x)&0x03)<<20)
+#define CSCR_SWSEN                  (0x00800000)
+#define CSCR_ASET_4CLK              (0x00300000)
+#define CSCR_ASET_3CLK              (0x00200000)
+#define CSCR_ASET_2CLK              (0x00100000)
+#define CSCR_ASET_1CLK              (0x00000000)
+#define CSCR_RDAH(x)                (((x)&0x03)<<18)
+#define CSCR_RDAH_4CYC              (0x000C0000)
+#define CSCR_RDAH_3CYC              (0x00080000)
+#define CSCR_RDAH_2CYC              (0x00040000)
+#define CSCR_RDAH_1CYC              (0x00000000)
+#define CSCR_WRAH(x)                (((x)&0x03)<<16)
+#define CSCR_WDAH_4CYC              (0x00003000)
+#define CSCR_WDAH_3CYC              (0x00002000)
+#define CSCR_WDAH_2CYC              (0x00001000)
+#define CSCR_WDAH_1CYC              (0x00000000)
+#define CSCR_WS(x)                  (((x)&0x3F)<<10)
+#define CSCR_SBM                    (0x00000200)
+#define CSCR_AA                     (0x00000100)
+#define CSCR_PS_MASK                (0x000000C0)
+#define CSCR_PS_32                  (0x00000000)
+#define CSCR_PS_16                  (0x00000080)
+#define CSCR_PS_8                   (0x00000040)
+#define CSCR_BEM                    (0x00000020)
+#define CSCR_BSTR                   (0x00000010)
+#define CSCR_BSTW                   (0x00000008)
+
+/*********************************************************************
+* FlexCAN Module (CAN)
+*********************************************************************/
+/* Bit definitions and macros for CAN_CANMCR */
+#define CANMCR_MDIS                 (0x80000000)
+#define CANMCR_FRZ                  (0x40000000)
+#define CANMCR_HALT                 (0x10000000)
+#define CANMCR_NORDY                (0x08000000)
+#define CANMCR_SOFTRST              (0x02000000)
+#define CANMCR_FRZACK               (0x01000000)
+#define CANMCR_SUPV                 (0x00800000)
+#define CANMCR_LPMACK               (0x00100000)
+#define CANMCR_MAXMB(x)             (((x)&0x0F))
+
+/* Bit definitions and macros for CAN_CANCTRL */
+#define CANCTRL_PRESDIV(x)          (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x)              (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x)            (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x)            (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK             (0x00008000)
+#define CANCTRL_ERRMSK              (0x00004000)
+#define CANCTRL_CLKSRC              (0x00002000)
+#define CANCTRL_LPB                 (0x00001000)
+#define CANCTRL_SMP                 (0x00000080)
+#define CANCTRL_BOFFREC             (0x00000040)
+#define CANCTRL_TSYNC               (0x00000020)
+#define CANCTRL_LBUF                (0x00000010)
+#define CANCTRL_LOM                 (0x00000008)
+#define CANCTRL_PROPSEG(x)          (((x)&0x07))
+
+/* Bit definitions and macros for CAN_TIMER */
+#define TIMER_TIMER(x)              ((x)&0xFFFF)
+
+/* Bit definitions and macros for CAN_RXGMASK */
+#define RXGMASK_MI(x)               ((x)&0x1FFFFFFF)
+
+/* Bit definitions and macros for CAN_ERRCNT */
+#define ERRCNT_TXECTR(x)            (((x)&0xFF))
+#define ERRCNT_RXECTR(x)            (((x)&0xFF)<<8)
+
+/* Bit definitions and macros for CAN_ERRSTAT */
+#define ERRSTAT_BITERR1             (0x00008000)
+#define ERRSTAT_BITERR0             (0x00004000)
+#define ERRSTAT_ACKERR              (0x00002000)
+#define ERRSTAT_CRCERR              (0x00001000)
+#define ERRSTAT_FRMERR              (0x00000800)
+#define ERRSTAT_STFERR              (0x00000400)
+#define ERRSTAT_TXWRN               (0x00000200)
+#define ERRSTAT_RXWRN               (0x00000100)
+#define ERRSTAT_IDLE                (0x00000080)
+#define ERRSTAT_TXRX                (0x00000040)
+#define ERRSTAT_FLT_BUSOFF          (0x00000020)
+#define ERRSTAT_FLT_PASSIVE         (0x00000010)
+#define ERRSTAT_FLT_ACTIVE          (0x00000000)
+#define ERRSTAT_BOFFINT             (0x00000004)
+#define ERRSTAT_ERRINT              (0x00000002)
+#define ERRSTAT_WAKINT              (0x00000001)
+
+/* Bit definitions and macros for CAN_IMASK */
+#define IMASK_BUF15M                (0x00008000)
+#define IMASK_BUF14M                (0x00004000)
+#define IMASK_BUF13M                (0x00002000)
+#define IMASK_BUF12M                (0x00001000)
+#define IMASK_BUF11M                (0x00000800)
+#define IMASK_BUF10M                (0x00000400)
+#define IMASK_BUF9M                 (0x00000200)
+#define IMASK_BUF8M                 (0x00000100)
+#define IMASK_BUF7M                 (0x00000080)
+#define IMASK_BUF6M                 (0x00000040)
+#define IMASK_BUF5M                 (0x00000020)
+#define IMASK_BUF4M                 (0x00000010)
+#define IMASK_BUF3M                 (0x00000008)
+#define IMASK_BUF2M                 (0x00000004)
+#define IMASK_BUF1M                 (0x00000002)
+#define IMASK_BUF0M                 (0x00000001)
+
+/* Bit definitions and macros for CAN_IFLAG */
+#define IFLAG_BUF15I                (0x00008000)
+#define IFLAG_BUF14I                (0x00004000)
+#define IFLAG_BUF13I                (0x00002000)
+#define IFLAG_BUF12I                (0x00001000)
+#define IFLAG_BUF11I                (0x00000800)
+#define IFLAG_BUF10I                (0x00000400)
+#define IFLAG_BUF9I                 (0x00000200)
+#define IFLAG_BUF8I                 (0x00000100)
+#define IFLAG_BUF7I                 (0x00000080)
+#define IFLAG_BUF6I                 (0x00000040)
+#define IFLAG_BUF5I                 (0x00000020)
+#define IFLAG_BUF4I                 (0x00000010)
+#define IFLAG_BUF3I                 (0x00000008)
+#define IFLAG_BUF2I                 (0x00000004)
+#define IFLAG_BUF1I                 (0x00000002)
+#define IFLAG_BUF0I                 (0x00000001)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INTC0_EPORT                 INTC_IPRL_INT1
+
+#define INT0_LO_RSVD0				(0)
+#define INT0_LO_EPORT1				(1)
+#define INT0_LO_EPORT2				(2)
+#define INT0_LO_EPORT3				(3)
+#define INT0_LO_EPORT4				(4)
+#define INT0_LO_EPORT5				(5)
+#define INT0_LO_EPORT6				(6)
+#define INT0_LO_EPORT7				(7)
+#define INT0_LO_EDMA_00				(8)
+#define INT0_LO_EDMA_01				(9)
+#define INT0_LO_EDMA_02				(10)
+#define INT0_LO_EDMA_03				(11)
+#define INT0_LO_EDMA_04				(12)
+#define INT0_LO_EDMA_05				(13)
+#define INT0_LO_EDMA_06				(14)
+#define INT0_LO_EDMA_07				(15)
+#define INT0_LO_EDMA_08				(16)
+#define INT0_LO_EDMA_09				(17)
+#define INT0_LO_EDMA_10				(18)
+#define INT0_LO_EDMA_11				(19)
+#define INT0_LO_EDMA_12				(20)
+#define INT0_LO_EDMA_13				(21)
+#define INT0_LO_EDMA_14				(22)
+#define INT0_LO_EDMA_15				(23)
+#define INT0_LO_EDMA_ERR			(24)
+#define INT0_LO_SCM					(25)
+#define INT0_LO_UART0				(26)
+#define INT0_LO_UART1				(27)
+#define INT0_LO_UART2				(28)
+#define INT0_LO_RSVD1				(29)
+#define INT0_LO_I2C					(30)
+#define INT0_LO_QSPI				(31)
+#define INT0_HI_DTMR0				(32)
+#define INT0_HI_DTMR1				(33)
+#define INT0_HI_DTMR2				(34)
+#define INT0_HI_DTMR3				(35)
+#define INT0_HI_FEC_TXF				(36)
+#define INT0_HI_FEC_TXB				(37)
+#define INT0_HI_FEC_UN				(38)
+#define INT0_HI_FEC_RL				(39)
+#define INT0_HI_FEC_RXF				(40)
+#define INT0_HI_FEC_RXB				(41)
+#define INT0_HI_FEC_MII				(42)
+#define INT0_HI_FEC_LC				(43)
+#define INT0_HI_FEC_HBERR			(44)
+#define INT0_HI_FEC_GRA				(45)
+#define INT0_HI_FEC_EBERR			(46)
+#define INT0_HI_FEC_BABT			(47)
+#define INT0_HI_FEC_BABR			(48)
+/* 49 - 61 Reserved */
+#define INT0_HI_SCM					(62)
+
+/*#define INT1_HI_				*/
+
+/* Bit definitions and macros for INTC_IPRH */
+#define INTC_IPRH_INT63             (0x80000000)
+#define INTC_IPRH_INT62             (0x40000000)
+#define INTC_IPRH_INT61             (0x20000000)
+#define INTC_IPRH_INT60             (0x10000000)
+#define INTC_IPRH_INT59             (0x08000000)
+#define INTC_IPRH_INT58             (0x04000000)
+#define INTC_IPRH_INT57             (0x02000000)
+#define INTC_IPRH_INT56             (0x01000000)
+#define INTC_IPRH_INT55             (0x00800000)
+#define INTC_IPRH_INT54             (0x00400000)
+#define INTC_IPRH_INT53             (0x00200000)
+#define INTC_IPRH_INT52             (0x00100000)
+#define INTC_IPRH_INT51             (0x00080000)
+#define INTC_IPRH_INT50             (0x00040000)
+#define INTC_IPRH_INT49             (0x00020000)
+#define INTC_IPRH_INT48             (0x00010000)
+#define INTC_IPRH_INT47             (0x00008000)
+#define INTC_IPRH_INT46             (0x00004000)
+#define INTC_IPRH_INT45             (0x00002000)
+#define INTC_IPRH_INT44             (0x00001000)
+#define INTC_IPRH_INT43             (0x00000800)
+#define INTC_IPRH_INT42             (0x00000400)
+#define INTC_IPRH_INT41             (0x00000200)
+#define INTC_IPRH_INT40             (0x00000100)
+#define INTC_IPRH_INT39             (0x00000080)
+#define INTC_IPRH_INT38             (0x00000040)
+#define INTC_IPRH_INT37             (0x00000020)
+#define INTC_IPRH_INT36             (0x00000010)
+#define INTC_IPRH_INT35             (0x00000008)
+#define INTC_IPRH_INT34             (0x00000004)
+#define INTC_IPRH_INT33             (0x00000002)
+#define INTC_IPRH_INT32             (0x00000001)
+
+/* Bit definitions and macros for INTC_IPRL */
+#define INTC_IPRL_INT31             (0x80000000)
+#define INTC_IPRL_INT30             (0x40000000)
+#define INTC_IPRL_INT29             (0x20000000)
+#define INTC_IPRL_INT28             (0x10000000)
+#define INTC_IPRL_INT27             (0x08000000)
+#define INTC_IPRL_INT26             (0x04000000)
+#define INTC_IPRL_INT25             (0x02000000)
+#define INTC_IPRL_INT24             (0x01000000)
+#define INTC_IPRL_INT23             (0x00800000)
+#define INTC_IPRL_INT22             (0x00400000)
+#define INTC_IPRL_INT21             (0x00200000)
+#define INTC_IPRL_INT20             (0x00100000)
+#define INTC_IPRL_INT19             (0x00080000)
+#define INTC_IPRL_INT18             (0x00040000)
+#define INTC_IPRL_INT17             (0x00020000)
+#define INTC_IPRL_INT16             (0x00010000)
+#define INTC_IPRL_INT15             (0x00008000)
+#define INTC_IPRL_INT14             (0x00004000)
+#define INTC_IPRL_INT13             (0x00002000)
+#define INTC_IPRL_INT12             (0x00001000)
+#define INTC_IPRL_INT11             (0x00000800)
+#define INTC_IPRL_INT10             (0x00000400)
+#define INTC_IPRL_INT9              (0x00000200)
+#define INTC_IPRL_INT8              (0x00000100)
+#define INTC_IPRL_INT7              (0x00000080)
+#define INTC_IPRL_INT6              (0x00000040)
+#define INTC_IPRL_INT5              (0x00000020)
+#define INTC_IPRL_INT4              (0x00000010)
+#define INTC_IPRL_INT3              (0x00000008)
+#define INTC_IPRL_INT2              (0x00000004)
+#define INTC_IPRL_INT1              (0x00000002)
+#define INTC_IPRL_INT0              (0x00000001)
+
+/* Bit definitions and macros for INTC_ICONFIG */
+#define INTC_ICFG_ELVLPRI7          (0x8000)
+#define INTC_ICFG_ELVLPRI6          (0x4000)
+#define INTC_ICFG_ELVLPRI5          (0x2000)
+#define INTC_ICFG_ELVLPRI4          (0x1000)
+#define INTC_ICFG_ELVLPRI3          (0x0800)
+#define INTC_ICFG_ELVLPRI2          (0x0400)
+#define INTC_ICFG_ELVLPRI1          (0x0200)
+#define INTC_ICFG_EMASK             (0x0020)
+
+/* Bit definitions and macros for INTC_SIMR */
+#define INTC_SIMR_SALL              (0x40)
+#define INTC_SIMR_SIMR(x)           ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CIMR */
+#define INTC_CIMR_CALL              (0x40)
+#define INTC_CIMR_CIMR(x)           ((x)&0x3F)
+
+/* Bit definitions and macros for INTC_CLMASK */
+#define INTC_CLMASK_CLMASK(x)       ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_SLMASK */
+#define INTC_SLMASK_SLMASK(x)       ((x)&0x0F)
+
+/* Bit definitions and macros for INTC_ICR */
+#define INTC_ICR_IL(x)              ((x)&0x07)
+
+/*********************************************************************
+* I2C Module (I2C)
+*********************************************************************/
+/* Bit definitions and macros for I2C_AR */
+#define I2C_AR_ADR(x)               (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for I2C_FDR */
+#define I2C_FDR_IC(x)               ((x)&0x3F)
+
+/* Bit definitions and macros for I2C_CR */
+#define I2C_CR_IEN                  (0x80)
+#define I2C_CR_IIEN                 (0x40)
+#define I2C_CR_MSTA                 (0x20)
+#define I2C_CR_MTX                  (0x10)
+#define I2C_CR_TXAK                 (0x08)
+#define I2C_CR_RSTA                 (0x04)
+
+/* Bit definitions and macros for I2C_SR */
+#define I2C_SR_ICF                  (0x80)
+#define I2C_SR_IAAS                 (0x40)
+#define I2C_SR_IBB                  (0x20)
+#define I2C_SR_IAL                  (0x10)
+#define I2C_SR_SRW                  (0x04)
+#define I2C_SR_IIF                  (0x02)
+#define I2C_SR_RXAK                 (0x01)
+
+/* Bit definitions and macros for I2C_ICR */
+#define I2C_ICR_BNBE                (0x08)
+#define I2C_ICR_TE                  (0x04)
+#define I2C_ICR_RE                  (0x02)
+#define I2C_ICR_IE                  (0x01)
+
+/*********************************************************************
+* Queued Serial Peripheral Interface (QSPI)
+*********************************************************************/
+/* Bit definitions and macros for QSPI_QMR */
+#define QSPI_QMR_MSTR               (0x8000)
+#define QSPI_QMR_DOHIE              (0x4000)
+#define QSPI_QMR_BITS(x)            (((x)&0x000F)<<10)
+#define QSPI_QMR_CPOL               (0x0200)
+#define QSPI_QMR_CPHA               (0x0100)
+#define QSPI_QMR_BAUD(x)            ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QDLYR */
+#define QSPI_QDLYR_SPE              (0x8000)
+#define QSPI_QDLYR_QCD(x)           (((x)&0x007F)<<8)
+#define QSPI_QDLYR_DTL(x)           ((x)&0x00FF)
+
+/* Bit definitions and macros for QSPI_QWR */
+#define QSPI_QWR_NEWQP(x)           ((x)&0x000F)
+#define QSPI_QWR_ENDQP(x)           (((x)&0x000F)<<8)
+#define QSPI_QWR_CSIV               (0x1000)
+#define QSPI_QWR_WRTO               (0x2000)
+#define QSPI_QWR_WREN               (0x4000)
+#define QSPI_QWR_HALT               (0x8000)
+
+/* Bit definitions and macros for QSPI_QIR */
+#define QSPI_QIR_WCEFB              (0x8000)
+#define QSPI_QIR_ABRTB              (0x4000)
+#define QSPI_QIR_ABRTL              (0x1000)
+#define QSPI_QIR_WCEFE              (0x0800)
+#define QSPI_QIR_ABRTE              (0x0400)
+#define QSPI_QIR_SPIFE              (0x0100)
+#define QSPI_QIR_WCEF               (0x0008)
+#define QSPI_QIR_ABRT               (0x0004)
+#define QSPI_QIR_SPIF               (0x0001)
+
+/* Bit definitions and macros for QSPI_QAR */
+#define QSPI_QAR_ADDR(x)            ((x)&0x003F)
+#define QSPI_QAR_TRANS              (0x0000)
+#define QSPI_QAR_RECV               (0x0010)
+#define QSPI_QAR_CMD                (0x0020)
+
+/* Bit definitions and macros for QSPI_QDR */
+#define QSPI_QDR_CONT               (0x8000)
+#define QSPI_QDR_BITSE              (0x4000)
+#define QSPI_QDR_DT                 (0x2000)
+#define QSPI_QDR_DSCK               (0x1000)
+#define QSPI_QDR_QSPI_CS3           (0x0800)
+#define QSPI_QDR_QSPI_CS2           (0x0400)
+#define QSPI_QDR_QSPI_CS1           (0x0200)
+#define QSPI_QDR_QSPI_CS0           (0x0100)
+
+/*********************************************************************
+* Pulse Width Modulation (PWM)
+*********************************************************************/
+/* Bit definitions and macros for PWM_E */
+#define PWM_EN_PWME7                (0x80)
+#define PWM_EN_PWME5                (0x20)
+#define PWM_EN_PWME3                (0x08)
+#define PWM_EN_PWME1                (0x02)
+
+/* Bit definitions and macros for PWM_POL */
+#define PWM_POL_PPOL7               (0x80)
+#define PWM_POL_PPOL5               (0x20)
+#define PWM_POL_PPOL3               (0x08)
+#define PWM_POL_PPOL1               (0x02)
+
+/* Bit definitions and macros for PWM_CLK */
+#define PWM_CLK_PCLK7               (0x80)
+#define PWM_CLK_PCLK5               (0x20)
+#define PWM_CLK_PCLK3               (0x08)
+#define PWM_CLK_PCLK1               (0x02)
+
+/* Bit definitions and macros for PWM_PRCLK */
+#define PWM_PRCLK_PCKB(x)           (((x)&0x07)<<4)
+#define PWM_PRCLK_PCKA(x)           ((x)&0x07)
+
+/* Bit definitions and macros for PWM_CAE */
+#define PWM_CAE_CAE7                (0x80)
+#define PWM_CAE_CAE5                (0x20)
+#define PWM_CAE_CAE3                (0x08)
+#define PWM_CAE_CAE1                (0x02)
+
+/* Bit definitions and macros for PWM_CTL */
+#define PWM_CTL_CON67               (0x80)
+#define PWM_CTL_CON45               (0x40)
+#define PWM_CTL_CON23               (0x20)
+#define PWM_CTL_CON01               (0x10)
+#define PWM_CTL_PSWAR               (0x08)
+#define PWM_CTL_PFRZ                (0x04)
+
+/* Bit definitions and macros for PWM_SDN */
+#define PWM_SDN_IF                  (0x80)
+#define PWM_SDN_IE                  (0x40)
+#define PWM_SDN_RESTART             (0x20)
+#define PWM_SDN_LVL                 (0x10)
+#define PWM_SDN_PWM7IN              (0x04)
+#define PWM_SDN_PWM7IL              (0x02)
+#define PWM_SDN_SDNEN               (0x01)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT                (0x0008)
+#define WTM_WCR_DOZE                (0x0004)
+#define WTM_WCR_HALTED              (0x0002)
+#define WTM_WCR_EN                  (0x0001)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_CSC(x)              (((x)&0x0003)<<8|0x0001)
+#define CCM_CCR_LIMP                (0x0041)
+#define CCM_CCR_LOAD                (0x0021)
+#define CCM_CCR_BOOTPS(x)           (((x)&0x0003)<<3|0x0001)
+#define CCM_CCR_OSC_MODE            (0x0005)
+#define CCM_CCR_PLL_MODE            (0x0003)
+#define CCM_CCR_RESERVED            (0x0001)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_CSC(x)             (((x)&0x0003)<<8|0x0001)
+#define CCM_RCON_LIMP               (0x0041)
+#define CCM_RCON_LOAD               (0x0021)
+#define CCM_RCON_BOOTPS(x)          (((x)&0x0003)<<3|0x0001)
+#define CCM_RCON_OSC_MODE           (0x0005)
+#define CCM_RCON_PLL_MODE           (0x0003)
+#define CCM_RCON_RESERVED           (0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x)              (((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x)              ((x)&0x003F)
+
+/* Bit definitions and macros for CCM_MISCCR */
+#define CCM_MISCCR_PLL_LOCK         (0x2000)
+#define CCM_MISCCR_LIMP             (0x1000)
+#define CCM_MISCCR_LCD_CHEN         (0x0100)
+#define CCM_MISCCR_SSI_PUE          (0x0080)
+#define CCM_MISCCR_SSI_PUS          (0x0040)
+#define CCM_MISCCR_TIM_DMA          (0x0020)
+#define CCM_MISCCR_SSI_SRC          (0x0010)
+#define CCM_MISCCR_USBDIV           (0x0002)
+#define CCM_MISCCR_USBSRC           (0x0001)
+
+/* Bit definitions and macros for CCM_CDR */
+#define CCM_CDR_LPDIV(x)            (((x)&0x000F)<<8)
+#define CCM_CDR_SSIDIV(x)           ((x)&0x000F)
+
+/* Bit definitions and macros for CCM_UHCSR */
+#define CCM_UHCSR_PORTIND(x)        (((x)&0x0003)<<14)
+#define CCM_UHCSR_WKUP              (0x0004)
+#define CCM_UHCSR_UHMIE             (0x0002)
+#define CCM_UHCSR_XPDE              (0x0001)
+
+/* Bit definitions and macros for CCM_UOCSR */
+#define CCM_UOCSR_PORTIND(x)        (((x)&0x0003)<<14)
+#define CCM_UOCSR_DPPD              (0x2000)
+#define CCM_UOCSR_DMPD              (0x1000)
+#define CCM_UOCSR_DRV_VBUS          (0x0800)
+#define CCM_UOCSR_CRG_VBUS          (0x0400)
+#define CCM_UOCSR_DCR_VBUS          (0x0200)
+#define CCM_UOCSR_DPPU              (0x0100)
+#define CCM_UOCSR_AVLD              (0x0080)
+#define CCM_UOCSR_BVLD              (0x0040)
+#define CCM_UOCSR_VVLD              (0x0020)
+#define CCM_UOCSR_SEND              (0x0010)
+#define CCM_UOCSR_PWRFLT            (0x0008)
+#define CCM_UOCSR_WKUP              (0x0004)
+#define CCM_UOCSR_UOMIE             (0x0002)
+#define CCM_UOCSR_XPDE              (0x0001)
+
+/* not done yet */
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR_FECH_L */
+#define GPIO_PODR_FECH_L7           (0x80)
+#define GPIO_PODR_FECH_L6           (0x40)
+#define GPIO_PODR_FECH_L5           (0x20)
+#define GPIO_PODR_FECH_L4           (0x10)
+#define GPIO_PODR_FECH_L3           (0x08)
+#define GPIO_PODR_FECH_L2           (0x04)
+#define GPIO_PODR_FECH_L1           (0x02)
+#define GPIO_PODR_FECH_L0           (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_SSI */
+#define GPIO_PODR_SSI_4             (0x10)
+#define GPIO_PODR_SSI_3             (0x08)
+#define GPIO_PODR_SSI_2             (0x04)
+#define GPIO_PODR_SSI_1             (0x02)
+#define GPIO_PODR_SSI_0             (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BUSCTL */
+#define GPIO_PODR_BUSCTL_3          (0x08)
+#define GPIO_PODR_BUSCTL_2          (0x04)
+#define GPIO_PODR_BUSCTL_1          (0x02)
+#define GPIO_PODR_BUSCTL_0          (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BE */
+#define GPIO_PODR_BE_3              (0x08)
+#define GPIO_PODR_BE_2              (0x04)
+#define GPIO_PODR_BE_1              (0x02)
+#define GPIO_PODR_BE_0              (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_CS */
+#define GPIO_PODR_CS_5              (0x20)
+#define GPIO_PODR_CS_4              (0x10)
+#define GPIO_PODR_CS_3              (0x08)
+#define GPIO_PODR_CS_2              (0x04)
+#define GPIO_PODR_CS_1              (0x02)
+
+/* Bit definitions and macros for GPIO_PODR_PWM */
+#define GPIO_PODR_PWM_5             (0x20)
+#define GPIO_PODR_PWM_4             (0x10)
+#define GPIO_PODR_PWM_3             (0x08)
+#define GPIO_PODR_PWM_2             (0x04)
+
+/* Bit definitions and macros for GPIO_PODR_FECI2C */
+#define GPIO_PODR_FECI2C_3          (0x08)
+#define GPIO_PODR_FECI2C_2          (0x04)
+#define GPIO_PODR_FECI2C_1          (0x02)
+#define GPIO_PODR_FECI2C_0          (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_UART */
+#define GPIO_PODR_UART_7            (0x80)
+#define GPIO_PODR_UART_6            (0x40)
+#define GPIO_PODR_UART_5            (0x20)
+#define GPIO_PODR_UART_4            (0x10)
+#define GPIO_PODR_UART_3            (0x08)
+#define GPIO_PODR_UART_2            (0x04)
+#define GPIO_PODR_UART_1            (0x02)
+#define GPIO_PODR_UART_0            (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_QSPI */
+#define GPIO_PODR_QSPI_5            (0x20)
+#define GPIO_PODR_QSPI_4            (0x10)
+#define GPIO_PODR_QSPI_3            (0x08)
+#define GPIO_PODR_QSPI_2            (0x04)
+#define GPIO_PODR_QSPI_1            (0x02)
+#define GPIO_PODR_QSPI_0            (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_TIMER */
+#define GPIO_PODR_TIMER_3           (0x08)
+#define GPIO_PODR_TIMER_2           (0x04)
+#define GPIO_PODR_TIMER_1           (0x02)
+#define GPIO_PODR_TIMER_0           (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAH */
+#define GPIO_PODR_LCDDATAH_1        (0x02)
+#define GPIO_PODR_LCDDATAH_0        (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAM */
+#define GPIO_PODR_LCDDATAM_7        (0x80)
+#define GPIO_PODR_LCDDATAM_6        (0x40)
+#define GPIO_PODR_LCDDATAM_5        (0x20)
+#define GPIO_PODR_LCDDATAM_4        (0x10)
+#define GPIO_PODR_LCDDATAM_3        (0x08)
+#define GPIO_PODR_LCDDATAM_2        (0x04)
+#define GPIO_PODR_LCDDATAM_1        (0x02)
+#define GPIO_PODR_LCDDATAM_0        (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAL */
+#define GPIO_PODR_LCDDATAL_7        (0x80)
+#define GPIO_PODR_LCDDATAL_6        (0x40)
+#define GPIO_PODR_LCDDATAL_5        (0x20)
+#define GPIO_PODR_LCDDATAL_4        (0x10)
+#define GPIO_PODR_LCDDATAL_3        (0x08)
+#define GPIO_PODR_LCDDATAL_2        (0x04)
+#define GPIO_PODR_LCDDATAL_1        (0x02)
+#define GPIO_PODR_LCDDATAL_0        (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLH */
+#define GPIO_PODR_LCDCTLH_0         (0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLL */
+#define GPIO_PODR_LCDCTLL_7         (0x80)
+#define GPIO_PODR_LCDCTLL_6         (0x40)
+#define GPIO_PODR_LCDCTLL_5         (0x20)
+#define GPIO_PODR_LCDCTLL_4         (0x10)
+#define GPIO_PODR_LCDCTLL_3         (0x08)
+#define GPIO_PODR_LCDCTLL_2         (0x04)
+#define GPIO_PODR_LCDCTLL_1         (0x02)
+#define GPIO_PODR_LCDCTLL_0         (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_FECH */
+#define GPIO_PDDR_FECH_L7           (0x80)
+#define GPIO_PDDR_FECH_L6           (0x40)
+#define GPIO_PDDR_FECH_L5           (0x20)
+#define GPIO_PDDR_FECH_L4           (0x10)
+#define GPIO_PDDR_FECH_L3           (0x08)
+#define GPIO_PDDR_FECH_L2           (0x04)
+#define GPIO_PDDR_FECH_L1           (0x02)
+#define GPIO_PDDR_FECH_L0           (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_SSI */
+#define GPIO_PDDR_SSI_4             (0x10)
+#define GPIO_PDDR_SSI_3             (0x08)
+#define GPIO_PDDR_SSI_2             (0x04)
+#define GPIO_PDDR_SSI_1             (0x02)
+#define GPIO_PDDR_SSI_0             (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BUSCTL */
+#define GPIO_PDDR_BUSCTL_3          (0x08)
+#define GPIO_PDDR_BUSCTL_2          (0x04)
+#define GPIO_PDDR_BUSCTL_1          (0x02)
+#define GPIO_PDDR_BUSCTL_0          (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BE */
+#define GPIO_PDDR_BE_3              (0x08)
+#define GPIO_PDDR_BE_2              (0x04)
+#define GPIO_PDDR_BE_1              (0x02)
+#define GPIO_PDDR_BE_0              (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_CS */
+#define GPIO_PDDR_CS_1                  (0x02)
+#define GPIO_PDDR_CS_2                  (0x04)
+#define GPIO_PDDR_CS_3                  (0x08)
+#define GPIO_PDDR_CS_4                  (0x10)
+#define GPIO_PDDR_CS_5                  (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_PWM */
+#define GPIO_PDDR_PWM_2                (0x04)
+#define GPIO_PDDR_PWM_3                (0x08)
+#define GPIO_PDDR_PWM_4                (0x10)
+#define GPIO_PDDR_PWM_5                (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_FECI2C */
+#define GPIO_PDDR_FECI2C_0          (0x01)
+#define GPIO_PDDR_FECI2C_1          (0x02)
+#define GPIO_PDDR_FECI2C_2          (0x04)
+#define GPIO_PDDR_FECI2C_3          (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_UART */
+#define GPIO_PDDR_UART_0              (0x01)
+#define GPIO_PDDR_UART_1              (0x02)
+#define GPIO_PDDR_UART_2              (0x04)
+#define GPIO_PDDR_UART_3              (0x08)
+#define GPIO_PDDR_UART_4              (0x10)
+#define GPIO_PDDR_UART_5              (0x20)
+#define GPIO_PDDR_UART_6              (0x40)
+#define GPIO_PDDR_UART_7              (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_QSPI */
+#define GPIO_PDDR_QSPI_0              (0x01)
+#define GPIO_PDDR_QSPI_1              (0x02)
+#define GPIO_PDDR_QSPI_2              (0x04)
+#define GPIO_PDDR_QSPI_3              (0x08)
+#define GPIO_PDDR_QSPI_4              (0x10)
+#define GPIO_PDDR_QSPI_5              (0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_TIMER */
+#define GPIO_PDDR_TIMER_0            (0x01)
+#define GPIO_PDDR_TIMER_1            (0x02)
+#define GPIO_PDDR_TIMER_2            (0x04)
+#define GPIO_PDDR_TIMER_3            (0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
+#define GPIO_PDDR_LCDDATAH_0      (0x01)
+#define GPIO_PDDR_LCDDATAH_1      (0x02)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
+#define GPIO_PDDR_LCDDATAM_0      (0x01)
+#define GPIO_PDDR_LCDDATAM_1      (0x02)
+#define GPIO_PDDR_LCDDATAM_2      (0x04)
+#define GPIO_PDDR_LCDDATAM_3      (0x08)
+#define GPIO_PDDR_LCDDATAM_4      (0x10)
+#define GPIO_PDDR_LCDDATAM_5      (0x20)
+#define GPIO_PDDR_LCDDATAM_6      (0x40)
+#define GPIO_PDDR_LCDDATAM_7      (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
+#define GPIO_PDDR_LCDDATAL_0      (0x01)
+#define GPIO_PDDR_LCDDATAL_1      (0x02)
+#define GPIO_PDDR_LCDDATAL_2      (0x04)
+#define GPIO_PDDR_LCDDATAL_3      (0x08)
+#define GPIO_PDDR_LCDDATAL_4      (0x10)
+#define GPIO_PDDR_LCDDATAL_5      (0x20)
+#define GPIO_PDDR_LCDDATAL_6      (0x40)
+#define GPIO_PDDR_LCDDATAL_7      (0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
+#define GPIO_PDDR_LCDCTLH_0        (0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
+#define GPIO_PDDR_LCDCTLL_0        (0x01)
+#define GPIO_PDDR_LCDCTLL_1        (0x02)
+#define GPIO_PDDR_LCDCTLL_2        (0x04)
+#define GPIO_PDDR_LCDCTLL_3        (0x08)
+#define GPIO_PDDR_LCDCTLL_4        (0x10)
+#define GPIO_PDDR_LCDCTLL_5        (0x20)
+#define GPIO_PDDR_LCDCTLL_6        (0x40)
+#define GPIO_PDDR_LCDCTLL_7        (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECH */
+#define GPIO_PPDSDR_FECH_L0          (0x01)
+#define GPIO_PPDSDR_FECH_L1          (0x02)
+#define GPIO_PPDSDR_FECH_L2          (0x04)
+#define GPIO_PPDSDR_FECH_L3          (0x08)
+#define GPIO_PPDSDR_FECH_L4          (0x10)
+#define GPIO_PPDSDR_FECH_L5          (0x20)
+#define GPIO_PPDSDR_FECH_L6          (0x40)
+#define GPIO_PPDSDR_FECH_L7          (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_SSI */
+#define GPIO_PPDSDR_SSI_0            (0x01)
+#define GPIO_PPDSDR_SSI_1            (0x02)
+#define GPIO_PPDSDR_SSI_2            (0x04)
+#define GPIO_PPDSDR_SSI_3            (0x08)
+#define GPIO_PPDSDR_SSI_4            (0x10)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
+#define GPIO_PPDSDR_BUSCTL_0      (0x01)
+#define GPIO_PPDSDR_BUSCTL_1      (0x02)
+#define GPIO_PPDSDR_BUSCTL_2      (0x04)
+#define GPIO_PPDSDR_BUSCTL_3      (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BE */
+#define GPIO_PPDSDR_BE_0              (0x01)
+#define GPIO_PPDSDR_BE_1              (0x02)
+#define GPIO_PPDSDR_BE_2              (0x04)
+#define GPIO_PPDSDR_BE_3              (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_CS */
+#define GPIO_PPDSDR_CS_1              (0x02)
+#define GPIO_PPDSDR_CS_2              (0x04)
+#define GPIO_PPDSDR_CS_3              (0x08)
+#define GPIO_PPDSDR_CS_4              (0x10)
+#define GPIO_PPDSDR_CS_5              (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_PWM */
+#define GPIO_PPDSDR_PWM_2            (0x04)
+#define GPIO_PPDSDR_PWM_3            (0x08)
+#define GPIO_PPDSDR_PWM_4            (0x10)
+#define GPIO_PPDSDR_PWM_5            (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
+#define GPIO_PPDSDR_FECI2C_0      (0x01)
+#define GPIO_PPDSDR_FECI2C_1      (0x02)
+#define GPIO_PPDSDR_FECI2C_2      (0x04)
+#define GPIO_PPDSDR_FECI2C_3      (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_UART */
+#define GPIO_PPDSDR_UART_0          (0x01)
+#define GPIO_PPDSDR_UART_1          (0x02)
+#define GPIO_PPDSDR_UART_2          (0x04)
+#define GPIO_PPDSDR_UART_3          (0x08)
+#define GPIO_PPDSDR_UART_4          (0x10)
+#define GPIO_PPDSDR_UART_5          (0x20)
+#define GPIO_PPDSDR_UART_6          (0x40)
+#define GPIO_PPDSDR_UART_7          (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_QSPI */
+#define GPIO_PPDSDR_QSPI_0          (0x01)
+#define GPIO_PPDSDR_QSPI_1          (0x02)
+#define GPIO_PPDSDR_QSPI_2          (0x04)
+#define GPIO_PPDSDR_QSPI_3          (0x08)
+#define GPIO_PPDSDR_QSPI_4          (0x10)
+#define GPIO_PPDSDR_QSPI_5          (0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_TIMER */
+#define GPIO_PPDSDR_TIMER_0        (0x01)
+#define GPIO_PPDSDR_TIMER_1        (0x02)
+#define GPIO_PPDSDR_TIMER_2        (0x04)
+#define GPIO_PPDSDR_TIMER_3        (0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
+#define GPIO_PPDSDR_LCDDATAH_0  (0x01)
+#define GPIO_PPDSDR_LCDDATAH_1  (0x02)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
+#define GPIO_PPDSDR_LCDDATAM_0  (0x01)
+#define GPIO_PPDSDR_LCDDATAM_1  (0x02)
+#define GPIO_PPDSDR_LCDDATAM_2  (0x04)
+#define GPIO_PPDSDR_LCDDATAM_3  (0x08)
+#define GPIO_PPDSDR_LCDDATAM_4  (0x10)
+#define GPIO_PPDSDR_LCDDATAM_5  (0x20)
+#define GPIO_PPDSDR_LCDDATAM_6  (0x40)
+#define GPIO_PPDSDR_LCDDATAM_7  (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
+#define GPIO_PPDSDR_LCDDATAL_0  (0x01)
+#define GPIO_PPDSDR_LCDDATAL_1  (0x02)
+#define GPIO_PPDSDR_LCDDATAL_2  (0x04)
+#define GPIO_PPDSDR_LCDDATAL_3  (0x08)
+#define GPIO_PPDSDR_LCDDATAL_4  (0x10)
+#define GPIO_PPDSDR_LCDDATAL_5  (0x20)
+#define GPIO_PPDSDR_LCDDATAL_6  (0x40)
+#define GPIO_PPDSDR_LCDDATAL_7  (0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
+#define GPIO_PPDSDR_LCDCTLH_0    (0x01)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
+#define GPIO_PPDSDR_LCDCTLL_0    (0x01)
+#define GPIO_PPDSDR_LCDCTLL_1    (0x02)
+#define GPIO_PPDSDR_LCDCTLL_2    (0x04)
+#define GPIO_PPDSDR_LCDCTLL_3    (0x08)
+#define GPIO_PPDSDR_LCDCTLL_4    (0x10)
+#define GPIO_PPDSDR_LCDCTLL_5    (0x20)
+#define GPIO_PPDSDR_LCDCTLL_6    (0x40)
+#define GPIO_PPDSDR_LCDCTLL_7    (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECH */
+#define GPIO_PCLRR_FECH_L0            (0x01)
+#define GPIO_PCLRR_FECH_L1            (0x02)
+#define GPIO_PCLRR_FECH_L2            (0x04)
+#define GPIO_PCLRR_FECH_L3            (0x08)
+#define GPIO_PCLRR_FECH_L4            (0x10)
+#define GPIO_PCLRR_FECH_L5            (0x20)
+#define GPIO_PCLRR_FECH_L6            (0x40)
+#define GPIO_PCLRR_FECH_L7            (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_SSI */
+#define GPIO_PCLRR_SSI_0              (0x01)
+#define GPIO_PCLRR_SSI_1              (0x02)
+#define GPIO_PCLRR_SSI_2              (0x04)
+#define GPIO_PCLRR_SSI_3              (0x08)
+#define GPIO_PCLRR_SSI_4              (0x10)
+
+/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
+#define GPIO_PCLRR_BUSCTL_L0        (0x01)
+#define GPIO_PCLRR_BUSCTL_L1        (0x02)
+#define GPIO_PCLRR_BUSCTL_L2        (0x04)
+#define GPIO_PCLRR_BUSCTL_L3        (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_BE */
+#define GPIO_PCLRR_BE_0                (0x01)
+#define GPIO_PCLRR_BE_1                (0x02)
+#define GPIO_PCLRR_BE_2                (0x04)
+#define GPIO_PCLRR_BE_3                (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_CS */
+#define GPIO_PCLRR_CS_1                (0x02)
+#define GPIO_PCLRR_CS_2                (0x04)
+#define GPIO_PCLRR_CS_3                (0x08)
+#define GPIO_PCLRR_CS_4                (0x10)
+#define GPIO_PCLRR_CS_5                (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_PWM */
+#define GPIO_PCLRR_PWM_2              (0x04)
+#define GPIO_PCLRR_PWM_3              (0x08)
+#define GPIO_PCLRR_PWM_4              (0x10)
+#define GPIO_PCLRR_PWM_5              (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECI2C */
+#define GPIO_PCLRR_FECI2C_0        (0x01)
+#define GPIO_PCLRR_FECI2C_1        (0x02)
+#define GPIO_PCLRR_FECI2C_2        (0x04)
+#define GPIO_PCLRR_FECI2C_3        (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_UART */
+#define GPIO_PCLRR_UART0            (0x01)
+#define GPIO_PCLRR_UART1            (0x02)
+#define GPIO_PCLRR_UART2            (0x04)
+#define GPIO_PCLRR_UART3            (0x08)
+#define GPIO_PCLRR_UART4            (0x10)
+#define GPIO_PCLRR_UART5            (0x20)
+#define GPIO_PCLRR_UART6            (0x40)
+#define GPIO_PCLRR_UART7            (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_QSPI */
+#define GPIO_PCLRR_QSPI0            (0x01)
+#define GPIO_PCLRR_QSPI1            (0x02)
+#define GPIO_PCLRR_QSPI2            (0x04)
+#define GPIO_PCLRR_QSPI3            (0x08)
+#define GPIO_PCLRR_QSPI4            (0x10)
+#define GPIO_PCLRR_QSPI5            (0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_TIMER */
+#define GPIO_PCLRR_TIMER0          (0x01)
+#define GPIO_PCLRR_TIMER1          (0x02)
+#define GPIO_PCLRR_TIMER2          (0x04)
+#define GPIO_PCLRR_TIMER3          (0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
+#define GPIO_PCLRR_LCDDATAH0    (0x01)
+#define GPIO_PCLRR_LCDDATAH1    (0x02)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
+#define GPIO_PCLRR_LCDDATAM0    (0x01)
+#define GPIO_PCLRR_LCDDATAM1    (0x02)
+#define GPIO_PCLRR_LCDDATAM2    (0x04)
+#define GPIO_PCLRR_LCDDATAM3    (0x08)
+#define GPIO_PCLRR_LCDDATAM4    (0x10)
+#define GPIO_PCLRR_LCDDATAM5    (0x20)
+#define GPIO_PCLRR_LCDDATAM6    (0x40)
+#define GPIO_PCLRR_LCDDATAM7    (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
+#define GPIO_PCLRR_LCDDATAL0    (0x01)
+#define GPIO_PCLRR_LCDDATAL1    (0x02)
+#define GPIO_PCLRR_LCDDATAL2    (0x04)
+#define GPIO_PCLRR_LCDDATAL3    (0x08)
+#define GPIO_PCLRR_LCDDATAL4    (0x10)
+#define GPIO_PCLRR_LCDDATAL5    (0x20)
+#define GPIO_PCLRR_LCDDATAL6    (0x40)
+#define GPIO_PCLRR_LCDDATAL7    (0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
+#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0      (0x01)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
+#define GPIO_PCLRR_LCDCTLL0      (0x01)
+#define GPIO_PCLRR_LCDCTLL1      (0x02)
+#define GPIO_PCLRR_LCDCTLL2      (0x04)
+#define GPIO_PCLRR_LCDCTLL3      (0x08)
+#define GPIO_PCLRR_LCDCTLL4      (0x10)
+#define GPIO_PCLRR_LCDCTLL5      (0x20)
+#define GPIO_PCLRR_LCDCTLL6      (0x40)
+#define GPIO_PCLRR_LCDCTLL7      (0x80)
+
+/* Bit definitions and macros for GPIO_PAR_FEC */
+#define GPIO_PAR_FEC_MII(x)            (((x)&0x03)<<0)
+#define GPIO_PAR_FEC_7W(x)             (((x)&0x03)<<2)
+#define GPIO_PAR_FEC_7W_GPIO           (0x00)
+#define GPIO_PAR_FEC_7W_URTS1          (0x04)
+#define GPIO_PAR_FEC_7W_FEC            (0x0C)
+#define GPIO_PAR_FEC_MII_GPIO          (0x00)
+#define GPIO_PAR_FEC_MII_UART          (0x01)
+#define GPIO_PAR_FEC_MII_FEC           (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_PWM */
+#define GPIO_PAR_PWM1(x)               (((x)&0x03)<<0)
+#define GPIO_PAR_PWM3(x)               (((x)&0x03)<<2)
+#define GPIO_PAR_PWM5                  (0x10)
+#define GPIO_PAR_PWM7                  (0x20)
+
+/* Bit definitions and macros for GPIO_PAR_BUSCTL */
+#define GPIO_PAR_BUSCTL_TS(x)              (((x)&0x03)<<3)
+#define GPIO_PAR_BUSCTL_RWB                (0x20)
+#define GPIO_PAR_BUSCTL_TA                 (0x40)
+#define GPIO_PAR_BUSCTL_OE                 (0x80)
+#define GPIO_PAR_BUSCTL_OE_GPIO            (0x00)
+#define GPIO_PAR_BUSCTL_OE_OE              (0x80)
+#define GPIO_PAR_BUSCTL_TA_GPIO            (0x00)
+#define GPIO_PAR_BUSCTL_TA_TA              (0x40)
+#define GPIO_PAR_BUSCTL_RWB_GPIO           (0x00)
+#define GPIO_PAR_BUSCTL_RWB_RWB            (0x20)
+#define GPIO_PAR_BUSCTL_TS_GPIO            (0x00)
+#define GPIO_PAR_BUSCTL_TS_DACK0           (0x10)
+#define GPIO_PAR_BUSCTL_TS_TS              (0x18)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x)             (((x)&0x03)<<0)
+#define GPIO_PAR_FECI2C_SCL(x)             (((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_MDIO(x)            (((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_MDC(x)             (((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_MDC_GPIO           (0x00)
+#define GPIO_PAR_FECI2C_MDC_UTXD2          (0x40)
+#define GPIO_PAR_FECI2C_MDC_SCL            (0x80)
+#define GPIO_PAR_FECI2C_MDC_EMDC           (0xC0)
+#define GPIO_PAR_FECI2C_MDIO_GPIO          (0x00)
+#define GPIO_PAR_FECI2C_MDIO_URXD2         (0x10)
+#define GPIO_PAR_FECI2C_MDIO_SDA           (0x20)
+#define GPIO_PAR_FECI2C_MDIO_EMDIO         (0x30)
+#define GPIO_PAR_FECI2C_SCL_GPIO           (0x00)
+#define GPIO_PAR_FECI2C_SCL_UTXD2          (0x04)
+#define GPIO_PAR_FECI2C_SCL_SCL            (0x0C)
+#define GPIO_PAR_FECI2C_SDA_GPIO           (0x00)
+#define GPIO_PAR_FECI2C_SDA_URXD2          (0x02)
+#define GPIO_PAR_FECI2C_SDA_SDA            (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_BE */
+#define GPIO_PAR_BE0                    (0x01)
+#define GPIO_PAR_BE1                    (0x02)
+#define GPIO_PAR_BE2                    (0x04)
+#define GPIO_PAR_BE3                    (0x08)
+
+/* Bit definitions and macros for GPIO_PAR_CS */
+#define GPIO_PAR_CS1                    (0x02)
+#define GPIO_PAR_CS2                    (0x04)
+#define GPIO_PAR_CS3                    (0x08)
+#define GPIO_PAR_CS4                    (0x10)
+#define GPIO_PAR_CS5                    (0x20)
+#define GPIO_PAR_CS1_GPIO            	(0x00)
+#define GPIO_PAR_CS1_SDCS1           	(0x01)
+#define GPIO_PAR_CS1_CS1             	(0x03)
+
+/* Bit definitions and macros for GPIO_PAR_SSI */
+#define GPIO_PAR_SSI_MCLK                  (0x0080)
+#define GPIO_PAR_SSI_TXD(x)                (((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_RXD(x)                (((x)&0x0003)<<10)
+#define GPIO_PAR_SSI_FS(x)                 (((x)&0x0003)<<12)
+#define GPIO_PAR_SSI_BCLK(x)               (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_UART */
+#define GPIO_PAR_UART_TXD0                (0x0001)
+#define GPIO_PAR_UART_RXD0                (0x0002)
+#define GPIO_PAR_UART_RTS0                (0x0004)
+#define GPIO_PAR_UART_CTS0                (0x0008)
+#define GPIO_PAR_UART_TXD1(x)             (((x)&0x0003)<<4)
+#define GPIO_PAR_UART_RXD1(x)             (((x)&0x0003)<<6)
+#define GPIO_PAR_UART_RTS1(x)             (((x)&0x0003)<<8)
+#define GPIO_PAR_UART_CTS1(x)             (((x)&0x0003)<<10)
+#define GPIO_PAR_UART_CTS1_GPIO           (0x0000)
+#define GPIO_PAR_UART_CTS1_SSI_BCLK       (0x0800)
+#define GPIO_PAR_UART_CTS1_ULPI_D7        (0x0400)
+#define GPIO_PAR_UART_CTS1_UCTS1          (0x0C00)
+#define GPIO_PAR_UART_RTS1_GPIO           (0x0000)
+#define GPIO_PAR_UART_RTS1_SSI_FS         (0x0200)
+#define GPIO_PAR_UART_RTS1_ULPI_D6        (0x0100)
+#define GPIO_PAR_UART_RTS1_URTS1          (0x0300)
+#define GPIO_PAR_UART_RXD1_GPIO           (0x0000)
+#define GPIO_PAR_UART_RXD1_SSI_RXD        (0x0080)
+#define GPIO_PAR_UART_RXD1_ULPI_D5        (0x0040)
+#define GPIO_PAR_UART_RXD1_URXD1          (0x00C0)
+#define GPIO_PAR_UART_TXD1_GPIO           (0x0000)
+#define GPIO_PAR_UART_TXD1_SSI_TXD        (0x0020)
+#define GPIO_PAR_UART_TXD1_ULPI_D4        (0x0010)
+#define GPIO_PAR_UART_TXD1_UTXD1          (0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_QSPI */
+#define GPIO_PAR_QSPI_SCK(x)               (((x)&0x0003)<<4)
+#define GPIO_PAR_QSPI_DOUT(x)              (((x)&0x0003)<<6)
+#define GPIO_PAR_QSPI_DIN(x)               (((x)&0x0003)<<8)
+#define GPIO_PAR_QSPI_PCS0(x)              (((x)&0x0003)<<10)
+#define GPIO_PAR_QSPI_PCS1(x)              (((x)&0x0003)<<12)
+#define GPIO_PAR_QSPI_PCS2(x)              (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIN0(x)             (((x)&0x03)<<0)
+#define GPIO_PAR_TIN1(x)             (((x)&0x03)<<2)
+#define GPIO_PAR_TIN2(x)             (((x)&0x03)<<4)
+#define GPIO_PAR_TIN3(x)             (((x)&0x03)<<6)
+#define GPIO_PAR_TIN3_GPIO           (0x00)
+#define GPIO_PAR_TIN3_TOUT3          (0x80)
+#define GPIO_PAR_TIN3_URXD2          (0x40)
+#define GPIO_PAR_TIN3_TIN3           (0xC0)
+#define GPIO_PAR_TIN2_GPIO           (0x00)
+#define GPIO_PAR_TIN2_TOUT2          (0x20)
+#define GPIO_PAR_TIN2_UTXD2          (0x10)
+#define GPIO_PAR_TIN2_TIN2           (0x30)
+#define GPIO_PAR_TIN1_GPIO           (0x00)
+#define GPIO_PAR_TIN1_TOUT1          (0x08)
+#define GPIO_PAR_TIN1_DACK1          (0x04)
+#define GPIO_PAR_TIN1_TIN1           (0x0C)
+#define GPIO_PAR_TIN0_GPIO           (0x00)
+#define GPIO_PAR_TIN0_TOUT0          (0x02)
+#define GPIO_PAR_TIN0_DREQ0          (0x01)
+#define GPIO_PAR_TIN0_TIN0           (0x03)
+
+/* Bit definitions and macros for GPIO_PAR_LCDDATA */
+#define GPIO_PAR_LCDDATA_LD7_0(x)          ((x)&0x03)
+#define GPIO_PAR_LCDDATA_LD15_8(x)         (((x)&0x03)<<2)
+#define GPIO_PAR_LCDDATA_LD16(x)           (((x)&0x03)<<4)
+#define GPIO_PAR_LCDDATA_LD17(x)           (((x)&0x03)<<6)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_CLS                (0x0001)
+#define GPIO_PAR_LCDCTL_PS                 (0x0002)
+#define GPIO_PAR_LCDCTL_REV                (0x0004)
+#define GPIO_PAR_LCDCTL_SPL_SPR            (0x0008)
+#define GPIO_PAR_LCDCTL_CONTRAST           (0x0010)
+#define GPIO_PAR_LCDCTL_LSCLK              (0x0020)
+#define GPIO_PAR_LCDCTL_LP_HSYNC           (0x0040)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC          (0x0080)
+#define GPIO_PAR_LCDCTL_ACD_OE             (0x0100)
+
+/* Bit definitions and macros for GPIO_PAR_IRQ */
+#define GPIO_PAR_IRQ1(x)               (((x)&0x0003)<<4)
+#define GPIO_PAR_IRQ2(x)               (((x)&0x0003)<<6)
+#define GPIO_PAR_IRQ4(x)               (((x)&0x0003)<<8)
+#define GPIO_PAR_IRQ5(x)               (((x)&0x0003)<<10)
+#define GPIO_PAR_IRQ6(x)               (((x)&0x0003)<<12)
+
+/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
+#define GPIO_MSCR_FLEXBUS_ADDRCTL(x)      ((x)&0x03)
+#define GPIO_MSCR_FLEXBUS_DLOWER(x)       (((x)&0x03)<<2)
+#define GPIO_MSCR_FLEXBUS_DUPPER(x)       (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDRAM(x)          ((x)&0x03)
+#define GPIO_MSCR_SDRAM_SDCLK(x)          (((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDCLKB(x)         (((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_DSCR_I2C */
+#define GPIO_DSCR_I2C_DSE(x)               ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_PWM */
+#define GPIO_DSCR_PWM_DSE(x)               ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_FEC */
+#define GPIO_DSCR_FEC_DSE(x)               ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_UART */
+#define GPIO_DSCR_UART0_DSE(x)            ((x)&0x03)
+#define GPIO_DSCR_UART1_DSE(x)            (((x)&0x03)<<2)
+
+/* Bit definitions and macros for GPIO_DSCR_QSPI */
+#define GPIO_DSCR_QSPI_DSE(x)             ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_TIMER */
+#define GPIO_DSCR_TIMER_DSE(x)            ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_SSI */
+#define GPIO_DSCR_SSI_DSE(x)               ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_LCD */
+#define GPIO_DSCR_LCD_DSE(x)               ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DSE(x)           ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_CLKRST */
+#define GPIO_DSCR_CLKRST_DSE(x)         ((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_IRQ */
+#define GPIO_DSCR_IRQ_DSE(x)               ((x)&0x03)
+
+/* not done yet */
+/*********************************************************************
+* LCD Controller (LCDC)
+*********************************************************************/
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_LSSAR_SSA(x)           (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_LSR_YMAX(x)            (((x)&0x000003FF)<<0)
+#define LCDC_LSR_XMAX(x)            (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_LVPWR_VPW(x)           (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_LCPR_CYP(x)            (((x)&0x000003FF)<<0)
+#define LCDC_LCPR_CXP(x)            (((x)&0x000003FF)<<16)
+#define LCDC_LCPR_OP                (0x10000000)
+#define LCDC_LCPR_CC(x)             (((x)&0x00000003)<<30)
+#define LCDC_LCPR_CC_TRANSPARENT    (0x00000000)
+#define LCDC_LCPR_CC_OR             (0x40000000)
+#define LCDC_LCPR_CC_XOR            (0x80000000)
+#define LCDC_LCPR_CC_AND            (0xC0000000)
+#define LCDC_LCPR_OP_ON             (0x10000000)
+#define LCDC_LCPR_OP_OFF            (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_LCWHBR_BD(x)           (((x)&0x000000FF)<<0)
+#define LCDC_LCWHBR_CH(x)           (((x)&0x0000001F)<<16)
+#define LCDC_LCWHBR_CW(x)           (((x)&0x0000001F)<<24)
+#define LCDC_LCWHBR_BK_EN           (0x80000000)
+#define LCDC_LCWHBR_BK_EN_ON        (0x80000000)
+#define LCDC_LCWHBR_BK_EN_OFF       (0x00000000)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_LCCMR_CUR_COL_B(x)     (((x)&0x0000003F)<<0)
+#define LCDC_LCCMR_CUR_COL_G(x)     (((x)&0x0000003F)<<6)
+#define LCDC_LCCMR_CUR_COL_R(x)     (((x)&0x0000003F)<<12)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_LPCR_PCD(x)            (((x)&0x0000003F)<<0)
+#define LCDC_LPCR_SHARP             (0x00000040)
+#define LCDC_LPCR_SCLKSEL           (0x00000080)
+#define LCDC_LPCR_ACD(x)            (((x)&0x0000007F)<<8)
+#define LCDC_LPCR_ACDSEL            (0x00008000)
+#define LCDC_LPCR_REV_VS            (0x00010000)
+#define LCDC_LPCR_SWAP_SEL          (0x00020000)
+#define LCDC_LPCR_ENDSEL            (0x00040000)
+#define LCDC_LPCR_SCLKIDLE          (0x00080000)
+#define LCDC_LPCR_OEPOL             (0x00100000)
+#define LCDC_LPCR_CLKPOL            (0x00200000)
+#define LCDC_LPCR_LPPOL             (0x00400000)
+#define LCDC_LPCR_FLM               (0x00800000)
+#define LCDC_LPCR_PIXPOL            (0x01000000)
+#define LCDC_LPCR_BPIX(x)           (((x)&0x00000007)<<25)
+#define LCDC_LPCR_PBSIZ(x)          (((x)&0x00000003)<<28)
+#define LCDC_LPCR_COLOR             (0x40000000)
+#define LCDC_LPCR_TFT               (0x80000000)
+#define LCDC_LPCR_MODE_MONOCHROME   (0x00000000)
+#define LCDC_LPCR_MODE_CSTN         (0x40000000)
+#define LCDC_LPCR_MODE_TFT          (0xC0000000)
+#define LCDC_LPCR_PBSIZ_1           (0x00000000)
+#define LCDC_LPCR_PBSIZ_2           (0x10000000)
+#define LCDC_LPCR_PBSIZ_4           (0x20000000)
+#define LCDC_LPCR_PBSIZ_8           (0x30000000)
+#define LCDC_LPCR_BPIX_1bpp         (0x00000000)
+#define LCDC_LPCR_BPIX_2bpp         (0x02000000)
+#define LCDC_LPCR_BPIX_4bpp         (0x04000000)
+#define LCDC_LPCR_BPIX_8bpp         (0x06000000)
+#define LCDC_LPCR_BPIX_12bpp        (0x08000000)
+#define LCDC_LPCR_BPIX_16bpp        (0x0A000000)
+#define LCDC_LPCR_BPIX_18bpp        (0x0C000000)
+
+#define LCDC_LPCR_PANEL_TYPE(x)     (((x)&0x00000003)<<30)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_LHCR_H_WAIT_2(x)       (((x)&0x000000FF)<<0)
+#define LCDC_LHCR_H_WAIT_1(x)       (((x)&0x000000FF)<<8)
+#define LCDC_LHCR_H_WIDTH(x)        (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_LVCR_V_WAIT_2(x)       (((x)&0x000000FF)<<0)
+#define LCDC_LVCR_V_WAIT_1(x)       (((x)&0x000000FF)<<8)
+#define LCDC_LVCR_V_WIDTH(x)      (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for LCDC_LPOR */
+#define LCDC_LPOR_POS(x)            (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_LPCCR_PW(x)            (((x)&0x000000FF)<<0)
+#define LCDC_LPCCR_CC_EN            (0x00000100)
+#define LCDC_LPCCR_SCR(x)           (((x)&0x00000003)<<9)
+#define LCDC_LPCCR_LDMSK            (0x00008000)
+#define LCDC_LPCCR_CLS_HI_WIDTH(x)  (((x)&0x000001FF)<<16)
+#define LCDC_LPCCR_SCR_LINEPULSE    (0x00000000)
+#define LCDC_LPCCR_SCR_PIXELCLK     (0x00002000)
+#define LCDC_LPCCR_SCR_LCDCLOCK     (0x00004000)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_LDCR_TM(x)             (((x)&0x0000001F)<<0)
+#define LCDC_LDCR_HM(x)             (((x)&0x0000001F)<<16)
+#define LCDC_LDCR_BURST             (0x80000000)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_LRMCR_SEL_REF          (0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_LICR_INTCON            (0x00000001)
+#define LCDC_LICR_INTSYN            (0x00000004)
+#define LCDC_LICR_GW_INT_CON        (0x00000010)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_LIER_BOF_EN            (0x00000001)
+#define LCDC_LIER_EOF_EN            (0x00000002)
+#define LCDC_LIER_ERR_RES_EN        (0x00000004)
+#define LCDC_LIER_UDR_ERR_EN        (0x00000008)
+#define LCDC_LIER_GW_BOF_EN         (0x00000010)
+#define LCDC_LIER_GW_EOF_EN         (0x00000020)
+#define LCDC_LIER_GW_ERR_RES_EN     (0x00000040)
+#define LCDC_LIER_GW_UDR_ERR_EN     (0x00000080)
+
+/* Bit definitions and macros for LCDC_LISR */
+#define LCDC_LISR_BOF               (0x00000001)
+#define LCDC_LISR_EOF               (0x00000002)
+#define LCDC_LISR_ERR_RES           (0x00000004)
+#define LCDC_LISR_UDR_ERR           (0x00000008)
+#define LCDC_LISR_GW_BOF            (0x00000010)
+#define LCDC_LISR_GW_EOF            (0x00000020)
+#define LCDC_LISR_GW_ERR_RES        (0x00000040)
+#define LCDC_LISR_GW_UDR_ERR        (0x00000080)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_LGWSAR_GWSA(x)         (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_LGWSR_GWH(x)           (((x)&0x000003FF)<<0)
+#define LCDC_LGWSR_GWW(x)           (((x)&0x0000003F)<<20)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_LGWVPWR_GWVPW(x)       (((x)&0x000003FF)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_LGWPOR_GWPO(x)         (((x)&0x0000001F)<<0)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_LGWPR_GWYP(x)          (((x)&0x000003FF)<<0)
+#define LCDC_LGWPR_GWXP(x)          (((x)&0x000003FF)<<16)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_LGWCR_GWCKB(x)         (((x)&0x0000003F)<<0)
+#define LCDC_LGWCR_GWCKG(x)         (((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKR(x)         (((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GW_RVS           (0x00200000)
+#define LCDC_LGWCR_GWE              (0x00400000)
+#define LCDC_LGWCR_GWCKE            (0x00800000)
+#define LCDC_LGWCR_GWAV(x)          (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWTM(x)         (((x)&0x0000001F)<<0)
+#define LCDC_LGWDCR_GWHM(x)         (((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWBT            (0x80000000)
+
+/* Bit definitions and macros for LCDC_BPLUT_BASE */
+#define LCDC_BPLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for LCDC_GWLUT_BASE */
+#define LCDC_GWLUT_BASE_BASE(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* not done yet */
+/*********************************************************************
+* USB Controller (USB)
+*********************************************************************/
+/* Bit definitions and macros for USB_HCSPARAMS */
+#define USB_HCSPARAMS_N_PORTS(x)             ((x)&0x0000000F)
+#define USB_HCSPARAMS_PPC                    (0x00000010)
+#define USB_HCSPARAMS_N_PCC(x)               (((x)&0x0000000F)<<8)
+#define USB_HCSPARAMS_N_CC(x)                (((x)&0x0000000F)<<12)
+#define USB_HCSPARAMS_PI                     (0x00010000)
+#define USB_HCSPARAMS_N_PTT(x)               (((x)&0x0000000F)<<20)
+#define USB_HCSPARAMS_N_TT(x)                (((x)&0x0000000F)<<24)
+
+/* Bit definitions and macros for USB_HCCPARAMS */
+#define USB_HCCPARAMS_ADC                    (0x00000001)
+#define USB_HCCPARAMS_PFL                    (0x00000002)
+#define USB_HCCPARAMS_ASP                    (0x00000004)
+#define USB_HCCPARAMS_IST(x)                 (((x)&0x0000000F)<<4)
+#define USB_HCCPARAMS_EECP(x)                (((x)&0x000000FF)<<8)
+
+/* Bit definitions and macros for USB_DCIVERSION */
+#define USB_DCIVERSION_DCIVERSION(x)         (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for USB_DCCPARAMS */
+#define USB_DCCPARAMS_DEN(x)                 (((x)&0x0000001F)<<0)
+#define USB_DCCPARAMS_DC                     (0x00000080)
+#define USB_DCCPARAMS_HC                     (0x00000100)
+
+/* Bit definitions and macros for USB_USBCMD */
+#define USB_USBCMD_RS                        (0x00000001)
+#define USB_USBCMD_RST                       (0x00000002)
+#define USB_USBCMD_FS0                       (0x00000004)
+#define USB_USBCMD_FS1                       (0x00000008)
+#define USB_USBCMD_PSE                       (0x00000010)
+#define USB_USBCMD_ASE                       (0x00000020)
+#define USB_USBCMD_IAA                       (0x00000040)
+#define USB_USBCMD_LR                        (0x00000080)
+#define USB_USBCMD_ASP(x)                    (((x)&0x00000003)<<8)
+#define USB_USBCMD_ASPE                      (0x00000800)
+#define USB_USBCMD_SUTW                      (0x00002000)
+#define USB_USBCMD_ATDTW                     (0x00004000)
+#define USB_USBCMD_FS2                       (0x00008000)
+#define USB_USBCMD_ITC(x)                    (((x)&0x000000FF)<<16)
+#define USB_USBCMD_ITC_IMM                   (0x00000000)
+#define USB_USBCMD_ITC_1                     (0x00010000)
+#define USB_USBCMD_ITC_2                     (0x00020000)
+#define USB_USBCMD_ITC_4                     (0x00040000)
+#define USB_USBCMD_ITC_8                     (0x00080000)
+#define USB_USBCMD_ITC_16                    (0x00100000)
+#define USB_USBCMD_ITC_32                    (0x00200000)
+#define USB_USBCMD_ITC_40                    (0x00400000)
+#define USB_USBCMD_FS_1024                   (0x00000000)
+#define USB_USBCMD_FS_512                    (0x00000004)
+#define USB_USBCMD_FS_256                    (0x00000008)
+#define USB_USBCMD_FS_128                    (0x0000000C)
+#define USB_USBCMD_FS_64                     (0x00008000)
+#define USB_USBCMD_FS_32                     (0x00008004)
+#define USB_USBCMD_FS_16                     (0x00008008)
+#define USB_USBCMD_FS_8                      (0x0000800C)
+
+/* Bit definitions and macros for USB_USBSTS */
+#define USB_USBSTS_UI                        (0x00000001)
+#define USB_USBSTS_UEI                       (0x00000002)
+#define USB_USBSTS_PCI                       (0x00000004)
+#define USB_USBSTS_FRI                       (0x00000008)
+#define USB_USBSTS_SEI                       (0x00000010)
+#define USB_USBSTS_AAI                       (0x00000020)
+#define USB_USBSTS_URI                       (0x00000040)
+#define USB_USBSTS_SRI                       (0x00000080)
+#define USB_USBSTS_SLI                       (0x00000100)
+#define USB_USBSTS_HCH                       (0x00001000)
+#define USB_USBSTS_RCL                       (0x00002000)
+#define USB_USBSTS_PS                        (0x00004000)
+#define USB_USBSTS_AS                        (0x00008000)
+
+/* Bit definitions and macros for USB_USBINTR */
+#define USB_USBINTR_UE                       (0x00000001)
+#define USB_USBINTR_UEE                      (0x00000002)
+#define USB_USBINTR_PCE                      (0x00000004)
+#define USB_USBINTR_FRE                      (0x00000008)
+#define USB_USBINTR_SEE                      (0x00000010)
+#define USB_USBINTR_AAE                      (0x00000020)
+#define USB_USBINTR_URE                      (0x00000040)
+#define USB_USBINTR_SRE                      (0x00000080)
+#define USB_USBINTR_SLE                      (0x00000100)
+
+/* Bit definitions and macros for USB_FRINDEX */
+#define USB_FRINDEX_FRINDEX(x)               (((x)&0x00003FFF)<<0)
+
+/* Bit definitions and macros for USB_PERIODICLISTBASE */
+#define USB_PERIODICLISTBASE_PERBASE(x)      (((x)&0x000FFFFF)<<12)
+
+/* Bit definitions and macros for USB_DEVICEADDR */
+#define USB_DEVICEADDR_USBADR(x)             (((x)&0x0000007F)<<25)
+
+/* Bit definitions and macros for USB_ASYNCLISTADDR */
+#define USB_ASYNCLISTADDR_ASYBASE(x)         (((x)&0x07FFFFFF)<<5)
+
+/* Bit definitions and macros for USB_EPLISTADDR */
+#define USB_EPLISTADDR_EPBASE(x)             (((x)&0x001FFFFF)<<11)
+
+/* Bit definitions and macros for USB_ASNCTTSTS */
+#define USB_ASNCTTSTS_TTAS                   (0x00000001)
+#define USB_ASNCTTSTS_TTAC                   (0x00000002)
+
+/* Bit definitions and macros for USB_BURSTSIZE */
+#define USB_BURSTSIZE_RXPBURST(x)            (((x)&0x000000FF)<<0)
+#define USB_BURSTSIZE_TXPBURST(x)            (((x)&0x000000FF)<<8)
+
+/* Bit definitions and macros for USB_TXFILLTUNING */
+#define USB_TXFILLTUNING_TXSCHOH(x)          (((x)&0x000000FF)<<0)
+#define USB_TXFILLTUNING_TXSCHHEALTH(x)      (((x)&0x0000001F)<<8)
+#define USB_TXFILLTUNING_TXFIFOTHRES(x)      (((x)&0x0000003F)<<16)
+
+/* Bit definitions and macros for USB_TXTTFILLTUNING */
+#define USB_TXTTFILLTUNING_TXTTSCHOH(x)      (((x)&0x0000001F)<<0)
+#define USB_TXTTFILLTUNING_TXTTSCHHEALTH(x)  (((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for USB_ULPI_VIEWPORT */
+#define USB_ULPI_VIEWPORT_ULPI_DATWR(x)      (((x)&0x000000FF)<<0)
+#define USB_ULPI_VIEWPORT_ULPI_DATRD(x)      (((x)&0x000000FF)<<8)
+#define USB_ULPI_VIEWPORT_ULPI_ADDR(x)       (((x)&0x000000FF)<<16)
+#define USB_ULPI_VIEWPORT_ULPI_PORT(x)       (((x)&0x00000007)<<24)
+#define USB_ULPI_VIEWPORT_ULPI_SS            (0x08000000)
+#define USB_ULPI_VIEWPORT_ULPI_RW            (0x20000000)
+#define USB_ULPI_VIEWPORT_ULPI_RUN           (0x40000000)
+#define USB_ULPI_VIEWPORT_ULPI_WU            (0x80000000)
+
+/* Bit definitions and macros for USB_CONFIGFLAG */
+#define USB_CONFIGFLAG_CONFIGFLAG(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for USB_PORTSC */
+#define USB_PORTSC_CCS                       (0x00000001)
+#define USB_PORTSC_CSC                       (0x00000002)
+#define USB_PORTSC_PE                        (0x00000004)
+#define USB_PORTSC_PEC                       (0x00000008)
+#define USB_PORTSC_OCA                       (0x00000010)
+#define USB_PORTSC_OCC                       (0x00000020)
+#define USB_PORTSC_FPR                       (0x00000040)
+#define USB_PORTSC_SUSP                      (0x00000080)
+#define USB_PORTSC_PR                        (0x00000100)
+#define USB_PORTSC_LS(x)                     (((x)&0x00000003)<<10)
+#define USB_PORTSC_PP                        (0x00001000)
+#define USB_PORTSC_PO                        (0x00002000)
+#define USB_PORTSC_PIC(x)                    (((x)&0x00000003)<<14)
+#define USB_PORTSC_PTC(x)                    (((x)&0x0000000F)<<16)
+#define USB_PORTSC_WLCN                      (0x00100000)
+#define USB_PORTSC_WKDS                      (0x00200000)
+#define USB_PORTSC_WKOC                      (0x00400000)
+#define USB_PORTSC_PHCD                      (0x00800000)
+#define USB_PORTSC_PFSC                      (0x01000000)
+#define USB_PORTSC_PSPD(x)                   (((x)&0x00000003)<<26)
+#define USB_PORTSC_PTS(x)                    (((x)&0x00000003)<<30)
+#define USB_PORTSC_PTS_ULPI                  (0x80000000)
+#define USB_PORTSC_PTS_FS_LS                 (0xC0000000)
+#define USB_PORTSC_PSPD_FULL                 (0x00000000)
+#define USB_PORTSC_PSPD_LOW                  (0x04000000)
+#define USB_PORTSC_PSPD_HIGH                 (0x08000000)
+#define USB_PORTSC_PTC_DISBALE               (0x00000000)
+#define USB_PORTSC_PTC_JSTATE                (0x00010000)
+#define USB_PORTSC_PTC_KSTATE                (0x00020000)
+#define USB_PORTSC_PTC_SEQ_NAK               (0x00030000)
+#define USB_PORTSC_PTC_PACKET                (0x00040000)
+#define USB_PORTSC_PTC_FORCE_ENABLE          (0x00050000)
+#define USB_PORTSC_PIC_OFF                   (0x00000000)
+#define USB_PORTSC_PIC_AMBER                 (0x00004000)
+#define USB_PORTSC_PIC_GREEN                 (0x00008000)
+#define USB_PORTSC_LS_SE0                    (0x00000000)
+#define USB_PORTSC_LS_JSTATE                 (0x00000400)
+#define USB_PORTSC_LS_KSTATE                 (0x00000800)
+
+/* Bit definitions and macros for USB_OTGSC */
+#define USB_OTGSC_VD                         (0x00000001)
+#define USB_OTGSC_VC                         (0x00000002)
+#define USB_OTGSC_OT                         (0x00000008)
+#define USB_OTGSC_DP                         (0x00000010)
+#define USB_OTGSC_ID                         (0x00000100)
+#define USB_OTGSC_AVV                        (0x00000200)
+#define USB_OTGSC_ASV                        (0x00000400)
+#define USB_OTGSC_BSV                        (0x00000800)
+#define USB_OTGSC_BSE                        (0x00001000)
+#define USB_OTGSC_1MST                       (0x00002000)
+#define USB_OTGSC_DPS                        (0x00004000)
+#define USB_OTGSC_IDIS                       (0x00010000)
+#define USB_OTGSC_AVVIS                      (0x00020000)
+#define USB_OTGSC_ASVIS                      (0x00040000)
+#define USB_OTGSC_BSVIS                      (0x00080000)
+#define USB_OTGSC_BSEIS                      (0x00100000)
+#define USB_OTGSC_1MSS                       (0x00200000)
+#define USB_OTGSC_DPIS                       (0x00400000)
+#define USB_OTGSC_IDIE                       (0x01000000)
+#define USB_OTGSC_AVVIE                      (0x02000000)
+#define USB_OTGSC_ASVIE                      (0x04000000)
+#define USB_OTGSC_BSVIE                      (0x08000000)
+#define USB_OTGSC_BSEIE                      (0x10000000)
+#define USB_OTGSC_1MSE                       (0x20000000)
+#define USB_OTGSC_DPIE                       (0x40000000)
+#define USB_OTGSC_CLEAR                      (0x007F0000)
+#define USB_OTGSC_ENABLE_ALL                 (0x7F000000)
+
+/* Bit definitions and macros for USB_USBMODE */
+#define USB_USBMODE_CM(x)                    (((x)&0x00000003)<<0)
+#define USB_USBMODE_SLOM                     (0x00000008)
+#define USB_USBMODE_SDIS                     (0x00000010)
+#define USB_USBMODE_CM_IDLE                  (0x00000000)
+#define USB_USBMODE_CM_DEVICE                (0x00000002)
+#define USB_USBMODE_CM_HOST                  (0x00000003)
+#define USB_USBMODE_ES		                 (0x00000004)
+
+/* Bit definitions and macros for USB_EPSETUPSR */
+#define USB_EPSETUPSR_EPSETUPSTAT(x)         (((x)&0x0000003F)<<0)
+
+/* Bit definitions and macros for USB_EPPRIME */
+#define USB_EPPRIME_PERB(x)                  (((x)&0x0000003F)<<0)
+#define USB_EPPRIME_PETB(x)                  (((x)&0x0000003F)<<16)
+#define USB_EPPRIME_PETB0                    (0x00010000)
+#define USB_EPPRIME_PETB1                    (0x00020000)
+#define USB_EPPRIME_PETB2                    (0x00040000)
+#define USB_EPPRIME_PETB3                    (0x00080000)
+#define USB_EPPRIME_PETB4                    (0x00100000)
+#define USB_EPPRIME_PETB5                    (0x00200000)
+#define USB_EPPRIME_PERB0                    (0x00000001)
+#define USB_EPPRIME_PERB1                    (0x00000002)
+#define USB_EPPRIME_PERB2                    (0x00000004)
+#define USB_EPPRIME_PERB3                    (0x00000008)
+#define USB_EPPRIME_PERB4                    (0x00000010)
+#define USB_EPPRIME_PERB5                    (0x00000020)
+
+/* Bit definitions and macros for USB_EPFLUSH */
+#define USB_EPFLUSH_FERB(x)                  (((x)&0x0000003F)<<0)
+#define USB_EPFLUSH_FETB(x)                  (((x)&0x0000003F)<<16)
+#define USB_EPFLUSH_FETB0                    (0x00010000)
+#define USB_EPFLUSH_FETB1                    (0x00020000)
+#define USB_EPFLUSH_FETB2                    (0x00040000)
+#define USB_EPFLUSH_FETB3                    (0x00080000)
+#define USB_EPFLUSH_FETB4                    (0x00100000)
+#define USB_EPFLUSH_FETB5                    (0x00200000)
+#define USB_EPFLUSH_FERB0                    (0x00000001)
+#define USB_EPFLUSH_FERB1                    (0x00000002)
+#define USB_EPFLUSH_FERB2                    (0x00000004)
+#define USB_EPFLUSH_FERB3                    (0x00000008)
+#define USB_EPFLUSH_FERB4                    (0x00000010)
+#define USB_EPFLUSH_FERB5                    (0x00000020)
+
+/* Bit definitions and macros for USB_EPSR */
+#define USB_EPSR_ERBR(x)                     (((x)&0x0000003F)<<0)
+#define USB_EPSR_ETBR(x)                     (((x)&0x0000003F)<<16)
+#define USB_EPSR_ETBR0                       (0x00010000)
+#define USB_EPSR_ETBR1                       (0x00020000)
+#define USB_EPSR_ETBR2                       (0x00040000)
+#define USB_EPSR_ETBR3                       (0x00080000)
+#define USB_EPSR_ETBR4                       (0x00100000)
+#define USB_EPSR_ETBR5                       (0x00200000)
+#define USB_EPSR_ERBR0                       (0x00000001)
+#define USB_EPSR_ERBR1                       (0x00000002)
+#define USB_EPSR_ERBR2                       (0x00000004)
+#define USB_EPSR_ERBR3                       (0x00000008)
+#define USB_EPSR_ERBR4                       (0x00000010)
+#define USB_EPSR_ERBR5                       (0x00000020)
+
+/* Bit definitions and macros for USB_EPCOMPLETE */
+#define USB_EPCOMPLETE_ERCE(x)               (((x)&0x0000003F)<<0)
+#define USB_EPCOMPLETE_ETCE(x)               (((x)&0x0000003F)<<16)
+#define USB_EPCOMPLETE_ETCE0                 (0x00010000)
+#define USB_EPCOMPLETE_ETCE1                 (0x00020000)
+#define USB_EPCOMPLETE_ETCE2                 (0x00040000)
+#define USB_EPCOMPLETE_ETCE3                 (0x00080000)
+#define USB_EPCOMPLETE_ETCE4                 (0x00100000)
+#define USB_EPCOMPLETE_ETCE5                 (0x00200000)
+#define USB_EPCOMPLETE_ERCE0                 (0x00000001)
+#define USB_EPCOMPLETE_ERCE1                 (0x00000002)
+#define USB_EPCOMPLETE_ERCE2                 (0x00000004)
+#define USB_EPCOMPLETE_ERCE3                 (0x00000008)
+#define USB_EPCOMPLETE_ERCE4                 (0x00000010)
+#define USB_EPCOMPLETE_ERCE5                 (0x00000020)
+
+/* Bit definitions and macros for USB_EPCR0 */
+#define USB_EPCR0_RXS                        (0x00000001)
+#define USB_EPCR0_RXT(x)                     (((x)&0x00000003)<<2)
+#define USB_EPCR0_RXE                        (0x00000080)
+#define USB_EPCR0_TXS                        (0x00010000)
+#define USB_EPCR0_TXT(x)                     (((x)&0x00000003)<<18)
+#define USB_EPCR0_TXE                        (0x00800000)
+
+/* Bit definitions and macros for USB_EPCR */
+#define USB_EPCR_RXS                         (0x00000001)
+#define USB_EPCR_RXD                         (0x00000002)
+#define USB_EPCR_RXT(x)                      (((x)&0x00000003)<<2)
+#define USB_EPCR_RXI                         (0x00000020)
+#define USB_EPCR_RXR                         (0x00000040)
+#define USB_EPCR_RXE                         (0x00000080)
+#define USB_EPCR_TXS                         (0x00010000)
+#define USB_EPCR_TXD                         (0x00020000)
+#define USB_EPCR_TXT(x)                      (((x)&0x00000003)<<18)
+#define USB_EPCR_TXI                         (0x00200000)
+#define USB_EPCR_TXR                         (0x00400000)
+#define USB_EPCR_TXE                         (0x00800000)
+#define USB_EPCR_TXT_CONTROL                 (0x00000000)
+#define USB_EPCR_TXT_ISO                     (0x00040000)
+#define USB_EPCR_TXT_BULK                    (0x00080000)
+#define USB_EPCR_TXT_INT                     (0x000C0000)
+#define USB_EPCR_RXT_CONTROL                 (0x00000000)
+#define USB_EPCR_RXT_ISO                     (0x00000004)
+#define USB_EPCR_RXT_BULK                    (0x00000008)
+#define USB_EPCR_RXT_INT                     (0x0000000C)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_SDMR */
+#define SDRAMC_SDMR_BNKAD_LEMR      (0x40000000)
+#define SDRAMC_SDMR_BNKAD_LMR       (0x00000000)
+#define SDRAMC_SDMR_AD(x)           (((x)&0x00000FFF)<<18)
+#define SDRAMC_SDMR_CMD             (0x00010000)
+
+/* Bit definitions and macros for SDRAMC_SDCR */
+#define SDRAMC_SDCR_MODE_EN        (0x80000000)
+#define SDRAMC_SDCR_CKE            (0x40000000)
+#define SDRAMC_SDCR_DDR            (0x20000000)
+#define SDRAMC_SDCR_REF            (0x10000000)
+#define SDRAMC_SDCR_MUX(x)         (((x)&0x00000003)<<24)
+#define SDRAMC_SDCR_OE_RULE        (0x00400000)
+#define SDRAMC_SDCR_RCNT(x)        (((x)&0x0000003F)<<16)
+#define SDRAMC_SDCR_PS_32          (0x00000000)
+#define SDRAMC_SDCR_PS_16          (0x00002000)
+#define SDRAMC_SDCR_DQS_OE(x)      (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCR_IREF           (0x00000004)
+#define SDRAMC_SDCR_IPALL          (0x00000002)
+
+/* Bit definitions and macros for SDRAMC_SDCFG1 */
+#define SDRAMC_SDCFG1_SRD2RW(x)    (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG1_SWT2RD(x)    (((x)&0x00000007)<<24)
+#define SDRAMC_SDCFG1_RDLAT(x)     (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG1_ACT2RW(x)    (((x)&0x00000007)<<16)
+#define SDRAMC_SDCFG1_PRE2ACT(x)   (((x)&0x00000007)<<12)
+#define SDRAMC_SDCFG1_REF2ACT(x)   (((x)&0x0000000F)<<8)
+#define SDRAMC_SDCFG1_WTLAT(x)     (((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for SDRAMC_SDCFG2 */
+#define SDRAMC_SDCFG2_BRD2PRE(x)   (((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG2_BWT2RW(x)    (((x)&0x0000000F)<<24)
+#define SDRAMC_SDCFG2_BRD2WT(x)    (((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG2_BL(x)        (((x)&0x0000000F)<<16)
+
+/* Bit definitions and macros for SDRAMC_SDDS */
+#define SDRAMC_SDDS_SB_E(x)        (((x)&0x00000003)<<8)
+#define SDRAMC_SDDS_SB_C(x)        (((x)&0x00000003)<<6)
+#define SDRAMC_SDDS_SB_A(x)        (((x)&0x00000003)<<4)
+#define SDRAMC_SDDS_SB_S(x)        (((x)&0x00000003)<<2)
+#define SDRAMC_SDDS_SB_D(x)        ((x)&0x00000003)
+
+/* Bit definitions and macros for SDRAMC_SDCS */
+#define SDRAMC_SDCS_BASE(x)        (((x)&0x00000FFF)<<20)
+#define SDRAMC_SDCS_CSSZ(x)        ((x)&0x0000001F)
+#define SDRAMC_SDCS_CSSZ_4GBYTE    (0x0000001F)
+#define SDRAMC_SDCS_CSSZ_2GBYTE    (0x0000001E)
+#define SDRAMC_SDCS_CSSZ_1GBYTE    (0x0000001D)
+#define SDRAMC_SDCS_CSSZ_512MBYTE  (0x0000001C)
+#define SDRAMC_SDCS_CSSZ_256MBYTE  (0x0000001B)
+#define SDRAMC_SDCS_CSSZ_128MBYTE  (0x0000001A)
+#define SDRAMC_SDCS_CSSZ_64MBYTE   (0x00000019)
+#define SDRAMC_SDCS_CSSZ_32MBYTE   (0x00000018)
+#define SDRAMC_SDCS_CSSZ_16MBYTE   (0x00000017)
+#define SDRAMC_SDCS_CSSZ_8MBYTE    (0x00000016)
+#define SDRAMC_SDCS_CSSZ_4MBYTE    (0x00000015)
+#define SDRAMC_SDCS_CSSZ_2MBYTE    (0x00000014)
+#define SDRAMC_SDCS_CSSZ_1MBYTE    (0x00000013)
+#define SDRAMC_SDCS_CSSZ_DIABLE    (0x00000000)
+
+/*********************************************************************
+* Synchronous Serial Interface (SSI)
+*********************************************************************/
+/* Bit definitions and macros for SSI_CR */
+#define SSI_CR_CIS                  (0x00000200)
+#define SSI_CR_TCH                  (0x00000100)
+#define SSI_CR_MCE                  (0x00000080)
+#define SSI_CR_I2S_SLAVE            (0x00000040)
+#define SSI_CR_I2S_MASTER           (0x00000020)
+#define SSI_CR_I2S_NORMAL           (0x00000000)
+#define SSI_CR_SYN                  (0x00000010)
+#define SSI_CR_NET                  (0x00000008)
+#define SSI_CR_RE                   (0x00000004)
+#define SSI_CR_TE                   (0x00000002)
+#define SSI_CR_SSI_EN               (0x00000001)
+
+/* Bit definitions and macros for SSI_ISR */
+#define SSI_ISR_CMDAU               (0x00040000)
+#define SSI_ISR_CMDDU               (0x00020000)
+#define SSI_ISR_RXT                 (0x00010000)
+#define SSI_ISR_RDR1                (0x00008000)
+#define SSI_ISR_RDR0                (0x00004000)
+#define SSI_ISR_TDE1                (0x00002000)
+#define SSI_ISR_TDE0                (0x00001000)
+#define SSI_ISR_ROE1                (0x00000800)
+#define SSI_ISR_ROE0                (0x00000400)
+#define SSI_ISR_TUE1                (0x00000200)
+#define SSI_ISR_TUE0                (0x00000100)
+#define SSI_ISR_TFS                 (0x00000080)
+#define SSI_ISR_RFS                 (0x00000040)
+#define SSI_ISR_TLS                 (0x00000020)
+#define SSI_ISR_RLS                 (0x00000010)
+#define SSI_ISR_RFF1                (0x00000008)
+#define SSI_ISR_RFF0                (0x00000004)
+#define SSI_ISR_TFE1                (0x00000002)
+#define SSI_ISR_TFE0                (0x00000001)
+
+/* Bit definitions and macros for SSI_IER */
+#define SSI_IER_RDMAE               (0x00400000)
+#define SSI_IER_RIE                 (0x00200000)
+#define SSI_IER_TDMAE               (0x00100000)
+#define SSI_IER_TIE                 (0x00080000)
+#define SSI_IER_CMDAU               (0x00040000)
+#define SSI_IER_CMDU                (0x00020000)
+#define SSI_IER_RXT                 (0x00010000)
+#define SSI_IER_RDR1                (0x00008000)
+#define SSI_IER_RDR0                (0x00004000)
+#define SSI_IER_TDE1                (0x00002000)
+#define SSI_IER_TDE0                (0x00001000)
+#define SSI_IER_ROE1                (0x00000800)
+#define SSI_IER_ROE0                (0x00000400)
+#define SSI_IER_TUE1                (0x00000200)
+#define SSI_IER_TUE0                (0x00000100)
+#define SSI_IER_TFS                 (0x00000080)
+#define SSI_IER_RFS                 (0x00000040)
+#define SSI_IER_TLS                 (0x00000020)
+#define SSI_IER_RLS                 (0x00000010)
+#define SSI_IER_RFF1                (0x00000008)
+#define SSI_IER_RFF0                (0x00000004)
+#define SSI_IER_TFE1                (0x00000002)
+#define SSI_IER_TFE0                (0x00000001)
+
+/* Bit definitions and macros for SSI_TCR */
+#define SSI_TCR_TXBIT0              (0x00000200)
+#define SSI_TCR_TFEN1               (0x00000100)
+#define SSI_TCR_TFEN0               (0x00000080)
+#define SSI_TCR_TFDIR               (0x00000040)
+#define SSI_TCR_TXDIR               (0x00000020)
+#define SSI_TCR_TSHFD               (0x00000010)
+#define SSI_TCR_TSCKP               (0x00000008)
+#define SSI_TCR_TFSI                (0x00000004)
+#define SSI_TCR_TFSL                (0x00000002)
+#define SSI_TCR_TEFS                (0x00000001)
+
+/* Bit definitions and macros for SSI_RCR */
+#define SSI_RCR_RXEXT               (0x00000400)
+#define SSI_RCR_RXBIT0              (0x00000200)
+#define SSI_RCR_RFEN1               (0x00000100)
+#define SSI_RCR_RFEN0               (0x00000080)
+#define SSI_RCR_RSHFD               (0x00000010)
+#define SSI_RCR_RSCKP               (0x00000008)
+#define SSI_RCR_RFSI                (0x00000004)
+#define SSI_RCR_RFSL                (0x00000002)
+#define SSI_RCR_REFS                (0x00000001)
+
+/* Bit definitions and macros for SSI_CCR */
+#define SSI_CCR_DIV2                (0x00040000)
+#define SSI_CCR_PSR                 (0x00020000)
+#define SSI_CCR_WL(x)               (((x)&0x0000000F)<<13)
+#define SSI_CCR_DC(x)               (((x)&0x0000001F)<<8)
+#define SSI_CCR_PM(x)               ((x)&0x000000FF)
+
+/* Bit definitions and macros for SSI_FCSR */
+#define SSI_FCSR_RFCNT1(x)          (((x)&0x0000000F)<<28)
+#define SSI_FCSR_TFCNT1(x)          (((x)&0x0000000F)<<24)
+#define SSI_FCSR_RFWM1(x)           (((x)&0x0000000F)<<20)
+#define SSI_FCSR_TFWM1(x)           (((x)&0x0000000F)<<16)
+#define SSI_FCSR_RFCNT0(x)          (((x)&0x0000000F)<<12)
+#define SSI_FCSR_TFCNT0(x)          (((x)&0x0000000F)<<8)
+#define SSI_FCSR_RFWM0(x)           (((x)&0x0000000F)<<4)
+#define SSI_FCSR_TFWM0(x)           ((x)&0x0000000F)
+
+/* Bit definitions and macros for SSI_ACR */
+#define SSI_ACR_FRDIV(x)            (((x)&0x0000003F)<<5)
+#define SSI_ACR_WR                  (0x00000010)
+#define SSI_ACR_RD                  (0x00000008)
+#define SSI_ACR_TIF                 (0x00000004)
+#define SSI_ACR_FV                  (0x00000002)
+#define SSI_ACR_AC97EN              (0x00000001)
+
+/* Bit definitions and macros for SSI_ACADD */
+#define SSI_ACADD_SSI_ACADD(x)      ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ACDAT */
+#define SSI_ACDAT_SSI_ACDAT(x)      ((x)&0x0007FFFF)
+
+/* Bit definitions and macros for SSI_ATAG */
+#define SSI_ATAG_DDI_ATAG(x)        ((x)&0x0000FFFF)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+/* Bit definitions and macros for PLL_PODR */
+#define PLL_PODR_CPUDIV(x)          (((x)&0x0F)<<4)
+#define PLL_PODR_BUSDIV(x)          ((x)&0x0F)
+
+/* Bit definitions and macros for PLL_PLLCR */
+#define PLL_PLLCR_DITHEN            (0x80)
+#define PLL_PLLCR_DITHDEV(x)        ((x)&0x07)
+
+#endif				/* mcf5329_h */
diff --git a/include/asm-m68k/mcfrtc.h b/include/asm-m68k/mcfrtc.h
new file mode 100644
index 000000000..70785354f
--- /dev/null
+++ b/include/asm-m68k/mcfrtc.h
@@ -0,0 +1,108 @@
+/*
+ * RealTime Clock
+ *
+ * (C) Copyright 2007
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCFRTC_H__
+#define __MCFRTC_H__
+
+/* Real time Clock */
+typedef struct rtc_ctrl {
+	u32 hourmin;		/* 0x00 Hours and Minutes Counter Register */
+	u32 seconds;		/* 0x04 Seconds Counter Register */
+	u32 alrm_hm;		/* 0x08 Hours and Minutes Alarm Register */
+	u32 alrm_sec;		/* 0x0C Seconds Alarm Register */
+	u32 cr;			/* 0x10 Control Register */
+	u32 isr;		/* 0x14 Interrupt Status Register */
+	u32 ier;		/* 0x18 Interrupt Enable Register */
+	u32 stpwach;		/* 0x1C Stopwatch Minutes Register */
+	u32 days;		/* 0x20 Days Counter Register */
+	u32 alrm_day;		/* 0x24 Days Alarm Register */
+} rtc_t;
+
+/* Bit definitions and macros for HOURMIN */
+#define RTC_HOURMIN_MINUTES(x)	(((x)&0x0000003F))
+#define RTC_HOURMIN_HOURS(x)	(((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for SECONDS */
+#define RTC_SECONDS_SECONDS(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for ALRM_HM */
+#define RTC_ALRM_HM_MINUTES(x)	(((x)&0x0000003F))
+#define RTC_ALRM_HM_HOURS(x)	(((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for ALRM_SEC */
+#define RTC_ALRM_SEC_SECONDS(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for CR */
+#define RTC_CR_SWR		(0x00000001)
+#define RTC_CR_XTL(x)		(((x)&0x00000003)<<5)
+#define RTC_CR_EN		(0x00000080)
+#define RTC_CR_32768		(0x0)
+#define RTC_CR_32000		(0x1)
+#define RTC_CR_38400		(0x2)
+
+/* Bit definitions and macros for ISR */
+#define RTC_ISR_SW		(0x00000001)
+#define RTC_ISR_MIN		(0x00000002)
+#define RTC_ISR_ALM		(0x00000004)
+#define RTC_ISR_DAY		(0x00000008)
+#define RTC_ISR_1HZ		(0x00000010)
+#define RTC_ISR_HR		(0x00000020)
+#define RTC_ISR_2HZ		(0x00000080)
+#define RTC_ISR_SAM0		(0x00000100)
+#define RTC_ISR_SAM1		(0x00000200)
+#define RTC_ISR_SAM2		(0x00000400)
+#define RTC_ISR_SAM3		(0x00000800)
+#define RTC_ISR_SAM4		(0x00001000)
+#define RTC_ISR_SAM5		(0x00002000)
+#define RTC_ISR_SAM6		(0x00004000)
+#define RTC_ISR_SAM7		(0x00008000)
+
+/* Bit definitions and macros for IER */
+#define RTC_IER_SW		(0x00000001)
+#define RTC_IER_MIN		(0x00000002)
+#define RTC_IER_ALM		(0x00000004)
+#define RTC_IER_DAY		(0x00000008)
+#define RTC_IER_1HZ		(0x00000010)
+#define RTC_IER_HR		(0x00000020)
+#define RTC_IER_2HZ		(0x00000080)
+#define RTC_IER_SAM0		(0x00000100)
+#define RTC_IER_SAM1		(0x00000200)
+#define RTC_IER_SAM2		(0x00000400)
+#define RTC_IER_SAM3		(0x00000800)
+#define RTC_IER_SAM4		(0x00001000)
+#define RTC_IER_SAM5		(0x00002000)
+#define RTC_IER_SAM6		(0x00004000)
+#define RTC_IER_SAM7		(0x00008000)
+
+/* Bit definitions and macros for STPWCH */
+#define RTC_STPWCH_CNT(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for DAYS */
+#define RTC_DAYS_DAYS(x)	(((x)&0x0000FFFF))
+
+/* Bit definitions and macros for ALRM_DAY */
+#define RTC_ALRM_DAY_DAYS(x)	(((x)&0x0000FFFF))
+
+#endif				/* __MCFRTC_H__ */
diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h
index a73b80eaf..988860d07 100644
--- a/include/asm-m68k/mcftimer.h
+++ b/include/asm-m68k/mcftimer.h
@@ -35,32 +35,31 @@
  *	Get address specific defines for this ColdFire member.
  */
 #if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define	MCFTIMER_BASE1		0x100		/* Base address of TIMER1 */
-#define	MCFTIMER_BASE2		0x120		/* Base address of TIMER2 */
+#define	MCFTIMER_BASE1		0x100	/* Base address of TIMER1 */
+#define	MCFTIMER_BASE2		0x120	/* Base address of TIMER2 */
 #elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1		0x200           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x220           /* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0x240           /* Base address of TIMER4 */
-#define MCFTIMER_BASE4		0x260           /* Base address of TIMER3 */
+#define MCFTIMER_BASE1		0x200	/* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x220	/* Base address of TIMER2 */
+#define MCFTIMER_BASE3		0x240	/* Base address of TIMER4 */
+#define MCFTIMER_BASE4		0x260	/* Base address of TIMER3 */
 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1		0x140           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x180           /* Base address of TIMER2 */
+#define MCFTIMER_BASE1		0x140	/* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x180	/* Base address of TIMER2 */
 #elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
-#define MCFTIMER_BASE1		0x150000        /* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x160000        /* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0x170000        /* Base address of TIMER4 */
+#define MCFTIMER_BASE1		0x150000	/* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x160000	/* Base address of TIMER2 */
+#define MCFTIMER_BASE3		0x170000	/* Base address of TIMER4 */
 #define MCFTIMER_BASE4		0x180000	/* Base address of TIMER3 */
 #endif
 
 /*
  *	Define the TIMER register set addresses.
  */
-#define	MCFTIMER_TMR		0x00		/* Timer Mode reg (r/w) */
-#define	MCFTIMER_TRR		0x02		/* Timer Reference (r/w) */
-#define	MCFTIMER_TCR		0x04		/* Timer Capture reg (r/w) */
-#define	MCFTIMER_TCN		0x06		/* Timer Counter reg (r/w) */
-#define	MCFTIMER_TER		0x11		/* Timer Event reg (r/w) */
-
+#define	MCFTIMER_TMR		0x00	/* Timer Mode reg (r/w) */
+#define	MCFTIMER_TRR		0x02	/* Timer Reference (r/w) */
+#define	MCFTIMER_TCR		0x04	/* Timer Capture reg (r/w) */
+#define	MCFTIMER_TCN		0x06	/* Timer Counter reg (r/w) */
+#define	MCFTIMER_TER		0x11	/* Timer Event reg (r/w) */
 
 /*
  *	Define the TIMER register set addresses for 5282.
@@ -73,29 +72,29 @@
  *	Bit definitions for the Timer Mode Register (TMR).
  *	Register bit flags are common accross ColdFires.
  */
-#define	MCFTIMER_TMR_PREMASK	0xff00		/* Prescalar mask */
-#define	MCFTIMER_TMR_DISCE	0x0000		/* Disable capture */
-#define	MCFTIMER_TMR_ANYCE	0x00c0		/* Capture any edge */
-#define	MCFTIMER_TMR_FALLCE	0x0080		/* Capture fallingedge */
-#define	MCFTIMER_TMR_RISECE	0x0040		/* Capture rising edge */
-#define	MCFTIMER_TMR_ENOM	0x0020		/* Enable output toggle */
-#define	MCFTIMER_TMR_DISOM	0x0000		/* Do single output pulse  */
-#define	MCFTIMER_TMR_ENORI	0x0010		/* Enable ref interrupt */
-#define	MCFTIMER_TMR_DISORI	0x0000		/* Disable ref interrupt */
-#define	MCFTIMER_TMR_RESTART	0x0008		/* Restart counter */
-#define	MCFTIMER_TMR_FREERUN	0x0000		/* Free running counter */
-#define	MCFTIMER_TMR_CLKTIN	0x0006		/* Input clock is TIN */
-#define	MCFTIMER_TMR_CLK16	0x0004		/* Input clock is /16 */
-#define	MCFTIMER_TMR_CLK1	0x0002		/* Input clock is /1 */
-#define	MCFTIMER_TMR_CLKSTOP	0x0000		/* Stop counter */
-#define	MCFTIMER_TMR_ENABLE	0x0001		/* Enable timer */
-#define	MCFTIMER_TMR_DISABLE	0x0000		/* Disable timer */
+#define	MCFTIMER_TMR_PREMASK	0xff00	/* Prescalar mask */
+#define	MCFTIMER_TMR_DISCE	0x0000	/* Disable capture */
+#define	MCFTIMER_TMR_ANYCE	0x00c0	/* Capture any edge */
+#define	MCFTIMER_TMR_FALLCE	0x0080	/* Capture fallingedge */
+#define	MCFTIMER_TMR_RISECE	0x0040	/* Capture rising edge */
+#define	MCFTIMER_TMR_ENOM	0x0020	/* Enable output toggle */
+#define	MCFTIMER_TMR_DISOM	0x0000	/* Do single output pulse  */
+#define	MCFTIMER_TMR_ENORI	0x0010	/* Enable ref interrupt */
+#define	MCFTIMER_TMR_DISORI	0x0000	/* Disable ref interrupt */
+#define	MCFTIMER_TMR_RESTART	0x0008	/* Restart counter */
+#define	MCFTIMER_TMR_FREERUN	0x0000	/* Free running counter */
+#define	MCFTIMER_TMR_CLKTIN	0x0006	/* Input clock is TIN */
+#define	MCFTIMER_TMR_CLK16	0x0004	/* Input clock is /16 */
+#define	MCFTIMER_TMR_CLK1	0x0002	/* Input clock is /1 */
+#define	MCFTIMER_TMR_CLKSTOP	0x0000	/* Stop counter */
+#define	MCFTIMER_TMR_ENABLE	0x0001	/* Enable timer */
+#define	MCFTIMER_TMR_DISABLE	0x0000	/* Disable timer */
 
 /*
  *	Bit definitions for the Timer Event Registers (TER).
  */
-#define	MCFTIMER_TER_CAP	0x01		/* Capture event */
-#define	MCFTIMER_TER_REF	0x02		/* Refernece event */
+#define	MCFTIMER_TER_CAP	0x01	/* Capture event */
+#define	MCFTIMER_TER_REF	0x02	/* Refernece event */
 
 /*
  *	Bit definitions for the 5282 PIT Control and Status Register (PCSR).
@@ -108,6 +107,77 @@
 #define MCFTIMER_PCSR_HALTED	0x0020
 #define MCFTIMER_PCSR_DOZE	0x0040
 
+/****************************************************************************/
+/* New Timer structure */
+/****************************************************************************/
+/* DMA Timer module registers */
+typedef struct dtimer_ctrl {
+	u16 tmr;		/* 0x00 Mode register */
+	u8 txmr;		/* 0x02 Extended Mode register */
+	u8 ter;			/* 0x03 Event register */
+	u32 trr;		/* 0x04 Reference register */
+	u32 tcr;		/* 0x08 Capture register */
+	u32 tcn;		/* 0x0C Counter register */
+} dtmr_t;
+
+/*Programmable Interrupt Timer */
+typedef struct pit_ctrl {
+	u16 pcsr;		/* 0x00 Control and Status Register */
+	u16 pmr;		/* 0x02 Modulus Register */
+	u16 pcntr;		/* 0x04 Count Register */
+} pit_t;
+
+/*********************************************************************
+* DMA Timers (DTIM)
+*********************************************************************/
+/* Bit definitions and macros for DTMR */
+#define DTIM_DTMR_RST		(0x0001)	/* Reset */
+#define DTIM_DTMR_CLK(x)	(((x)&0x0003)<<1)	/* Input clock source */
+#define DTIM_DTMR_FRR		(0x0008)	/* Free run/restart */
+#define DTIM_DTMR_ORRI		(0x0010)	/* Output reference request/interrupt enable */
+#define DTIM_DTMR_OM		(0x0020)	/* Output Mode */
+#define DTIM_DTMR_CE(x)		(((x)&0x0003)<<6)	/* Capture Edge */
+#define DTIM_DTMR_PS(x)		(((x)&0x00FF)<<8)	/* Prescaler value */
+#define DTIM_DTMR_RST_EN	(0x0001)
+#define DTIM_DTMR_RST_RST	(0x0000)
+#define DTIM_DTMR_CE_ANY	(0x00C0)
+#define DTIM_DTMR_CE_FALL	(0x0080)
+#define DTIM_DTMR_CE_RISE	(0x0040)
+#define DTIM_DTMR_CE_NONE	(0x0000)
+#define DTIM_DTMR_CLK_DTIN	(0x0006)
+#define DTIM_DTMR_CLK_DIV16	(0x0004)
+#define DTIM_DTMR_CLK_DIV1	(0x0002)
+#define DTIM_DTMR_CLK_STOP	(0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define DTIM_DTXMR_MODE16	(0x01)	/* Increment Mode */
+#define DTIM_DTXMR_DMAEN	(0x80)	/* DMA request */
+
+/* Bit definitions and macros for DTER */
+#define DTIM_DTER_CAP		(0x01)	/* Capture event */
+#define DTIM_DTER_REF		(0x02)	/* Output reference event */
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer Modules (PIT)
+*
+*********************************************************************/
+
+/* Bit definitions and macros for PCSR */
+#define PIT_PCSR_EN		(0x0001)
+#define PIT_PCSR_RLD		(0x0002)
+#define PIT_PCSR_PIF		(0x0004)
+#define PIT_PCSR_PIE		(0x0008)
+#define PIT_PCSR_OVW		(0x0010)
+#define PIT_PCSR_HALTED		(0x0020)
+#define PIT_PCSR_DOZE		(0x0040)
+#define PIT_PCSR_PRE(x)		(((x)&0x000F)<<8)
+
+/* Bit definitions and macros for PMR */
+#define PIT_PMR_PM(x)		(x)
+
+/* Bit definitions and macros for PCNTR */
+#define PIT_PCNTR_PC(x)		(x)
 
 /****************************************************************************/
-#endif	/* mcftimer_h */
+#endif				/* mcftimer_h */
diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h
index 7c0999d61..43b49a87c 100644
--- a/include/asm-m68k/mcfuart.h
+++ b/include/asm-m68k/mcfuart.h
@@ -36,106 +36,105 @@
  *	space.
  */
 #if defined(CONFIG_M5272)
-#define	MCFUART_BASE1		0x100		/* Base address of UART1 */
-#define	MCFUART_BASE2		0x140		/* Base address of UART2 */
+#define	MCFUART_BASE1		0x100	/* Base address of UART1 */
+#define	MCFUART_BASE2		0x140	/* Base address of UART2 */
 #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
 #if defined(CONFIG_NETtel)
-#define	MCFUART_BASE1		0x180		/* Base address of UART1 */
-#define	MCFUART_BASE2		0x140		/* Base address of UART2 */
+#define	MCFUART_BASE1		0x180	/* Base address of UART1 */
+#define	MCFUART_BASE2		0x140	/* Base address of UART2 */
 #else
-#define	MCFUART_BASE1		0x140		/* Base address of UART1 */
-#define	MCFUART_BASE2		0x180		/* Base address of UART2 */
+#define	MCFUART_BASE1		0x140	/* Base address of UART1 */
+#define	MCFUART_BASE2		0x180	/* Base address of UART2 */
 #endif
 #elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define MCFUART_BASE1		0x200           /* Base address of UART1 */
-#define MCFUART_BASE2		0x240           /* Base address of UART2 */
-#define MCFUART_BASE3		0x280           /* Base address of UART3 */
+#define MCFUART_BASE1		0x200	/* Base address of UART1 */
+#define MCFUART_BASE2		0x240	/* Base address of UART2 */
+#define MCFUART_BASE3		0x280	/* Base address of UART3 */
 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
 #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1		0x200           /* Base address of UART1 */
-#define MCFUART_BASE2		0x1c0           /* Base address of UART2 */
+#define MCFUART_BASE1		0x200	/* Base address of UART1 */
+#define MCFUART_BASE2		0x1c0	/* Base address of UART2 */
 #else
-#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
-#define MCFUART_BASE2		0x200           /* Base address of UART2 */
+#define MCFUART_BASE1		0x1c0	/* Base address of UART1 */
+#define MCFUART_BASE2		0x200	/* Base address of UART2 */
 #endif
 #endif
 
-
 /*
  *	Define the ColdFire UART register set addresses.
  */
-#define	MCFUART_UMR		0x00		/* Mode register (r/w) */
-#define	MCFUART_USR		0x04		/* Status register (r) */
-#define	MCFUART_UCSR		0x04		/* Clock Select (w) */
-#define	MCFUART_UCR		0x08		/* Command register (w) */
-#define	MCFUART_URB		0x0c		/* Receiver Buffer (r) */
-#define	MCFUART_UTB		0x0c		/* Transmit Buffer (w) */
-#define	MCFUART_UIPCR		0x10		/* Input Port Change (r) */
-#define	MCFUART_UACR		0x10		/* Auxiliary Control (w) */
-#define	MCFUART_UISR		0x14		/* Interrup Status (r) */
-#define	MCFUART_UIMR		0x14		/* Interrupt Mask (w) */
-#define	MCFUART_UBG1		0x18		/* Baud Rate MSB (r/w) */
-#define	MCFUART_UBG2		0x1c		/* Baud Rate LSB (r/w) */
+#define	MCFUART_UMR		0x00	/* Mode register (r/w) */
+#define	MCFUART_USR		0x04	/* Status register (r) */
+#define	MCFUART_UCSR		0x04	/* Clock Select (w) */
+#define	MCFUART_UCR		0x08	/* Command register (w) */
+#define	MCFUART_URB		0x0c	/* Receiver Buffer (r) */
+#define	MCFUART_UTB		0x0c	/* Transmit Buffer (w) */
+#define	MCFUART_UIPCR		0x10	/* Input Port Change (r) */
+#define	MCFUART_UACR		0x10	/* Auxiliary Control (w) */
+#define	MCFUART_UISR		0x14	/* Interrup Status (r) */
+#define	MCFUART_UIMR		0x14	/* Interrupt Mask (w) */
+#define	MCFUART_UBG1		0x18	/* Baud Rate MSB (r/w) */
+#define	MCFUART_UBG2		0x1c	/* Baud Rate LSB (r/w) */
 #ifdef	CONFIG_M5272
-#define	MCFUART_UTF		0x28		/* Transmitter FIFO (r/w) */
-#define	MCFUART_URF		0x2c		/* Receiver FIFO (r/w) */
-#define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
+#define	MCFUART_UTF		0x28	/* Transmitter FIFO (r/w) */
+#define	MCFUART_URF		0x2c	/* Receiver FIFO (r/w) */
+#define	MCFUART_UFPD		0x30	/* Frac Prec. Divider (r/w) */
 #else
-#define	MCFUART_UIVR		0x30		/* Interrupt Vector (r/w) */
+#define	MCFUART_UIVR		0x30	/* Interrupt Vector (r/w) */
 #endif
-#define	MCFUART_UIPR		0x34		/* Input Port (r) */
-#define	MCFUART_UOP1		0x38		/* Output Port Bit Set (w) */
-#define	MCFUART_UOP0		0x3c		/* Output Port Bit Reset (w) */
+#define	MCFUART_UIPR		0x34	/* Input Port (r) */
+#define	MCFUART_UOP1		0x38	/* Output Port Bit Set (w) */
+#define	MCFUART_UOP0		0x3c	/* Output Port Bit Reset (w) */
 
 #ifdef	CONFIG_M5249
 /* Note: This isn't in the 5249 docs */
-#define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
+#define	MCFUART_UFPD		0x30	/* Frac Prec. Divider (r/w) */
 #endif
 
 /*
  *	Define bit flags in Mode Register 1 (MR1).
  */
-#define	MCFUART_MR1_RXRTS	0x80		/* Auto RTS flow control */
-#define	MCFUART_MR1_RXIRQFULL	0x40		/* RX IRQ type FULL */
-#define	MCFUART_MR1_RXIRQRDY	0x00		/* RX IRQ type RDY */
-#define	MCFUART_MR1_RXERRBLOCK	0x20		/* RX block error mode */
-#define	MCFUART_MR1_RXERRCHAR	0x00		/* RX char error mode */
+#define	MCFUART_MR1_RXRTS	0x80	/* Auto RTS flow control */
+#define	MCFUART_MR1_RXIRQFULL	0x40	/* RX IRQ type FULL */
+#define	MCFUART_MR1_RXIRQRDY	0x00	/* RX IRQ type RDY */
+#define	MCFUART_MR1_RXERRBLOCK	0x20	/* RX block error mode */
+#define	MCFUART_MR1_RXERRCHAR	0x00	/* RX char error mode */
 
-#define	MCFUART_MR1_PARITYNONE	0x10		/* No parity */
-#define	MCFUART_MR1_PARITYEVEN	0x00		/* Even parity */
-#define	MCFUART_MR1_PARITYODD	0x04		/* Odd parity */
-#define	MCFUART_MR1_PARITYSPACE	0x08		/* Space parity */
-#define	MCFUART_MR1_PARITYMARK	0x0c		/* Mark parity */
+#define	MCFUART_MR1_PARITYNONE	0x10	/* No parity */
+#define	MCFUART_MR1_PARITYEVEN	0x00	/* Even parity */
+#define	MCFUART_MR1_PARITYODD	0x04	/* Odd parity */
+#define	MCFUART_MR1_PARITYSPACE	0x08	/* Space parity */
+#define	MCFUART_MR1_PARITYMARK	0x0c	/* Mark parity */
 
-#define	MCFUART_MR1_CS5		0x00		/* 5 bits per char */
-#define	MCFUART_MR1_CS6		0x01		/* 6 bits per char */
-#define	MCFUART_MR1_CS7		0x02		/* 7 bits per char */
-#define	MCFUART_MR1_CS8		0x03		/* 8 bits per char */
+#define	MCFUART_MR1_CS5		0x00	/* 5 bits per char */
+#define	MCFUART_MR1_CS6		0x01	/* 6 bits per char */
+#define	MCFUART_MR1_CS7		0x02	/* 7 bits per char */
+#define	MCFUART_MR1_CS8		0x03	/* 8 bits per char */
 
 /*
  *	Define bit flags in Mode Register 2 (MR2).
  */
-#define	MCFUART_MR2_LOOPBACK	0x80		/* Loopback mode */
-#define	MCFUART_MR2_REMOTELOOP	0xc0		/* Remote loopback mode */
-#define	MCFUART_MR2_AUTOECHO	0x40		/* Automatic echo */
-#define	MCFUART_MR2_TXRTS	0x20		/* Assert RTS on TX */
-#define	MCFUART_MR2_TXCTS	0x10		/* Auto CTS flow control */
+#define	MCFUART_MR2_LOOPBACK	0x80	/* Loopback mode */
+#define	MCFUART_MR2_REMOTELOOP	0xc0	/* Remote loopback mode */
+#define	MCFUART_MR2_AUTOECHO	0x40	/* Automatic echo */
+#define	MCFUART_MR2_TXRTS	0x20	/* Assert RTS on TX */
+#define	MCFUART_MR2_TXCTS	0x10	/* Auto CTS flow control */
 
-#define	MCFUART_MR2_STOP1	0x07		/* 1 stop bit */
-#define	MCFUART_MR2_STOP15	0x08		/* 1.5 stop bits */
-#define	MCFUART_MR2_STOP2	0x0f		/* 2 stop bits */
+#define	MCFUART_MR2_STOP1	0x07	/* 1 stop bit */
+#define	MCFUART_MR2_STOP15	0x08	/* 1.5 stop bits */
+#define	MCFUART_MR2_STOP2	0x0f	/* 2 stop bits */
 
 /*
  *	Define bit flags in Status Register (USR).
  */
-#define	MCFUART_USR_RXBREAK	0x80		/* Received BREAK */
-#define	MCFUART_USR_RXFRAMING	0x40		/* Received framing error */
-#define	MCFUART_USR_RXPARITY	0x20		/* Received parity error */
-#define	MCFUART_USR_RXOVERRUN	0x10		/* Received overrun error */
-#define	MCFUART_USR_TXEMPTY	0x08		/* Transmitter empty */
-#define	MCFUART_USR_TXREADY	0x04		/* Transmitter ready */
-#define	MCFUART_USR_RXFULL	0x02		/* Receiver full */
-#define	MCFUART_USR_RXREADY	0x01		/* Receiver ready */
+#define	MCFUART_USR_RXBREAK	0x80	/* Received BREAK */
+#define	MCFUART_USR_RXFRAMING	0x40	/* Received framing error */
+#define	MCFUART_USR_RXPARITY	0x20	/* Received parity error */
+#define	MCFUART_USR_RXOVERRUN	0x10	/* Received overrun error */
+#define	MCFUART_USR_TXEMPTY	0x08	/* Transmitter empty */
+#define	MCFUART_USR_TXREADY	0x04	/* Transmitter ready */
+#define	MCFUART_USR_RXFULL	0x02	/* Receiver full */
+#define	MCFUART_USR_RXREADY	0x01	/* Receiver ready */
 
 #define	MCFUART_USR_RXERR	(MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
 				MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
@@ -143,13 +142,13 @@
 /*
  *	Define bit flags in Clock Select Register (UCSR).
  */
-#define	MCFUART_UCSR_RXCLKTIMER	0xd0		/* RX clock is timer */
-#define	MCFUART_UCSR_RXCLKEXT16	0xe0		/* RX clock is external x16 */
-#define	MCFUART_UCSR_RXCLKEXT1	0xf0		/* RX clock is external x1 */
+#define	MCFUART_UCSR_RXCLKTIMER	0xd0	/* RX clock is timer */
+#define	MCFUART_UCSR_RXCLKEXT16	0xe0	/* RX clock is external x16 */
+#define	MCFUART_UCSR_RXCLKEXT1	0xf0	/* RX clock is external x1 */
 
-#define	MCFUART_UCSR_TXCLKTIMER	0x0d		/* TX clock is timer */
-#define	MCFUART_UCSR_TXCLKEXT16	0x0e		/* TX clock is external x16 */
-#define	MCFUART_UCSR_TXCLKEXT1	0x0f		/* TX clock is external x1 */
+#define	MCFUART_UCSR_TXCLKTIMER	0x0d	/* TX clock is timer */
+#define	MCFUART_UCSR_TXCLKEXT16	0x0e	/* TX clock is external x16 */
+#define	MCFUART_UCSR_TXCLKEXT1	0x0f	/* TX clock is external x1 */
 
 /*
  *	Define bit flags in Command Register (UCR).
@@ -163,59 +162,200 @@
 #define	MCFUART_UCR_CMDBREAKSTART	0x60	/* Start BREAK */
 #define	MCFUART_UCR_CMDBREAKSTOP	0x70	/* Stop BREAK */
 
-#define	MCFUART_UCR_TXNULL	0x00		/* No TX command */
-#define	MCFUART_UCR_TXENABLE	0x04		/* Enable TX */
-#define	MCFUART_UCR_TXDISABLE	0x08		/* Disable TX */
-#define	MCFUART_UCR_RXNULL	0x00		/* No RX command */
-#define	MCFUART_UCR_RXENABLE	0x01		/* Enable RX */
-#define	MCFUART_UCR_RXDISABLE	0x02		/* Disable RX */
+#define	MCFUART_UCR_TXNULL	0x00	/* No TX command */
+#define	MCFUART_UCR_TXENABLE	0x04	/* Enable TX */
+#define	MCFUART_UCR_TXDISABLE	0x08	/* Disable TX */
+#define	MCFUART_UCR_RXNULL	0x00	/* No RX command */
+#define	MCFUART_UCR_RXENABLE	0x01	/* Enable RX */
+#define	MCFUART_UCR_RXDISABLE	0x02	/* Disable RX */
 
 /*
  *	Define bit flags in Input Port Change Register (UIPCR).
  */
-#define	MCFUART_UIPCR_CTSCOS	0x10		/* CTS change of state */
-#define	MCFUART_UIPCR_CTS	0x01		/* CTS value */
+#define	MCFUART_UIPCR_CTSCOS	0x10	/* CTS change of state */
+#define	MCFUART_UIPCR_CTS	0x01	/* CTS value */
 
 /*
  *	Define bit flags in Input Port Register (UIP).
  */
-#define	MCFUART_UIPR_CTS	0x01		/* CTS value */
+#define	MCFUART_UIPR_CTS	0x01	/* CTS value */
 
 /*
  *	Define bit flags in Output Port Registers (UOP).
  *	Clear bit by writing to UOP0, set by writing to UOP1.
  */
-#define	MCFUART_UOP_RTS		0x01		/* RTS set or clear */
+#define	MCFUART_UOP_RTS		0x01	/* RTS set or clear */
 
 /*
  *	Define bit flags in the Auxiliary Control Register (UACR).
  */
-#define	MCFUART_UACR_IEC	0x01		/* Input enable control */
+#define	MCFUART_UACR_IEC	0x01	/* Input enable control */
 
 /*
  *	Define bit flags in Interrupt Status Register (UISR).
  *	These same bits are used for the Interrupt Mask Register (UIMR).
  */
-#define	MCFUART_UIR_COS		0x80		/* Change of state (CTS) */
-#define	MCFUART_UIR_DELTABREAK	0x04		/* Break start or stop */
-#define	MCFUART_UIR_RXREADY	0x02		/* Receiver ready */
-#define	MCFUART_UIR_TXREADY	0x01		/* Transmitter ready */
+#define	MCFUART_UIR_COS		0x80	/* Change of state (CTS) */
+#define	MCFUART_UIR_DELTABREAK	0x04	/* Break start or stop */
+#define	MCFUART_UIR_RXREADY	0x02	/* Receiver ready */
+#define	MCFUART_UIR_TXREADY	0x01	/* Transmitter ready */
 
 #ifdef	CONFIG_M5272
 /*
  *	Define bit flags in the Transmitter FIFO Register (UTF).
  */
-#define	MCFUART_UTF_TXB		0x1f		/* transmitter data level */
-#define	MCFUART_UTF_FULL	0x20		/* transmitter fifo full */
-#define	MCFUART_UTF_TXS		0xc0		/* transmitter status */
+#define	MCFUART_UTF_TXB		0x1f	/* transmitter data level */
+#define	MCFUART_UTF_FULL	0x20	/* transmitter fifo full */
+#define	MCFUART_UTF_TXS		0xc0	/* transmitter status */
 
 /*
  *	Define bit flags in the Receiver FIFO Register (URF).
  */
-#define	MCFUART_URF_RXB		0x1f		/* receiver data level */
-#define	MCFUART_URF_FULL	0x20		/* receiver fifo full */
-#define	MCFUART_URF_RXS		0xc0		/* receiver status */
+#define	MCFUART_URF_RXB		0x1f	/* receiver data level */
+#define	MCFUART_URF_FULL	0x20	/* receiver fifo full */
+#define	MCFUART_URF_RXS		0xc0	/* receiver status */
 #endif
 
+#ifdef	CONFIG_MCFUART
+/* UART module registers */
+/* Register read/write struct */
+typedef struct uart {
+	u8 umr;			/* 0x00 Mode Register */
+	u8 resv0[0x3];
+	union {
+		u8 usr;		/* 0x04 Status Register */
+		u8 ucsr;	/* 0x04 Clock Select Register */
+	};
+	u8 resv1[0x3];
+	u8 ucr;			/* 0x08 Command Register */
+	u8 resv2[0x3];
+	union {
+		u8 utb;		/* 0x0c Transmit Buffer */
+		u8 urb;		/* 0x0c Receive Buffer */
+	};
+	u8 resv3[0x3];
+	union {
+		u8 uipcr;	/* 0x10 Input Port Change Register */
+		u8 uacr;	/* 0x10 Auxiliary Control reg */
+	};
+	u8 resv4[0x3];
+	union {
+		u8 uimr;	/* 0x14 Interrupt Mask reg */
+		u8 uisr;	/* 0x14 Interrupt Status reg */
+	};
+	u8 resv5[0x3];
+	u8 ubg1;		/* 0x18 Counter Timer Upper Register */
+	u8 resv6[0x3];
+	u8 ubg2;		/* 0x1c Counter Timer Lower Register */
+	u8 resv7[0x17];
+	u8 uip;			/* 0x34 Input Port Register */
+	u8 resv8[0x3];
+	u8 uop1;		/* 0x38 Output Port Set Register */
+	u8 resv9[0x3];
+	u8 uop0;		/* 0x3c Output Port Reset Register */
+} uart_t;
+
+/*********************************************************************
+* Universal Asynchronous Receiver Transmitter (UART)
+*********************************************************************/
+/* Bit definitions and macros for UMR */
+#define UART_UMR_BC(x)			(((x)&0x03))
+#define UART_UMR_PT			(0x04)
+#define UART_UMR_PM(x)			(((x)&0x03)<<3)
+#define UART_UMR_ERR			(0x20)
+#define UART_UMR_RXIRQ			(0x40)
+#define UART_UMR_RXRTS			(0x80)
+#define UART_UMR_SB(x)			(((x)&0x0F))
+#define UART_UMR_TXCTS			(0x10)	/* Trsnsmit CTS */
+#define UART_UMR_TXRTS			(0x20)	/* Transmit RTS */
+#define UART_UMR_CM(x)			(((x)&0x03)<<6)	/* CM bits */
+#define UART_UMR_PM_MULTI_ADDR		(0x1C)
+#define UART_UMR_PM_MULTI_DATA		(0x18)
+#define UART_UMR_PM_NONE		(0x10)
+#define UART_UMR_PM_FORCE_HI		(0x0C)
+#define UART_UMR_PM_FORCE_LO		(0x08)
+#define UART_UMR_PM_ODD			(0x04)
+#define UART_UMR_PM_EVEN		(0x00)
+#define UART_UMR_BC_5			(0x00)
+#define UART_UMR_BC_6			(0x01)
+#define UART_UMR_BC_7			(0x02)
+#define UART_UMR_BC_8			(0x03)
+#define UART_UMR_CM_NORMAL		(0x00)
+#define UART_UMR_CM_ECH			(0x40)
+#define UART_UMR_CM_LOCAL_LOOP		(0x80)
+#define UART_UMR_CM_REMOTE_LOOP		(0xC0)
+#define UART_UMR_SB_STOP_BITS_1		(0x07)
+#define UART_UMR_SB_STOP_BITS_15	(0x08)
+#define UART_UMR_SB_STOP_BITS_2		(0x0F)
+
+/* Bit definitions and macros for USR */
+#define UART_USR_RXRDY			(0x01)
+#define UART_USR_FFULL			(0x02)
+#define UART_USR_TXRDY			(0x04)
+#define UART_USR_TXEMP			(0x08)
+#define UART_USR_OE			(0x10)
+#define UART_USR_PE			(0x20)
+#define UART_USR_FE			(0x40)
+#define UART_USR_RB			(0x80)
+
+/* Bit definitions and macros for UCSR */
+#define UART_UCSR_TCS(x)		(((x)&0x0F))
+#define UART_UCSR_RCS(x)		(((x)&0x0F)<<4)
+#define UART_UCSR_RCS_SYS_CLK		(0xD0)
+#define UART_UCSR_RCS_CTM16		(0xE0)
+#define UART_UCSR_RCS_CTM		(0xF0)
+#define UART_UCSR_TCS_SYS_CLK		(0x0D)
+#define UART_UCSR_TCS_CTM16		(0x0E)
+#define UART_UCSR_TCS_CTM		(0x0F)
+
+/* Bit definitions and macros for UCR */
+#define UART_UCR_RXC(x)			(((x)&0x03))
+#define UART_UCR_TXC(x)			(((x)&0x03)<<2)
+#define UART_UCR_MISC(x)		(((x)&0x07)<<4)
+#define UART_UCR_NONE			(0x00)
+#define UART_UCR_STOP_BREAK		(0x70)
+#define UART_UCR_START_BREAK		(0x60)
+#define UART_UCR_BKCHGINT		(0x50)
+#define UART_UCR_RESET_ERROR		(0x40)
+#define UART_UCR_RESET_TX		(0x30)
+#define UART_UCR_RESET_RX		(0x20)
+#define UART_UCR_RESET_MR		(0x10)
+#define UART_UCR_TX_DISABLED		(0x08)
+#define UART_UCR_TX_ENABLED		(0x04)
+#define UART_UCR_RX_DISABLED		(0x02)
+#define UART_UCR_RX_ENABLED		(0x01)
+
+/* Bit definitions and macros for UIPCR */
+#define UART_UIPCR_CTS			(0x01)
+#define UART_UIPCR_COS			(0x10)
+
+/* Bit definitions and macros for UACR */
+#define UART_UACR_IEC			(0x01)
+
+/* Bit definitions and macros for UIMR */
+#define UART_UIMR_TXRDY			(0x01)
+#define UART_UIMR_RXRDY_FU		(0x02)
+#define UART_UIMR_DB			(0x04)
+#define UART_UIMR_COS			(0x80)
+
+/* Bit definitions and macros for UISR */
+#define UART_UISR_TXRDY			(0x01)
+#define UART_UISR_RXRDY_FU		(0x02)
+#define UART_UISR_DB			(0x04)
+#define UART_UISR_RXFTO			(0x08)
+#define UART_UISR_TXFIFO		(0x10)
+#define UART_UISR_RXFIFO		(0x20)
+#define UART_UISR_COS			(0x80)
+
+/* Bit definitions and macros for UIP */
+#define UART_UIP_CTS			(0x01)
+
+/* Bit definitions and macros for UOP1 */
+#define UART_UOP1_RTS			(0x01)
+
+/* Bit definitions and macros for UOP0 */
+#define UART_UOP0_RTS			(0x01)
+#endif				/* CONFIG_MCFUART */
+
 /****************************************************************************/
-#endif	/* mcfuart_h */
+#endif				/* mcfuart_h */
diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h
index 75b241883..01535beb1 100644
--- a/include/asm-m68k/ptrace.h
+++ b/include/asm-m68k/ptrace.h
@@ -28,32 +28,32 @@
 #ifndef __ASSEMBLY__
 
 struct pt_regs {
-	ulong     d0;
-	ulong     d1;
-	ulong     d2;
-	ulong     d3;
-	ulong     d4;
-	ulong     d5;
-	ulong     d6;
-	ulong     d7;
-	ulong     a0;
-	ulong     a1;
-	ulong     a2;
-	ulong     a3;
-	ulong     a4;
-	ulong     a5;
-	ulong     a6;
-#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
-	unsigned format :  4; /* frame format specifier */
-	unsigned vector : 12; /* vector offset */
+	ulong d0;
+	ulong d1;
+	ulong d2;
+	ulong d3;
+	ulong d4;
+	ulong d5;
+	ulong d6;
+	ulong d7;
+	ulong a0;
+	ulong a1;
+	ulong a2;
+	ulong a3;
+	ulong a4;
+	ulong a5;
+	ulong a6;
+#if defined(__M68K__)
+	unsigned format:4;	/* frame format specifier */
+	unsigned vector:12;	/* vector offset */
 	unsigned short sr;
-	unsigned long  pc;
+	unsigned long pc;
 #else
 	unsigned short sr;
-	unsigned long  pc;
+	unsigned long pc;
 #endif
 };
 
-#endif	/* #ifndef __ASSEMBLY__ */
+#endif				/* #ifndef __ASSEMBLY__ */
 
-#endif	/* #ifndef _M68K_PTRACE_H */
+#endif				/* #ifndef _M68K_PTRACE_H */
diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h
index 7a6a8c1ff..70dbda464 100644
--- a/include/asm-m68k/u-boot.h
+++ b/include/asm-m68k/u-boot.h
@@ -37,24 +37,36 @@
 #ifndef __ASSEMBLY__
 
 typedef struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
-	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long	bi_sramstart;	/* start of SRAM memory */
-	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_mbar_base;	/* base of internal registers */
-	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long   bi_boot_params; /* where this board expects params */
-	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
-	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned long	bi_baudrate;	/* Console Baudrate */
+	unsigned long bi_memstart;	/* start of DRAM memory */
+	unsigned long bi_memsize;	/* size  of DRAM memory in bytes */
+	unsigned long bi_flashstart;	/* start of FLASH memory */
+	unsigned long bi_flashsize;	/* size  of FLASH memory */
+	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
+	unsigned long bi_sramstart;	/* start of SRAM memory */
+	unsigned long bi_sramsize;	/* size  of SRAM memory */
+	unsigned long bi_mbar_base;	/* base of internal registers */
+	unsigned long bi_bootflags;	/* boot / reboot flag (for LynxOS) */
+	unsigned long bi_boot_params;	/* where this board expects params */
+	unsigned long bi_ip_addr;	/* IP Address */
+	unsigned char bi_enetaddr[6];	/* Ethernet adress */
+	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
+	unsigned long bi_baudrate;	/* Console Baudrate */
+
+#ifdef CONFIG_HAS_ETH1
+	/* second onboard ethernet port */
+	unsigned char bi_enet1addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH2
+	/* third onboard ethernet port */
+	unsigned char bi_enet2addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH3
+	unsigned char bi_enet3addr[6];
+#endif
 } bd_t;
 
-#endif /* __ASSEMBLY__ */
+#endif				/* __ASSEMBLY__ */
 
-#endif	/* __U_BOOT_H__ */
+#endif				/* __U_BOOT_H__ */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
new file mode 100644
index 000000000..ac529dfbc
--- /dev/null
+++ b/include/configs/M5329EVB.h
@@ -0,0 +1,275 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x		/* define processor family */
+#define CONFIG_M5329		/* define processor type */
+
+#undef DEBUG
+
+#define CONFIG_MCFSERIAL
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+#define CFG_NUM_IRQS	128
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+							  CFG_CMD_CACHE | \
+							  CFG_CMD_DATE | \
+							  CFG_CMD_ELF | \
+							  CFG_CMD_FLASH | \
+							  (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
+							  CFG_CMD_MEMORY | \
+							  CFG_CMD_MISC | \
+							  CFG_CMD_MII | \
+							  CFG_CMD_NET | \
+							  CFG_CMD_PING | \
+							  CFG_CMD_REGINFO \
+							)
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_MULTI	1
+#	define CONFIG_MII		1
+#	define CFG_DISCOVER_PHY
+#	define CFG_RX_ETH_BUFFER	8
+#	define CFG_FAULT_ECHO_LINK_DOWN
+
+#	define CFG_FEC0_IOBASE	0xFC030000
+#	define CFG_FEC0_PINMUX	0
+#	define CFG_FEC0_MIIBASE	CFG_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 50000
+/* If CFG_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CFG_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CFG_FAULT_ECHO_LINK_DOWN
+#			define CFG_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CFG_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFUART
+#ifdef CONFIG_MCFUART
+#	define CFG_UART_PORT		(0)
+#	define CFG_UART_BASE		(0xFC060000)
+#endif
+
+#define CONFIG_MCFRTC
+#ifdef CONFIG_MCFRTC
+#	define CFG_MCFRTC_BASE		(0xFC0A8000)
+#	undef RTC_DEBUG
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#ifdef CONFIG_MCFTMR
+#	define CFG_UDELAY_BASE	(0xFC070000)
+#	define CFG_TMR_BASE		(0xFC074000)
+#	define CFG_TMRINTR_NO	(33)
+#	define CFG_TMRINTR_MASK	(2)
+#	define CFG_TMRINTR_PRI	(6)
+#	define CFG_TIMER_PRESCALER	(((CFG_CLK / 1000000) - 1) << 8)
+#endif
+
+#undef CONFIG_MCFPIT
+#ifdef CONFIG_MCFPIT
+#	define CFG_UDELAY_BASE	(0xFC080000)
+#	define CFG_PIT_BASE		(0xFC084000)
+#	define CFG_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_MCFINTC
+#ifdef CONFIG_MCFINTC
+#	define CFG_INTR_BASE	(0xFC048000)
+#	define CFG_NUM_IRQ0		64
+#	define CFG_NUM_IRQ1		64
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR		192.162.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5329EVB
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=40010000\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 2ffff;"	\
+	"era 0 2ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM			512	/* 512 KB */
+#define CFG_PROMPT			"-> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#	define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
+#else
+#	define CFG_CBSIZE			256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS			16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR		0x40010000
+
+#define CFG_HZ				1000
+#define CFG_CLK				80000000
+#define CFG_CPU_CLK			CFG_CLK * 3
+
+#define CFG_MBAR			0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x80000000
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CFG_INIT_RAM_CTRL	0x221
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x40000000
+#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CFG_SDRAM_CFG1		0x53722730
+#define CFG_SDRAM_CFG2		0x56670000
+#define CFG_SDRAM_CTRL		0xE1092000
+#define CFG_SDRAM_EMOD		0x40010000
+#define CFG_SDRAM_MODE		0x018D0000
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE + 0x400
+#define CFG_MEMTEST_END		((CFG_SDRAM_SIZE - 3) << 20)
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CFG_BOOTPARAMS_LEN	64*1024
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#undef CFG_FLASH_CFI
+#ifdef CFG_FLASH_CFI
+#	define CFG_FLASH_CFI_DRIVER	1
+#	define CFG_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#else
+#	define CFG_FLASH_UNLOCK_TOUT	1000
+#	define CFG_FLASH_WRITE_TOUT		1000
+#endif
+
+#define CFG_FLASH_BASE			0
+#define CFG_FLASH0_BASE			(CFG_CS0_BASE << 16)
+#define CFG_MAX_FLASH_BANKS		1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT		137	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+#define CFG_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CFG_CS0_BASE		0
+#define CFG_CS0_MASK		0x007f0001
+#define CFG_CS0_CTRL		0x00001fa0
+
+#define CFG_CS1_BASE		0x1000
+#define CFG_CS1_MASK		0x001f0001
+#define CFG_CS1_CTRL		0x002A3780
+
+#ifdef NANDFLASH_SIZE
+#define CFG_CS2_BASE		0x00800000
+#define CFG_CS2_MASK		0x00ff0001
+#define CFG_CS2_CTRL		0x00001f60
+#endif
+
+#define CONFIG_UDP_CHECKSUM
+
+#endif				/* _M5329EVB_H */
diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile
index 82165f098..03784fd84 100644
--- a/lib_m68k/Makefile
+++ b/lib_m68k/Makefile
@@ -27,7 +27,7 @@ LIB	= $(obj)lib$(ARCH).a
 
 SOBJS	=
 
-COBJS	= cache.o traps.o time.o board.o m68k_linux.o
+COBJS	= cache.o traps.o time.o interrupts.o board.o m68k_linux.o
 
 SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 6aaf60991..1b515a4c5 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -221,6 +221,7 @@ static int init_func_i2c (void)
  */
 
 init_fnc_t *init_sequence[] = {
+    get_clocks,
 	env_init,
 	init_baudrate,
 	serial_init,
@@ -371,6 +372,10 @@ board_init_f (ulong bootflag)
 	 */
 	bd->bi_memstart  = CFG_SDRAM_BASE;	/* start of  DRAM memory      */
 	bd->bi_memsize   = gd->ram_size;	/* size  of  DRAM memory in bytes */
+#ifdef CFG_INIT_RAM_ADDR
+	bd->bi_sramstart = CFG_INIT_RAM_ADDR;	/* start of  SRAM memory	*/
+	bd->bi_sramsize  = CFG_INIT_RAM_END;	/* size  of  SRAM memory	*/
+#endif
 	bd->bi_mbar_base = CFG_MBAR;		/* base of internal registers */
 
 	bd->bi_bootflags = bootflag;		/* boot / reboot flag (for LynxOS)    */
@@ -430,6 +435,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
+#ifdef CONFIG_SERIAL_MULTI
+	serial_initialize();
+#endif
+
 	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
 	WATCHDOG_RESET ();
@@ -489,7 +498,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/*
 	 * Setup trap handlers
 	 */
-	trap_init (0);
+	trap_init (CFG_SDRAM_BASE);
 
 #if !defined(CFG_NO_FLASH)
 	puts ("FLASH: ");
@@ -562,12 +571,48 @@ void board_init_r (gd_t *id, ulong dest_addr)
 		if (s)
 			s = (*e) ? e + 1 : e;
 	}
+#ifdef CONFIG_HAS_ETH1
+	/* handle the 2nd ethernet address */
+
+	s = getenv ("eth1addr");
+	for (i = 0; i < 6; ++i) {
+		bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+#endif
+#ifdef CONFIG_HAS_ETH2
+	/* handle the 3rd ethernet address */
+
+	s = getenv ("eth2addr");
+	for (i = 0; i < 6; ++i) {
+		bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+	/* handle 4th ethernet address */
+	s = getenv("eth3addr");
+	for (i = 0; i < 6; ++i) {
+		bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+#endif
 
 	/* IP Address */
 	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
 
 	WATCHDOG_RESET ();
 
+#if defined(CONFIG_PCI)
+	/*
+	 * Do pci configuration
+	 */
+	pci_init ();
+#endif
 
 	/** leave this here (after malloc(), environment and PCI are working) **/
 	/* Initialize devices */
@@ -640,15 +685,33 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	nand_init();		/* go init the NAND */
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
 	WATCHDOG_RESET();
+#if defined(FEC_ENET)
 	eth_init(bd);
 #endif
+#if defined(CONFIG_NET_MULTI)
+	puts ("Net:   ");
+	eth_initialize (bd);
+#endif
+#endif
 
 #ifdef CONFIG_POST
 	post_run (NULL, POST_RAM | post_bootmode_get(0));
 #endif
 
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
+	WATCHDOG_RESET ();
+	puts ("PCMCIA:");
+	pcmcia_init ();
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+	WATCHDOG_RESET ();
+	puts ("IDE:   ");
+	ide_init ();
+#endif /* CFG_CMD_IDE */
+
 #ifdef CONFIG_LAST_STAGE_INIT
 	WATCHDOG_RESET ();
 	/*
diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c
new file mode 100644
index 000000000..6b3ce8975
--- /dev/null
+++ b/lib_m68k/interrupts.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_MCFINTC
+#define	NR_IRQS		(CFG_NUM_IRQS)
+
+/*
+ * Interrupt vector functions.
+ */
+struct interrupt_action {
+	interrupt_handler_t *handler;
+	void *arg;
+};
+
+static struct interrupt_action irq_vecs[NR_IRQS];
+
+static __inline__ unsigned short get_sr (void)
+{
+	unsigned short sr;
+
+	asm volatile ("move.w %%sr,%0":"=r" (sr):);
+
+	return sr;
+}
+
+static __inline__ void set_sr (unsigned short sr)
+{
+	asm volatile ("move.w %0,%%sr"::"r" (sr));
+}
+
+/************************************************************************/
+/*
+ * Install and free an interrupt handler
+ */
+void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
+{
+	if ((vec < 0) || (vec > NR_IRQS)) {
+		printf ("irq_install_handler: wrong interrupt vector %d\n",
+			vec);
+		return;
+	}
+
+	irq_vecs[vec].handler = handler;
+	irq_vecs[vec].arg = arg;
+}
+
+void irq_free_handler (int vec)
+{
+	if ((vec < 0) || (vec > NR_IRQS)) {
+		return;
+	}
+
+	irq_vecs[vec].handler = NULL;
+	irq_vecs[vec].arg = NULL;
+}
+
+void enable_interrupts (void)
+{
+	unsigned short sr;
+
+	sr = get_sr ();
+	set_sr (sr & ~0x0700);
+}
+
+int disable_interrupts (void)
+{
+	unsigned short sr;
+
+	sr = get_sr ();
+	set_sr (sr | 0x0700);
+
+	return ((sr & 0x0700) == 0);	/* return TRUE, if interrupts were enabled before */
+}
+
+void int_handler (struct pt_regs *fp)
+{
+	int vec;
+
+	vec = (fp->vector >> 2) & 0xff;
+	if (vec > 0x40)
+		vec -= 0x40;
+	else
+		return;
+
+	if (irq_vecs[vec].handler != NULL) {
+		irq_vecs[vec].handler (irq_vecs[vec].arg);
+	} else {
+		printf ("\nBogus External Interrupt Vector %d\n", vec);
+	}
+}
+#endif	/* CONFIG_MCFINTC */
\ No newline at end of file
diff --git a/lib_m68k/time.c b/lib_m68k/time.c
index 12e38f057..0e4efa473 100644
--- a/lib_m68k/time.c
+++ b/lib_m68k/time.c
@@ -46,13 +46,11 @@
 #include <asm/immap_5249.h>
 #endif
 
-
 static ulong timestamp;
 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 static unsigned short lastinc;
 #endif
 
-
 #if defined(CONFIG_M5272)
 /*
  * We use timer 3 which is running with a period of 1 us
@@ -293,6 +291,171 @@ void set_timer (ulong t)
 }
 #endif
 
+#if defined(CONFIG_MCFTMR)
+#ifndef CFG_UDELAY_BASE
+#	error	"uDelay base not defined!"
+#endif
+
+#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
+#	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
+#endif
+
+#include <asm/immap_5329.h>
+
+extern void dtimer_interrupt(void *not_used);
+extern void dtimer_interrupt_setup(void);
+extern void dtimer_interrupt_enable(void);
+
+void udelay(unsigned long usec)
+{
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_UDELAY_BASE);
+	uint start, now, tmp;
+
+	while (usec > 0) {
+		if (usec > 65000)
+			tmp = 65000;
+		else
+			tmp = usec;
+		usec = usec - tmp;
+
+		/* Set up TIMER 3 as timebase clock */
+		timerp->tmr = DTIM_DTMR_RST_RST;
+		timerp->tcn = 0;
+		/* set period to 1 us */
+		timerp->tmr =
+		    (((CFG_CLK / 1000000) -
+		      1) << 8) | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN;
+
+		start = now = timerp->tcn;
+		while (now < start + tmp)
+			now = timerp->tcn;
+	}
+}
+
+void dtimer_interrupt(void *not_used)
+{
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	/* check for timer interrupt asserted */
+	if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) {
+		timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
+		timestamp++;
+		return;
+	}
+}
+
+void timer_init(void)
+{
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
+	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+
+	timestamp = 0;
+
+	timerp->tcn = 0;
+	timerp->trr = 0;
+
+	/* Set up TIMER 4 as clock */
+	timerp->tmr = DTIM_DTMR_RST_RST;
+
+	/* initialize and enable timer 4 interrupt */
+	irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
+	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+
+	timerp->tcn = 0;
+	timerp->trr = 1000;	/* Interrupt every ms */
+
+	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+
+	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
+	timerp->tmr = CFG_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
+	    DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
+}
+
+void reset_timer(void)
+{
+	timestamp = 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return (timestamp - base);
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+#endif				/* CONFIG_MCFTMR */
+
+#if defined(CONFIG_MCFPIT)
+#if !defined(CFG_PIT_BASE)
+#	error	"CFG_PIT_BASE not defined!"
+#endif
+
+static unsigned short lastinc;
+
+void udelay(unsigned long usec)
+{
+	volatile pit_t *timerp = (pit_t *) (CFG_UDELAY_BASE);
+	uint tmp;
+
+	while (usec > 0) {
+		if (usec > 65000)
+			tmp = 65000;
+		else
+			tmp = usec;
+		usec = usec - tmp;
+
+		/* Set up TIMER 3 as timebase clock */
+		timerp->pcsr = PIT_PCSR_OVW;
+		timerp->pmr = 0;
+		/* set period to 1 us */
+		timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
+
+		timerp->pmr = tmp;
+		while (timerp->pcntr > 0) ;
+	}
+}
+
+void timer_init(void)
+{
+	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
+	timestamp = 0;
+
+	/* Set up TIMER 4 as poll clock */
+	timerp->pcsr = PIT_PCSR_OVW;
+	timerp->pmr = lastinc = 0;
+	timerp->pcsr |= PIT_PCSR_PRE(CFG_PIT_PRESCALE) | PIT_PCSR_EN;
+}
+
+void set_timer(ulong t)
+{
+	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
+
+	timestamp = 0;
+	timerp->pmr = lastinc = 0;
+}
+
+ulong get_timer(ulong base)
+{
+	unsigned short now, diff;
+	volatile pit_t *timerp = (pit_t *) (CFG_PIT_BASE);
+
+	now = timerp->pcntr;
+	diff = -(now - lastinc);
+
+	timestamp += diff;
+	lastinc = now;
+	return timestamp - base;
+}
+
+void wait_ticks(unsigned long ticks)
+{
+	set_timer(0);
+	while (get_timer(0) < ticks) ;
+}
+#endif				/* CONFIG_MCFPIT */
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
diff --git a/net/eth.c b/net/eth.c
index 0fc22115d..cefd30ff2 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -58,6 +58,7 @@ extern int npe_initialize(bd_t *);
 extern int uec_initialize(int);
 extern int bfin_EMAC_initialize(bd_t *);
 extern int atstk1000_eth_initialize(bd_t *);
+extern int mcffec_initialize(bd_t*);
 
 static struct eth_device *eth_devices, *eth_current;
 
diff --git a/rtc/Makefile b/rtc/Makefile
index 96c68c0ce..2e6f3bddd 100644
--- a/rtc/Makefile
+++ b/rtc/Makefile
@@ -31,7 +31,8 @@ COBJS	= date.o   \
 	  bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
 	  ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
 	  m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
-	  mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
+	  mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o \
+	  mcfrtc.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/rtc/mcfrtc.c b/rtc/mcfrtc.c
new file mode 100644
index 000000000..c7eb53fb4
--- /dev/null
+++ b/rtc/mcfrtc.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2007
+ * Freescale Semiconductor Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#include <asm/mcfrtc.h>
+
+#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#undef RTC_DEBUG
+
+#ifndef CFG_MCFRTC_BASE
+#error RTC_BASE is not defined!
+#endif
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+#define	STARTOFTIME		1970
+
+void rtc_get(struct rtc_time *tmp)
+{
+	volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+	int rtc_days, rtc_hrs, rtc_mins;
+	int tim;
+
+	rtc_days = rtc->days;
+	rtc_hrs = rtc->hourmin >> 8;
+	rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin);
+
+	tim = (rtc_days * 24) + rtc_hrs;
+	tim = (tim * 60) + rtc_mins;
+	tim = (tim * 60) + rtc->seconds;
+
+	to_tm(tim, tmp);
+
+	tmp->tm_yday = 0;
+	tmp->tm_isdst = 0;
+
+#ifdef RTC_DEBUG
+	printf("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+}
+
+void rtc_set(struct rtc_time *tmp)
+{
+	volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+	static int month_days[12] = {
+		31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+	};
+	int days, i, months;
+
+	if (tmp->tm_year > 2037) {
+		printf("Unable to handle. Exceeding integer limitation!\n");
+		tmp->tm_year = 2027;
+	}
+#ifdef RTC_DEBUG
+	printf("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+	/* calculate days by years */
+	for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) {
+		days += 365 + isleap(i);
+	}
+
+	/* calculate days by months */
+	months = tmp->tm_mon - 1;
+	for (i = 0; i < months; i++) {
+		days += month_days[i];
+
+		if (i == 1)
+			days += isleap(i);
+	}
+
+	days += tmp->tm_mday - 1;
+
+	rtc->days = days;
+	rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min;
+	rtc->seconds = tmp->tm_sec;
+}
+
+void rtc_reset(void)
+{
+	volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE);
+
+	if ((rtc->cr & RTC_CR_EN) == 0) {
+		printf("real-time-clock was stopped. Now starting...\n");
+		rtc->cr |= RTC_CR_EN;
+	}
+
+	rtc->cr |= RTC_CR_SWR;
+}
+
+#endif				/* CONFIG_MCFRTC && CFG_CMD_DATE */