Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
Patch by Steven Scholz, 02 Mar 2005
This commit is contained in:
Wolfgang Denk
parent
a188b5854f
commit
8e2be51de8
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@ -2,6 +2,9 @@
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Changes for U-Boot 1.1.4:
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======================================================================
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* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
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Patch by Steven Scholz, 02 Mar 2005
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* Fix typo in eth.c
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Patch by Ara Avanesyan, 24 Feb 2005
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@ -27,10 +27,11 @@
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typedef volatile unsigned int AT91_REG; /* Hardware register definition */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
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/* ***************************************************************************** */
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typedef struct _AT91S_TC {
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/******************************************************************************/
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typedef struct _AT91S_TC
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{
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AT91_REG TC_CCR; /* Channel Control Register */
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AT91_REG TC_CMR; /* Channel Mode Register */
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AT91_REG Reserved0[2]; /* */
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@ -42,7 +43,8 @@ typedef struct _AT91S_TC {
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AT91_REG TC_IER; /* Interrupt Enable Register */
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AT91_REG TC_IDR; /* Interrupt Disable Register */
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AT91_REG TC_IMR; /* Interrupt Mask Register */
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} AT91S_TC, *AT91PS_TC;
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}
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AT91S_TC, *AT91PS_TC;
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#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
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#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
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@ -59,10 +61,11 @@ typedef struct _AT91S_TC {
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#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
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#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Usart */
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/* ***************************************************************************** */
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typedef struct _AT91S_USART {
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/******************************************************************************/
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typedef struct _AT91S_USART
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{
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AT91_REG US_CR; /* Control Register */
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AT91_REG US_MR; /* Mode Register */
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AT91_REG US_IER; /* Interrupt Enable Register */
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@ -90,25 +93,30 @@ typedef struct _AT91S_USART {
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AT91_REG US_TNCR; /* Transmit Next Counter Register */
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AT91_REG US_PTCR; /* PDC Transfer Control Register */
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AT91_REG US_PTSR; /* PDC Transfer Status Register */
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} AT91S_USART, *AT91PS_USART;
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}
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AT91S_USART, *AT91PS_USART;
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/************************************************************************/
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
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/************************************************************************/
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typedef struct _AT91S_CKGR {
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/******************************************************************************/
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typedef struct _AT91S_CKGR
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{
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AT91_REG CKGR_MOR; /* Main Oscillator Register */
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AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
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AT91_REG CKGR_PLLAR; /* PLL A Register */
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AT91_REG CKGR_PLLBR; /* PLL B Register */
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} AT91S_CKGR, *AT91PS_CKGR;
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}
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AT91S_CKGR, *AT91PS_CKGR;
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/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
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#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
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#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
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#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
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/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
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#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
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#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
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/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
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#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
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#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
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@ -121,6 +129,7 @@ typedef struct _AT91S_CKGR {
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#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
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#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
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#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
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/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
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#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
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#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
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@ -135,10 +144,11 @@ typedef struct _AT91S_CKGR {
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#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
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#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
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/* ************************************************************************* */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
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/* ************************************************************************* */
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typedef struct _AT91S_PIO {
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/******************************************************************************/
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typedef struct _AT91S_PIO
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{
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AT91_REG PIO_PER; /* PIO Enable Register */
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AT91_REG PIO_PDR; /* PIO Disable Register */
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AT91_REG PIO_PSR; /* PIO Status Register */
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@ -174,13 +184,15 @@ typedef struct _AT91S_PIO {
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AT91_REG PIO_OWER; /* Output Write Enable Register */
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AT91_REG PIO_OWDR; /* Output Write Disable Register */
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AT91_REG PIO_OWSR; /* Output Write Status Register */
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} AT91S_PIO, *AT91PS_PIO;
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}
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AT91S_PIO, *AT91PS_PIO;
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Debug Unit */
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/* ***************************************************************************** */
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typedef struct _AT91S_DBGU {
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/******************************************************************************/
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typedef struct _AT91S_DBGU
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{
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AT91_REG DBGU_CR; /* Control Register */
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AT91_REG DBGU_MR; /* Mode Register */
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AT91_REG DBGU_IER; /* Interrupt Enable Register */
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@ -205,7 +217,8 @@ typedef struct _AT91S_DBGU {
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AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
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AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
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AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
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} AT91S_DBGU, *AT91PS_DBGU;
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}
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AT91S_DBGU, *AT91PS_DBGU;
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/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
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#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
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@ -234,12 +247,14 @@ typedef struct _AT91S_DBGU {
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#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
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#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
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/* ***************************************************************************** */
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typedef struct _AT91S_SMC2 {
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/******************************************************************************/
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typedef struct _AT91S_SMC2
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{
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AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
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} AT91S_SMC2, *AT91PS_SMC2;
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}
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AT91S_SMC2, *AT91PS_SMC2;
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/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
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#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
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@ -258,10 +273,11 @@ typedef struct _AT91S_SMC2 {
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#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
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#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Power Management Controler */
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/* ******************************************************************************/
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typedef struct _AT91S_PMC {
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/******************************************************************************/
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typedef struct _AT91S_PMC
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{
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AT91_REG PMC_SCER; /* System Clock Enable Register */
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AT91_REG PMC_SCDR; /* System Clock Disable Register */
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AT91_REG PMC_SCSR; /* System Clock Status Register */
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@ -277,8 +293,8 @@ typedef struct _AT91S_PMC {
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AT91_REG PMC_IDR; /* Interrupt Disable Register */
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AT91_REG PMC_SR; /* Status Register */
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AT91_REG PMC_IMR; /* Interrupt Mask Register */
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} AT91S_PMC, *AT91PS_PMC;
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}
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AT91S_PMC, *AT91PS_PMC;
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/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
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#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
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@ -332,10 +348,11 @@ typedef struct _AT91S_PMC {
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/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
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/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Ethernet MAC */
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/* ***************************************************************************** */
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typedef struct _AT91S_EMAC {
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/******************************************************************************/
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typedef struct _AT91S_EMAC
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{
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AT91_REG EMAC_CTL; /* Network Control Register */
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AT91_REG EMAC_CFG; /* Network Configuration Register */
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AT91_REG EMAC_SR; /* Network Status Register */
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@ -379,7 +396,8 @@ typedef struct _AT91S_EMAC {
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AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
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AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
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AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
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} AT91S_EMAC, *AT91PS_EMAC;
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}
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AT91S_EMAC, *AT91PS_EMAC;
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/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
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#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
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@ -391,6 +409,7 @@ typedef struct _AT91S_EMAC {
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#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
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#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
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#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
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/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
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#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
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#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
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@ -408,12 +427,15 @@ typedef struct _AT91S_EMAC {
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#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
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#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
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#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
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/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
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#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
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#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
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/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
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#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
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#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
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/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
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#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
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#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
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@ -422,10 +444,12 @@ typedef struct _AT91S_EMAC {
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#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
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#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
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#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
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/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
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#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
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#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
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#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
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/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
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#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
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#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
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@ -439,6 +463,7 @@ typedef struct _AT91S_EMAC {
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#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
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#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
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#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
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/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
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/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
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/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
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@ -454,10 +479,11 @@ typedef struct _AT91S_EMAC {
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#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
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#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
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/* ***************************************************************************** */
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typedef struct _AT91S_SPI {
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/******************************************************************************/
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typedef struct _AT91S_SPI
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{
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AT91_REG SPI_CR; /* Control Register */
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AT91_REG SPI_MR; /* Mode Register */
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AT91_REG SPI_RDR; /* Receive Data Register */
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@ -479,12 +505,14 @@ typedef struct _AT91S_SPI {
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AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
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AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
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AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
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} AT91S_SPI, *AT91PS_SPI;
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}
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AT91S_SPI, *AT91PS_SPI;
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/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
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#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
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#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
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#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
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/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
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#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
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#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
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@ -496,12 +524,15 @@ typedef struct _AT91S_SPI {
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#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
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#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
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#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
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/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
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#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
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#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
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/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
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#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
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#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
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/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
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#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
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#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
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@ -512,6 +543,7 @@ typedef struct _AT91S_SPI {
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#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
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#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
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#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
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/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
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/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
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/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
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@ -532,10 +564,11 @@ typedef struct _AT91S_SPI {
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#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
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#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
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/* ***************************************************************************** */
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/******************************************************************************/
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/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
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/* ***************************************************************************** */
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typedef struct _AT91S_PDC {
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/******************************************************************************/
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typedef struct _AT91S_PDC
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{
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AT91_REG PDC_RPR; /* Receive Pointer Register */
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AT91_REG PDC_RCR; /* Receive Counter Register */
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AT91_REG PDC_TPR; /* Transmit Pointer Register */
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@ -546,7 +579,8 @@ typedef struct _AT91S_PDC {
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AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
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AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
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AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
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} AT91S_PDC, *AT91PS_PDC;
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}
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AT91S_PDC, *AT91PS_PDC;
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/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
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#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
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@ -643,7 +677,6 @@ typedef struct _AT91S_PDC {
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#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
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#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
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#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
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#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
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#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
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@ -665,10 +698,6 @@ typedef struct _AT91S_PDC {
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#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
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#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
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#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB7 */
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#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB7 */
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#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB7 */
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#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB7 */
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#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
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#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
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#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
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Reference in New Issue