From 6fbf261f8df294e589cfadebebe5468e3c0f29e9 Mon Sep 17 00:00:00 2001
From: Xie Xiaobo <r63061@freescale.com>
Date: Fri, 9 Mar 2007 19:08:25 +0800
Subject: [PATCH 01/38] Fix two bugs for MPC83xx DDR2 controller SPD Init

There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
---
 cpu/mpc83xx/spd_sdram.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index d9b8753ca..41a1f1fc7 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -58,8 +58,8 @@ picos_to_clk(int picos)
 	int clks;
 
 	ddr_bus_clk = gd->ddr_clk >> 1;
-	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+	clks = picos / (1000000000 / (ddr_bus_clk / 1000));
+	if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
 		clks++;
 
 	return clks;
@@ -624,7 +624,7 @@ long int spd_sdram()
 			 | (1 << (16 + 10))             /* DQS Differential disable */
 			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
 			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
-			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
 			 | (caslat << 4)                /* caslat */
 			 | (burstlen << 0)              /* Burst length */
 			);

From 9d1d6a34d26c5933bc097ce73c9348f95573cdd4 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 20:53:31 +0200
Subject: [PATCH 02/38] Change ML401 parameters - Xilinx BSP

---
 board/xilinx/ml401/config.mk     |  2 +-
 board/xilinx/ml401/xparameters.h | 24 ++++++++++++------------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/ml401/config.mk
index 807f169fa..c75daaf0b 100644
--- a/board/xilinx/ml401/config.mk
+++ b/board/xilinx/ml401/config.mk
@@ -25,7 +25,7 @@
 # Version: Xilinx EDK 6.3 EDK_Gmm.12.3
 #
 
-TEXT_BASE = 0x12000000
+TEXT_BASE = 0x29000000
 
 PLATFORM_CPPFLAGS += -mno-xl-soft-mul
 PLATFORM_CPPFLAGS += -mno-xl-soft-div
diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 18d24f9c1..4fe36f8a9 100644
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -27,41 +27,41 @@
  */
 
 /* System Clock Frequency */
-#define XILINX_CLOCK_FREQ	66666667
+#define XILINX_CLOCK_FREQ	100000000
 
 /* Interrupt controller is intc_0 */
-#define XILINX_INTC_BASEADDR	0xd1000fc0
-#define XILINX_INTC_NUM_INTR_INPUTS	12
+#define XILINX_INTC_BASEADDR	0x41200000
+#define XILINX_INTC_NUM_INTR_INPUTS	4
 
 /* Timer pheriphery is opb_timer_0 */
-#define XILINX_TIMER_BASEADDR	0xa2000000
+#define XILINX_TIMER_BASEADDR	0x41c00000
 #define XILINX_TIMER_IRQ	0
 
 /* Uart pheriphery is console_uart */
-#define XILINX_UART_BASEADDR	0xa0000000
+#define XILINX_UART_BASEADDR	0x40600000
 #define XILINX_UART_BAUDRATE	115200
 
 /* GPIO is opb_gpio_0*/
 #define XILINX_GPIO_BASEADDR	0x90000000
 
 /* Flash Memory is opb_emc_0 */
-#define XILINX_FLASH_START	0x28000000
+#define XILINX_FLASH_START	0x2c000000
 #define XILINX_FLASH_SIZE	0x00800000
 
 /* Main Memory is plb_ddr_0 */
-#define XILINX_RAM_START	0x10000000
-#define XILINX_RAM_SIZE	0x10000000
+#define XILINX_RAM_START	0x28000000
+#define XILINX_RAM_SIZE	0x04000000
 
 /* Sysace Controller is opb_sysace_0 */
-#define XILINX_SYSACE_BASEADDR	0xCF000000
-#define XILINX_SYSACE_HIGHADDR	0xCF0001FF
+#define XILINX_SYSACE_BASEADDR	0x41800000
+#define XILINX_SYSACE_HIGHADDR	0x4180FFFF
 #define XILINX_SYSACE_MEM_WIDTH	16
 
 /* Ethernet controller is opb_ethernet_0 */
 #define XPAR_XEMAC_NUM_INSTANCES	1
 #define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
-#define XPAR_OPB_ETHERNET_0_BASEADDR	0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x60003FFF
+#define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0fFFF
 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
 #define XPAR_OPB_ETHERNET_0_MII_EXIST	1

From 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:02:40 +0200
Subject: [PATCH 03/38] 16bit read/write little endian

---
 cpu/microblaze/start.S | 33 +++++++++++++++++++++++++++++++++
 include/common.h       |  4 ++++
 2 files changed, 37 insertions(+)

diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 29481af9a..453815818 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -117,3 +117,36 @@ clear_bss:
 3:	/* jumping to board_init */
 	brai	board_init
 1:	bri	1b
+
+/*
+ * Read 16bit little endian
+ */
+	.text
+	.global	in16
+	.ent	in16
+	.align	2
+in16:	lhu	r3, r0, r5
+	bslli	r4, r3, 8
+	bsrli	r3, r3, 8
+	andi	r4, r4, 0xffff
+	or	r3, r3, r4
+	rtsd	r15, 8
+	sext16	r3, r3
+	.end	in16
+
+/*
+ * Write 16bit little endian
+ * first parameter(r5) - address, second(r6) - short value
+ */
+	.text
+	.global	out16
+	.ent	out16
+	.align	2
+out16:	bslli	r3, r6, 8
+	bsrli	r6, r6, 8
+	andi	r3, r3, 0xffff
+	or	r3, r3, r6
+	sh	r3, r0, r5
+	rtsd	r15, 8
+	or	r0, r0, r0
+	.end	out16
diff --git a/include/common.h b/include/common.h
index b162dbd7c..40fbba532 100644
--- a/include/common.h
+++ b/include/common.h
@@ -402,6 +402,10 @@ void		ppcDcbi(unsigned long value);
 void		ppcSync(void);
 void		ppcDcbz(unsigned long value);
 #endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short	in16(unsigned int);
+void		out16(unsigned int, unsigned short value);
+#endif
 
 #if defined (CONFIG_MPC83XX)
 void		ppcDWload(unsigned int *addr, unsigned int *ret);

From 32556443840f127170e4baa8bdd5b567039f6c36 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:07:22 +0200
Subject: [PATCH 04/38] [PATCH] SystemACE support for Microblaze

---
 drivers/systemace.c      |  6 ++++++
 include/configs/ml401.h  | 26 +++++++++++++++++---------
 include/configs/xupv2p.h | 14 ++++++++------
 3 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/systemace.c b/drivers/systemace.c
index 3848d9c59..c9fd5f167 100644
--- a/drivers/systemace.c
+++ b/drivers/systemace.c
@@ -211,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start,
 		/* Write sector count | ReadMemCardData. */
 		ace_writew((trans & 0xff) | 0x0300, 0x14);
 
+/* 
+ * For FPGA configuration via SystemACE is reset unacceptable
+ * CFGDONE bit in STATUSREG is not set to 1.
+ */
+#ifndef SYSTEMACE_CONFIG_FPGA
 		/* Reset the configruation controller */
 		val = ace_readw(0x18);
 		val |= 0x0080;
 		ace_writew(val, 0x18);
+#endif
 
 		retry = trans * 16;
 		while (retry > 0) {
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f4a8a1f22..15c2fe7ec 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -36,7 +36,7 @@
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 /* setting reset address */
-#define	CFG_RESET_ADDRESS	TEXT_BASE
+//#define	CFG_RESET_ADDRESS	TEXT_BASE
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
@@ -66,7 +66,7 @@
  *
  * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
  * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
- * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 
+ * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
  *
  * 0x1000_0000	CFG_SDRAM_BASE
  *					FREE
@@ -93,7 +93,8 @@
 
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 
 
 /* monitor code */
 #define	SIZE			0x40000
@@ -152,6 +153,8 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -174,6 +177,8 @@
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING |\
 				CFG_CMD_ENV |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_SAVES \
 				)
 
@@ -189,6 +194,8 @@
 				CFG_CMD_BDI |\
 				CFG_CMD_RUN |\
 				CFG_CMD_LOADS |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_LOADB |\
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
@@ -221,10 +228,11 @@
 #define CFG_HZ	1000
 
 /* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index 224db5c8b..c89ef7ce5 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -132,6 +132,8 @@
 			CFG_CMD_LOADS |\
 			CFG_CMD_LOADB |\
 			CFG_CMD_MISC |\
+			CFG_CMD_FAT |\
+			CFG_CMD_EXT2 |\
 			CFG_CMD_PING \
 			)
 
@@ -163,12 +165,12 @@
 	"base 0;" \
 	"echo"
 
-
 /* system ace */
-/*#define	CONFIG_SYSTEMACE
-#define	DEBUG_SYSTEMACE
-#define	CFG_SYSTEMACE_BASE	0xCF000000
-#define	CFG_SYSTEMACE_WIDTH	16
-#define	CONFIG_DOS_PARTITION*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
 
 #endif	/* __CONFIG_H */

From d87c57b201b4572d16f1b642998faa00c9912b16 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:31:55 -0500
Subject: [PATCH 05/38] mpc83xx: Add register definitions for MPC831x.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 include/asm-ppc/immap_83xx.h |  56 +++++++-
 include/mpc83xx.h            | 252 ++++++++++++++++++++++++++++++++++-
 2 files changed, 301 insertions(+), 7 deletions(-)

diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 5e088d67d..0de93385f 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -206,7 +206,9 @@ typedef struct pmc83xx {
 	u32 pmccr;		/* PMC Configuration Register */
 	u32 pmcer;		/* PMC Event Register */
 	u32 pmcmr;		/* PMC Mask Register */
-	u8 res0[0xF4];
+	u32 pmccr1;		/* PMC Configuration Register 1 */
+	u32 pmccr2;		/* PMC Configuration Register 2 */
+	u8 res0[0xEC];
 } pmc83xx_t;
 
 /*
@@ -355,7 +357,8 @@ typedef struct lbus83xx {
 	u8 res2[0x8];
 	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
 	u32 mdr;		/* UPM Data Register */
-	u8 res3[0x8];
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation Register */
 	u32 lsdmr;		/* SDRAM Mode Register */
 	u8 res4[0x8];
 	u32 lurt;		/* UPM Refresh Timer */
@@ -369,8 +372,14 @@ typedef struct lbus83xx {
 	u8 res6[0xC];
 	u32 lbcr;		/* Configuration Register */
 	u32 lcrr;		/* Clock Ratio Register */
-	u8 res7[0x28];
-	u8 res8[0xF00];
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
 } lbus83xx_t;
 
 /*
@@ -527,7 +536,7 @@ typedef struct pcictrl83xx {
  * USB
  */
 typedef struct usb83xx {
-	u8 fixme[0x2000];
+	u8 fixme[0x1000];
 } usb83xx_t;
 
 /*
@@ -574,7 +583,42 @@ typedef struct immap {
 	ios83xx_t		ios;		/* Sequencer */
 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
 	u8			res5[0x19900];
-	usb83xx_t		usb;
+	usb83xx_t		usb[2];
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_MPC831X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res0[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res3[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x1aa00];
+	usb83xx_t		usb[1];
 	tsec83xx_t		tsec[2];
 	u8			res6[0xA000];
 	security83xx_t		security;
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c2a4ff587..16b6c62f0 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -95,6 +95,11 @@
 #define SPR_8321E_REV11			0x80660011
 #define SPR_8321_REV11			0x80670011
 
+#define SPR_8311_REV10			0x80B30010
+#define SPR_8311E_REV10			0x80B20010
+#define SPR_8313_REV10			0x80B10010
+#define SPR_8313E_REV10			0x80B00010
+
 /* SPCR - System Priority Configuration Register
  */
 #define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
@@ -121,6 +126,15 @@
 #define SPCR_TSEC2BDP_SHIFT		(31-29)
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
+
+#elif defined(CONFIG_MPC831X)
+/* SPCR bits - MPC831x specific */
+#define SPCR_TSECDP			0x00003000	/* TSEC data priority */
+#define SPCR_TSECDP_SHIFT		(31-19)
+#define SPCR_TSECEP			0x00000C00	/* TSEC emergency priority */
+#define SPCR_TSECEP_SHIFT		(31-21)
+#define SPCR_TSECBDP			0x00000300	/* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP_SHIFT		(31-23)
 #endif
 
 /* SICRL/H - System I/O Configuration Register Low/High
@@ -195,6 +209,36 @@
 #define SICRL_PCI_MSRC			0x10000000
 #define SICRL_URT_CTPR			0x06000000
 #define SICRL_IRQ_CTPR			0x00C00000
+
+#elif defined(CONFIG_MPC831X)
+/* SICRL bits - MPC831x specific */
+#define SICRL_LBC			0x30000000
+#define SICRL_UART			0x0C000000
+#define SICRL_SPI_A			0x03000000
+#define SICRL_SPI_B			0x00C00000
+#define SICRL_SPI_C			0x00300000
+#define SICRL_SPI_D			0x000C0000
+#define SICRL_USBDR			0x00000C00
+#define SICRL_ETSEC1_A			0x0000000C
+#define SICRL_ETSEC2_A			0x00000003
+
+/* SICRH bits - MPC831x specific */
+#define SICRH_INTR_A			0x02000000
+#define SICRH_INTR_B			0x00C00000
+#define SICRH_IIC			0x00300000
+#define SICRH_ETSEC2_B			0x000C0000
+#define SICRH_ETSEC2_C			0x00030000
+#define SICRH_ETSEC2_D			0x0000C000
+#define SICRH_ETSEC2_E			0x00003000
+#define SICRH_ETSEC2_F			0x00000C00
+#define SICRH_ETSEC2_G			0x00000300
+#define SICRH_ETSEC1_B			0x00000080
+#define SICRH_ETSEC1_C			0x00000060
+#define SICRH_GTX1_DLY			0x00000008
+#define SICRH_GTX2_DLY			0x00000004
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
 #endif
 
 /* SWCRR - System Watchdog Control Register
@@ -393,6 +437,28 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
+#if defined(CONFIG_MPC831X)
+#define HRCWH_ROM_LOC_NAND_SP_8BIT 	0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT 	0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
+
+#define HRCWH_RL_EXT_LEGACY		0x00000000
+#define HRCWH_RL_EXT_NAND		0x00040000
+
+#define HRCWH_TSEC1M_IN_MII		0x00000000
+#define HRCWH_TSEC1M_IN_RMII		0x00002000
+#define HRCWH_TSEC1M_IN_RGMII		0x00006000
+#define HRCWH_TSEC1M_IN_RTBI		0x0000A000
+#define HRCWH_TSEC1M_IN_SGMII		0x0000C000
+
+#define HRCWH_TSEC2M_IN_MII		0x00000000
+#define HRCWH_TSEC2M_IN_RMII		0x00000400
+#define HRCWH_TSEC2M_IN_RGMII		0x00000C00
+#define HRCWH_TSEC2M_IN_RTBI		0x00001400
+#define HRCWH_TSEC2M_IN_SGMII		0x00001800
+#endif
+
 #if defined(CONFIG_MPC834X)
 #define HRCWH_TSEC1M_IN_RGMII		0x00000000
 #define HRCWH_TSEC1M_IN_RTBI		0x00004000
@@ -523,6 +589,18 @@
 #define SCCR_TSEC2CM_1			0x10000000
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
+
+#elif defined(CONFIG_MPC831X)
+/* TSEC1 bits are for TSEC2 as well */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC1ON			0x20000000
+#define SCCR_TSEC2ON			0x10000000
+
 #endif
 
 #define SCCR_USBMPHCM			0x00c00000
@@ -556,6 +634,25 @@
 #define CSCONFIG_COL_BIT_10		0x00000002
 #define CSCONFIG_COL_BIT_11		0x00000003
 
+/* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+ */
+#define TIMING_CFG0_RWT			0xC0000000
+#define TIMING_CFG0_RWT_SHIFT		30
+#define TIMING_CFG0_WRT			0x30000000
+#define TIMING_CFG0_WRT_SHIFT		28
+#define TIMING_CFG0_RRT			0x0C000000
+#define TIMING_CFG0_RRT_SHIFT		26
+#define TIMING_CFG0_WWT			0x03000000
+#define TIMING_CFG0_WWT_SHIFT		24
+#define TIMING_CFG0_ACT_PD_EXIT		0x00700000
+#define TIMING_CFG0_ACT_PD_EXIT_SHIFT	20
+#define TIMING_CFG0_PRE_PD_EXIT		0x00070000
+#define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
+#define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
+#define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
+#define TIMING_CFG0_MRS_CYC		0x00000F00
+#define TIMING_CFG0_MRS_CYC_SHIFT	0
+
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
  */
 #define TIMING_CFG1_PRETOACT		0x70000000
@@ -586,6 +683,17 @@
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
 #define TIMING_CFG2_CPO_DEF		0x00000000	/* default (= CASLAT + 1) */
 
+#define TIMING_CFG2_ADD_LAT		0x70000000
+#define TIMING_CFG2_ADD_LAT_SHIFT	28
+#define TIMING_CFG2_WR_LAT_DELAY	0x00380000
+#define TIMING_CFG2_WR_LAT_DELAY_SHIFT	19
+#define TIMING_CFG2_RD_TO_PRE		0x0000E000
+#define TIMING_CFG2_RD_TO_PRE_SHIFT	13
+#define TIMING_CFG2_CKE_PLS		0x000001C0
+#define TIMING_CFG2_CKE_PLS_SHIFT	6
+#define TIMING_CFG2_FOUR_ACT		0x0000003F
+#define TIMING_CFG2_FOUR_ACT_SHIFT	0
+
 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  */
 #define SDRAM_CFG_MEM_EN		0x80000000
@@ -593,13 +701,14 @@
 #define SDRAM_CFG_ECC_EN		0x20000000
 #define SDRAM_CFG_RD_EN			0x10000000
 #define SDRAM_CFG_SDRAM_TYPE		0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
 #define SDRAM_CFG_32_BE			0x00080000
 #define SDRAM_CFG_8_BE			0x00040000
 #define SDRAM_CFG_NCAP			0x00020000
 #define SDRAM_CFG_2T_EN			0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
+#define SDRAM_CFG_BI			0x00000001
 
 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
  */
@@ -732,11 +841,15 @@
 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
 #define BR_DECC				0x00000600
 #define BR_DECC_SHIFT			9
+#define BR_DECC_OFF			0x00000000
+#define BR_DECC_CHK			0x00000200
+#define BR_DECC_CHK_GEN			0x00000400
 #define BR_WP				0x00000100
 #define BR_WP_SHIFT			8
 #define BR_MSEL				0x000000E0
 #define BR_MSEL_SHIFT			5
 #define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_FCM			0x00000020	/* FCM */
 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
 #define BR_MS_UPMA			0x00000080	/* UPMA */
 #define BR_MS_UPMB			0x000000A0	/* UPMB */
@@ -803,6 +916,34 @@
 #define OR_GPCM_EAD			0x00000001
 #define OR_GPCM_EAD_SHIFT		0
 
+#define OR_FCM_AM			0xFFFF8000
+#define OR_FCM_AM_SHIFT				15
+#define OR_FCM_BCTLD			0x00001000
+#define OR_FCM_BCTLD_SHIFT			12
+#define OR_FCM_PGS			0x00000400
+#define OR_FCM_PGS_SHIFT			10
+#define OR_FCM_CSCT			0x00000200
+#define OR_FCM_CSCT_SHIFT			 9
+#define OR_FCM_CST			0x00000100
+#define OR_FCM_CST_SHIFT			 8
+#define OR_FCM_CHT			0x00000080
+#define OR_FCM_CHT_SHIFT			 7
+#define OR_FCM_SCY			0x00000070
+#define OR_FCM_SCY_SHIFT			 4
+#define OR_FCM_SCY_1			0x00000010
+#define OR_FCM_SCY_2			0x00000020
+#define OR_FCM_SCY_3			0x00000030
+#define OR_FCM_SCY_4			0x00000040
+#define OR_FCM_SCY_5			0x00000050
+#define OR_FCM_SCY_6			0x00000060
+#define OR_FCM_SCY_7			0x00000070
+#define OR_FCM_RST			0x00000008
+#define OR_FCM_RST_SHIFT			 3
+#define OR_FCM_TRLX			0x00000004
+#define OR_FCM_TRLX_SHIFT			 2
+#define OR_FCM_EHTR			0x00000002
+#define OR_FCM_EHTR_SHIFT			 1
+
 #define OR_UPM_AM			0xFFFF8000
 #define OR_UPM_AM_SHIFT			15
 #define OR_UPM_XAM			0x00006000
@@ -1019,4 +1160,113 @@
 #define PIWAR_IWS_1G			0x0000001D
 #define PIWAR_IWS_2G			0x0000001E
 
+/* PMCCR1 - PCI Configuration Register 1
+ */
+#define PMCCR1_POWER_OFF		0x00000020
+
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO		0x0000F000
+#define FMR_CWTO_SHIFT		12
+#define FMR_BOOT		0x00000800
+#define FMR_ECCM		0x00000100
+#define FMR_AL			0x00000030
+#define FMR_AL_SHIFT		4
+#define FMR_OP			0x00000003
+#define FMR_OP_SHIFT		0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0			0xF0000000
+#define FIR_OP0_SHIFT		28
+#define FIR_OP1			0x0F000000
+#define FIR_OP1_SHIFT		24
+#define FIR_OP2			0x00F00000
+#define FIR_OP2_SHIFT		20
+#define FIR_OP3			0x000F0000
+#define FIR_OP3_SHIFT		16
+#define FIR_OP4			0x0000F000
+#define FIR_OP4_SHIFT		12
+#define FIR_OP5			0x00000F00
+#define FIR_OP5_SHIFT		8
+#define FIR_OP6			0x000000F0
+#define FIR_OP6_SHIFT		4
+#define FIR_OP7			0x0000000F
+#define FIR_OP7_SHIFT		0
+#define FIR_OP_NOP		0x0 /* No operation and end of sequence */
+#define FIR_OP_CA		0x1 /* Issue current column address */
+#define FIR_OP_PA		0x2 /* Issue current block+page address */
+#define FIR_OP_UA		0x3 /* Issue user defined address */
+#define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0		0xFF000000
+#define FCR_CMD0_SHIFT		24
+#define FCR_CMD1		0x00FF0000
+#define FCR_CMD1_SHIFT		16
+#define FCR_CMD2		0x0000FF00
+#define FCR_CMD2_SHIFT   	8
+#define FCR_CMD3		0x000000FF
+#define FCR_CMD3_SHIFT		0
+
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK		0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI		0x00007C00
+#define FPAR_SP_PI_SHIFT	10
+#define FPAR_SP_MS		0x00000200
+#define FPAR_SP_CI		0x000001FF
+#define FPAR_SP_CI_SHIFT	0
+#define FPAR_LP_PI		0x0003F000
+#define FPAR_LP_PI_SHIFT	12
+#define FPAR_LP_MS		0x00000800
+#define FPAR_LP_CI		0x000007FF
+#define FPAR_LP_CI_SHIFT	0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM		0x80000000
+#define LTESR_FCT 		0x40000000
+#define LTESR_PAR 		0x20000000
+#define LTESR_WP		0x04000000
+#define LTESR_ATMW		0x00800000
+#define LTESR_ATMR		0x00400000
+#define LTESR_CS		0x00080000
+#define LTESR_CC		0x00000001
+
+/* DDR Control Driver Register
+ */
+#define DDRCDR_EN		0x40000000
+#define DDRCDR_PZ		0x3C000000
+#define DDRCDR_PZ_MAXZ		0x00000000
+#define DDRCDR_PZ_HIZ		0x20000000
+#define DDRCDR_PZ_NOMZ		0x30000000
+#define DDRCDR_PZ_LOZ		0x38000000
+#define DDRCDR_PZ_MINZ		0x3C000000
+#define DDRCDR_NZ		0x3C000000
+#define DDRCDR_NZ_MAXZ		0x00000000
+#define DDRCDR_NZ_HIZ		0x02000000
+#define DDRCDR_NZ_NOMZ		0x03000000
+#define DDRCDR_NZ_LOZ		0x03800000
+#define DDRCDR_NZ_MINZ		0x03C00000
+#define DDRCDR_ODT		0x00080000
+#define DDRCDR_DDR_CFG		0x00040000
+#define DDRCDR_M_ODR		0x00000002
+#define DDRCDR_Q_DRN		0x00000001
+
 #endif	/* __MPC83XX_H__ */

From a35b0c4950d84cf9e3a9e32b916135956d1ac636 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:15 -0500
Subject: [PATCH 06/38] mpc83xx: Recognize SPR values for MPC8311 and MPC8313.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index e934ba638..d569c4972 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -124,6 +124,18 @@ int checkcpu(void)
 	case SPR_8321_REV11:
 		puts("MPC8321, ");
 		break;
+	case SPR_8311_REV10:
+		puts("MPC8311, ");
+		break;
+	case SPR_8311E_REV10:
+		puts("MPC8311E, ");
+		break;
+	case SPR_8313_REV10:
+		puts("MPC8313, ");
+		break;
+	case SPR_8313E_REV10:
+		puts("MPC8313E, ");
+		break;
 	default:
 		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
 		return 0;

From 95e7ef897e54591e615fc1b458b74c286fe1fb06 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:16 -0500
Subject: [PATCH 07/38] mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update
 checkcpu().

Rather than misleadingly define PVR_83xx as the specific type of 83xx
being built for, the PVR of each core revision is defined. checkcpu() now
prints the core that it detects, rather than aborting if it doesn't find
what it thinks it wants.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/cpu.c      | 21 +++++++++++++++++----
 include/asm-ppc/e300.h | 16 +++-------------
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index d569c4972..332afaad9 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -52,13 +52,26 @@ int checkcpu(void)
 
 	immr = (immap_t *)CFG_IMMR;
 
-	if ((pvr & 0xFFFF0000) != PVR_83xx) {
-		puts("Not MPC83xx Family!!!\n");
-		return -1;
+	puts("CPU: ");
+
+	switch (pvr & 0xffff0000) {
+		case PVR_E300C1:
+			printf("e300c1, ");
+			break;
+
+		case PVR_E300C2:
+			printf("e300c2, ");
+			break;
+
+		case PVR_E300C3:
+			printf("e300c3, ");
+			break;
+
+		default:
+			printf("Unknown core, ");
 	}
 
 	spridr = immr->sysconf.spridr;
-	puts("CPU: ");
 	switch(spridr) {
 	case SPR_8349E_REV10:
 	case SPR_8349E_REV11:
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index ff9512f20..d1bb159ae 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -6,19 +6,9 @@
 #ifndef	__E300_H__
 #define __E300_H__
 
-/*
- * e300 Processor Version & Revision Numbers
- */
-#define PVR_83xx 0x80830000
-#define PVR_8349_REV10 (PVR_83xx | 0x0010)
-#define PVR_8349_REV11 (PVR_83xx | 0x0011)
-#define PVR_8360_REV10 (PVR_83xx | 0x0020)
-#define PVR_8360_REV11 (PVR_83xx | 0x0020)
-
-#if defined(CONFIG_MPC832X)
-#undef PVR_83xx
-#define PVR_83xx 0x80840000
-#endif
+#define PVR_E300C1	0x80830000
+#define PVR_E300C2	0x80840000
+#define PVR_E300C3	0x80850000
 
 /*
  * Hardware Implementation-Dependent Register 0 (HID0)

From 0f253283a32d91e06844d7f87f9b33f4f4fbce8f Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:18 -0500
Subject: [PATCH 08/38] mpc83xx: Add 831x support to global_data.h

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 include/asm-ppc/global_data.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 26bc875f8..cd2463643 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -55,11 +55,13 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined (CONFIG_MPC834X)
+#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 usbmph_clk;
 	u32 usbdr_clk;
+#endif
+#if defined (CONFIG_MPC834X)
+	u32 usbmph_clk;
 #endif /* CONFIG_MPC834X */
 	u32 core_clk;
 	u32 i2c1_clk;

From 7c98e5193e93df6b9b651851d54b638a61ebb0ea Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:19 -0500
Subject: [PATCH 09/38] mpc83xx: Add 831x support to speed.c.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/speed.c | 68 ++++++++++++++++++++++++++++-----------------
 1 file changed, 42 insertions(+), 26 deletions(-)

diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index c75993059..1a440310e 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,11 +99,13 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 usbmph_clk;
 	u32 usbdr_clk;
+#endif
+#ifdef CONFIG_MPC834X
+	u32 usbmph_clk;
 #endif
 	u32 core_clk;
 	u32 i2c1_clk;
@@ -148,7 +150,7 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -167,6 +169,26 @@ int get_clocks(void)
 		return -4;
 	}
 
+	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
+	case 0:
+		usbdr_clk = 0;
+		break;
+	case 1:
+		usbdr_clk = csb_clk;
+		break;
+	case 2:
+		usbdr_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbdr_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_USBDRCM value */
+		return -8;
+	}
+#endif
+
+#if defined(CONFIG_MPC834X)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -205,24 +227,6 @@ int get_clocks(void)
 		return -7;
 	}
 
-	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
-	case 0:
-		usbdr_clk = 0;
-		break;
-	case 1:
-		usbdr_clk = csb_clk;
-		break;
-	case 2:
-		usbdr_clk = csb_clk / 2;
-		break;
-	case 3:
-		usbdr_clk = csb_clk / 3;
-		break;
-	default:
-		/* unkown SCCR_USBDRCM value */
-		return -8;
-	}
-
 	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 		/* if USB MPH clock is not disabled and
 		 * USB DR clock is not disabled then
@@ -230,8 +234,16 @@ int get_clocks(void)
 		 */
 		return -9;
 	}
+#elif defined(CONFIG_MPC831X)
+	tsec2_clk = tsec1_clk;
+
+	if (!(sccr & SCCR_TSEC1ON))
+		tsec1_clk = 0;
+	if (!(sccr & SCCR_TSEC2ON))
+		tsec2_clk = 0;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+
+#if !defined(CONFIG_MPC834X)
 	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_MPC832X)
@@ -314,11 +326,13 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
-	gd->usbmph_clk = usbmph_clk;
 	gd->usbdr_clk = usbdr_clk;
+#endif
+#if defined(CONFIG_MPC834X)
+	gd->usbmph_clk = usbmph_clk;
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
@@ -371,11 +385,13 @@ int print_clock_conf(void)
 #if !defined(CONFIG_MPC832X)
 	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
 	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
-	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
 	printf("  USB DR:              %4d MHz\n", gd->usbdr_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC834X)
+	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
 #endif
 	return 0;
 }

From 49ea3b6eafe606285ae4d5c378026153dde53200 Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:34:21 -0500
Subject: [PATCH 10/38] mpc83xx: Add generic PCI setup code.

Board code can now request the generic setup code rather than having to
copy-and-paste it for themselves.  Boards should be converted to use this
once they're tested with it.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 cpu/mpc83xx/Makefile |   2 +-
 cpu/mpc83xx/pci.c    | 191 +++++++++++++++++++++++++++++++++++++++++++
 include/mpc83xx.h    |   5 ++
 3 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 cpu/mpc83xx/pci.c

diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 4b9dcc818..bb96f774f 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -29,7 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  spd_sdram.o qe_io.o
+	  spd_sdram.o qe_io.o pci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
new file mode 100644
index 000000000..2a2b0bd90
--- /dev/null
+++ b/cpu/mpc83xx/pci.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>,
+ * with some bits from older board-specific PCI initialization.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+
+#ifdef CONFIG_83XX_GENERIC_PCI
+#define MAX_BUSES 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_controller pci_hose[MAX_BUSES];
+static int pci_num_buses;
+
+static void pci_init_bus(int bus, struct pci_region *reg)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile pot83xx_t *pot = immr->ios.pot;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
+	struct pci_controller *hose = &pci_hose[bus];
+	u32 dev;
+	u16 reg16;
+	int i;
+
+	if (bus == 1)
+		pot += 3;
+
+	/* Setup outbound translation windows */
+	for (i = 0; i < 3; i++, reg++, pot++) {
+		if (reg->size == 0)
+			break;
+
+		hose->regions[i] = *reg;
+		hose->region_count++;
+
+		pot->potar = reg->bus_start >> 12;
+		pot->pobar = reg->phys_start >> 12;
+		pot->pocmr = ~(reg->size - 1) >> 12;
+
+		if (reg->flags & PCI_REGION_IO)
+			pot->pocmr |= POCMR_IO;
+#ifdef CONFIG_83XX_PCI_STREAMING
+		else if (reg->flags & PCI_REGION_PREFETCH)
+			pot->pocmr |= POCMR_SE;
+#endif
+
+		if (bus == 1)
+			pot->pocmr |= POCMR_DST;
+
+		pot->pocmr |= POCMR_EN;
+	}
+
+	/* Point inbound translation at RAM */
+	pci_ctrl->pitar1 = 0;
+	pci_ctrl->pibar1 = 0;
+	pci_ctrl->piebar1 = 0;
+	pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+	                   PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	i = hose->region_count++;
+	hose->regions[i].bus_start = 0;
+	hose->regions[i].phys_start = 0;
+	hose->regions[i].size = gd->ram_size;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
+	                         CFG_IMMR + 0x8304 + bus * 0x80);
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+/*
+ * The caller must have already set OCCR, and the PCI_LAW BARs
+ * must have been set to cover all of the requested regions.
+ *
+ * If fewer than three regions are requested, then the region
+ * list is terminated with a region of size 0.
+ */
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	int i;
+
+	if (num_buses > MAX_BUSES) {
+		printf("%d PCI buses requsted, %d supported\n",
+		       num_buses, MAX_BUSES);
+
+		num_buses = MAX_BUSES;
+	}
+
+	pci_num_buses = num_buses;
+
+	/*
+	 * Release PCI RST Output signal.
+	 * Power on to RST high must be at least 100 ms as per PCI spec.
+	 * On warm boots only 1 ms is required.
+	 */
+	udelay(warmboot ? 1000 : 100000);
+
+	for (i = 0; i < num_buses; i++)
+		immr->pci_ctrl[i].gcr = 1;
+
+	/*
+	 * RST high to first config access must be at least 2^25 cycles
+	 * as per PCI spec.  This could be cut in half if we know we're
+	 * running at 66MHz.  This could be insufficiently long if we're
+	 * running the PCI bus at significantly less than 33MHz.
+	 */
+	udelay(1020000);
+
+	for (i = 0; i < num_buses; i++)
+		pci_init_bus(i, reg[i]);
+}
+
+#ifdef CONFIG_OF_FLAT_TREE
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	if (pci_num_buses < 1)
+		return;
+
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+	if (p) {
+		p[0] = pci_hose[0].first_busno;
+		p[1] = pci_hose[0].last_busno;
+	}
+
+	if (pci_num_buses < 2)
+		return;
+
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+	if (p) {
+		p[0] = pci_hose[1].first_busno;
+		p[1] = pci_hose[1].last_busno;
+	}
+}
+#endif /* CONFIG_OF_FLAT_TREE */
+
+#endif /* CONFIG_83XX_GENERIC_PCI */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 16b6c62f0..60fc214b3 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1269,4 +1269,9 @@
 #define DDRCDR_M_ODR		0x00000002
 #define DDRCDR_Q_DRN		0x00000001
 
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
+#endif
+
 #endif	/* __MPC83XX_H__ */

From 96b8a05432f346f36493535c85320b70ec9c7c1b Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:54:15 -0500
Subject: [PATCH 11/38] mpc83xx: Add MPC8313ERDB support.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Makefile                        |  13 +
 board/mpc8313erdb/Makefile      |  50 +++
 board/mpc8313erdb/config.mk     |   1 +
 board/mpc8313erdb/mpc8313erdb.c | 116 +++++++
 board/mpc8313erdb/sdram.c       | 133 ++++++++
 board/mpc8313erdb/u-boot.lds    | 123 +++++++
 doc/README.mpc8313erdb          |  83 +++++
 include/configs/MPC8313ERDB.h   | 569 ++++++++++++++++++++++++++++++++
 8 files changed, 1088 insertions(+)
 create mode 100644 board/mpc8313erdb/Makefile
 create mode 100644 board/mpc8313erdb/config.mk
 create mode 100644 board/mpc8313erdb/mpc8313erdb.c
 create mode 100644 board/mpc8313erdb/sdram.c
 create mode 100644 board/mpc8313erdb/u-boot.lds
 create mode 100644 doc/README.mpc8313erdb
 create mode 100644 include/configs/MPC8313ERDB.h

diff --git a/Makefile b/Makefile
index 94cda54c7..0b0c0d00e 100644
--- a/Makefile
+++ b/Makefile
@@ -1689,6 +1689,19 @@ MPC8360EMDS_SLAVE_config:	unconfig
 	fi ;
 	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
 
+MPC8313ERDB_33_config \
+MPC8313ERDB_66_config: unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "...33M ..." ; \
+		echo "#define CFG_33MHZ" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _66_,$@)" ] ; then \
+		echo -n "...66M..." ; \
+		echo "#define CFG_66MHZ" >>include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
 
diff --git a/board/mpc8313erdb/Makefile b/board/mpc8313erdb/Makefile
new file mode 100644
index 000000000..a987e510d
--- /dev/null
+++ b/board/mpc8313erdb/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mpc8313erdb/config.mk b/board/mpc8313erdb/config.mk
new file mode 100644
index 000000000..f76826495
--- /dev/null
+++ b/board/mpc8313erdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/mpc8313erdb/mpc8313erdb.c
new file mode 100644
index 000000000..999fe9e39
--- /dev/null
+++ b/board/mpc8313erdb/mpc8313erdb.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ft_build.h>
+#include <pci.h>
+#include <mpc83xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+#ifndef CFG_8313ERDB_BROKEN_PMC
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8313ERDB\n");
+	return 0;
+}
+
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CFG_PCI1_MEM_BASE,
+		phys_start: CFG_PCI1_MEM_PHYS,
+		size: CFG_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CFG_PCI1_MMIO_BASE,
+		phys_start: CFG_PCI1_MMIO_PHYS,
+		size: CFG_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CFG_PCI1_IO_BASE,
+		phys_start: CFG_PCI1_IO_PHYS,
+		size: CFG_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+	int warmboot;
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	clk->occr |= 0xe0000000;
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
+#ifndef CFG_8313ERDB_BROKEN_PMC
+	warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
+#endif
+
+	mpc83xx_pci_init(1, reg, warmboot);
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c
new file mode 100644
index 000000000..4b6778837
--- /dev/null
+++ b/board/mpc8313erdb/sdram.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+#ifndef CFG_8313ERDB_BROKEN_PMC
+static void resume_from_sleep(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+#endif
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+
+	/* Currently we use only one CS, so disable the other bank. */
+	im->ddr.cs_config[1] = 0;
+
+	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+
+#ifndef CFG_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI;
+	else
+#endif
+		im->ddr.sdram_cfg = CFG_SDRAM_CFG;
+
+	im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_DDR_MODE_2;
+
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	sync();
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile lbus83xx_t *lbc = &im->lbus;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	puts("Initializing\n");
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	sync();
+
+#ifndef CFG_8313ERDB_BROKEN_PMC
+	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+#endif
+
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/board/mpc8313erdb/u-boot.lds b/board/mpc8313erdb/u-boot.lds
new file mode 100644
index 000000000..937c87a27
--- /dev/null
+++ b/board/mpc8313erdb/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/doc/README.mpc8313erdb b/doc/README.mpc8313erdb
new file mode 100644
index 000000000..7ad4cc76c
--- /dev/null
+++ b/doc/README.mpc8313erdb
@@ -0,0 +1,83 @@
+Freescale MPC8313ERDB Board
+-----------------------------------------
+
+1.	Board Switches and Jumpers
+
+	SW3 is used to set CFG_RESET_SOURCE.
+
+	To boot the image at 0xFE000000 in NOR flash, use these DIP
+	switche settings for SW3 SW4:
+
+	+------+	+------+
+	|      |	| **** |
+	| **** |	|      |
+	+------+ ON	+------+ ON
+	  4321		  4321
+	(where the '*' indicates the position of the tab of the switch.)
+
+2.	Memory Map
+	The memory map looks like this:
+
+	0x0000_0000	0x07ff_ffff	DDR		 128M
+	0x8000_0000	0x8fff_ffff	PCI MEM		 256M
+	0x9000_0000	0x9fff_ffff	PCI_MMIO	 256M
+	0xe000_0000	0xe00f_ffff	IMMR		 1M
+	0xe200_0000	0xe20f_ffff	PCI IO	 	 16M
+	0xe280_0000	0xe280_7fff	NAND FLASH (CS1) 32K
+	0xf000_0000	0xf001_ffff	VSC7385 (CS2)	 128K
+	0xfa00_0000	0xfa00_7fff	Board Status/	 32K
+					LED Control (CS3)
+	0xfe00_0000	0xfe7f_ffff	NOR FLASH (CS0)	 8M
+
+3.	Definitions
+
+3.1	Explanation of NEW definitions in:
+
+	include/configs/MPC8313ERDB.h
+
+	CONFIG_MPC83xx		MPC83xx family
+	CONFIG_MPC831x		MPC831x specific
+	CONFIG_MPC8313ERDB	MPC8313ERDB board specific
+
+4.	Compilation
+
+	Assuming you're using BASH (or similar) as your shell:
+
+	export CROSS_COMPILE=your-cross-compiler-prefix-
+	make distclean
+	make MPC8313ERDB_33_config
+	(or make MPC8313ERDB_66_config, depending on the speed of
+	 the oscillator on your board)
+	make
+
+5.	Downloading and Flashing Images
+
+5.1	Reflash U-boot Image using U-boot
+
+	=>run tftpflash
+
+	You may want to try
+	=>tftpboot $loadaddr $uboot
+	first, to make sure that the TFTP load will succeed before it
+	goes ahead and wipes out your current firmware.  And of course,
+	have an alternate means of programming the flash available
+	if the new u-boot doesn't boot.
+
+5.2	Downloading and Booting Linux Kernel
+
+	Ensure that all networking-related environment variables are set
+	properly (including ipaddr, serverip, gatewayip (if needed),
+	netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+	fdtfile, and bootfile).
+
+	Then, do one of the following, depending on whether you
+	want an NFS root or a ramdisk root:
+
+	=>run nfsboot
+	or
+	=>run ramboot
+
+6	Notes
+
+	Booting from NAND flash is not yet supported.
+	The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
new file mode 100644
index 000000000..2519c6b8b
--- /dev/null
+++ b/include/configs/MPC8313ERDB.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
+ *           Initialized
+ * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
+ *           Code Cleanup
+ * 20070410: Scott Wood <scottwood@freescale.com>
+ *           More cleanup
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC83XX		1
+#define CONFIG_MPC831X		1
+#define CONFIG_MPC8313		1
+#define CONFIG_MPC8313ERDB	1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef CFG_66MHZ
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#elif defined(CFG_33MHZ)
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CFG_IMMR		0xE0000000
+
+#define CFG_MEMTEST_START	0x00001000
+#define CFG_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CFG_8313ERDB_BROKEN_PMC 1
+
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CFG_DDR_SIZE		128		/* MB */
+#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
+				| 0x00040000 /* TODO */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				/* 0x80840102 */
+
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x3935d322 */
+#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x0f9048ca */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03200064 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_2T_EN \
+				| SDRAM_CFG_DBW_32 )
+#else
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
+#endif
+#define CFG_SDRAM_CFG2		0x00401000;
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44400232 */
+#define CFG_DDR_MODE_2		0x8000C000;
+
+#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR )
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |    /* flash Base address */ \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V)		     /* valid */
+#define CFG_OR0_PRELIM		( 0xFF000000         /* 16 MByte */ \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD )
+				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	135		/* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_2	/* 0x00010002 */
+#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
+			| (0xFF << LBCR_BMT_SHIFT) \
+			| 0xF )	/* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#define CFG_NAND_BASE		0xE2800000 /* 0xF0000000 */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8            /* Port Size = 8 bit */ \
+				| BR_MS_FCM          /* MSEL = FCM */ \
+				| BR_V )             /* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000	/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#define CFG_VSC7385_BASE	0xF0000000
+
+#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
+#define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
+
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8313@0"
+#define OF_SOC			"soc8313@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8313@e0000000/serial@4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI		1
+#endif
+
+#define CONFIG_GMII			1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1		1
+
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2		1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR			0x1c
+#define TSEC2_PHY_ADDR			4
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#define CFG_BASE_COMMANDS	( CONFIG_CMD_DFL	\
+				| CFG_CMD_PING		\
+				| CFG_CMD_DHCP		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_PCI)
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CFG_RAMBOOT_COMMANDS	(CFG_BASE_COMMANDS & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+
+#if defined(CFG_RAMBOOT)
+#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
+#else
+#define CONFIG_COMMANDS CFG_BASE_COMMANDS
+#endif
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#ifdef CFG_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#elif defined(CFG_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#endif
+
+/* 0xa0606c00 */
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB Phy  */
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+                         HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR		00:E0:0C:00:95:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+
+#define CONFIG_IPADDR		10.0.0.2
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_NETDEV		eth1
+
+#define CONFIG_HOSTNAME		mpc8313erdb
+#define CONFIG_ROOTPATH		/nfs/root/path
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE		mpc8313erdb.dtb
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"ethprime=TSEC1\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
+	"tftpflash=tftpboot $loadaddr $uboot; " 			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"fdtaddr=400000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"							\
+	"run setipargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */

From 144876a380f5756f57412caf74c1d6dc201dd796 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 24 Apr 2007 23:01:02 +0200
Subject: [PATCH 12/38] [PATCH] MTD partition support, JFFS2 support

---
 fs/jffs2/compr_zlib.c   |  2 +-
 include/configs/ml401.h | 29 +++++++++++++++++++++++++++--
 include/linux/stat.h    |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c
index 1b35585ee..d88d0f8f3 100644
--- a/fs/jffs2/compr_zlib.c
+++ b/fs/jffs2/compr_zlib.c
@@ -45,7 +45,7 @@
 long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
 		      __u32 srclen, __u32 destlen)
 {
-    return (decompress_block(cpage_out, data_in + 2, ldr_memcpy));
+    return (decompress_block(cpage_out, data_in + 2, (void *) ldr_memcpy));
 
 }
 
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 15c2fe7ec..acaa1e4f2 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -40,7 +40,7 @@
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
-#define XPAR_EMAC_0_DEVICE_ID	XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID	XPAR_OPB_ETHERNET_0_DEVICE_ID
 
 /* gpio */
 #define	CFG_GPIO_0		1
@@ -118,6 +118,7 @@
 	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
 	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
 	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 
 	#ifdef	RAMENV
 		#define	CFG_ENV_IS_NOWHERE	1
@@ -136,6 +137,7 @@
 	#define	CFG_ENV_IS_NOWHERE	1
 	#define	CFG_ENV_SIZE		0x1000
 	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 #endif /* !FLASH */
 
 #ifdef	FLASH
@@ -155,6 +157,8 @@
 				CFG_CMD_CACHE |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -179,6 +183,8 @@
 				CFG_CMD_ENV |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +212,17 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
+#define MTDIDS_DEFAULT		"nor0=ml401-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
+				"256k(env),3m(kernel),1m(romfs),"\
+				"1m(cramfs),-(jffs2)"
+#endif
+
 /* Miscellaneous configurable options */
 #define	CFG_PROMPT	"U-Boot-mONStR> "
 #define	CFG_CBSIZE	512	/* size of console buffer */
@@ -214,7 +231,7 @@
 #define	CFG_LONGHELP
 #define	CFG_LOAD_ADDR	0x12000000 /* default load address */
 
-#define	CONFIG_BOOTDELAY 	30
+#define	CONFIG_BOOTDELAY	30
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		"ml401"
 #define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
@@ -235,4 +252,12 @@
 #define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
 #define	CONFIG_DOS_PARTITION
 
+#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
+					"nor0=ml401-0\0"\
+					"mtdparts=mtdparts=ml401-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"
+
 #endif	/* __CONFIG_H */
diff --git a/include/linux/stat.h b/include/linux/stat.h
index f9422cb1f..39386f122 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,8 @@ struct stat {
 
 #endif	/* __PPC__ */
 
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) ||\
+	defined (__microblaze__)
 
 struct stat {
 	unsigned short st_dev;

From 5c5d3242935cf3543af01142627494434834cf98 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Wed, 25 Apr 2007 12:34:38 -0500
Subject: [PATCH 13/38] mpc83xx: minor fixups for 8313rdb introduction

---
 MAKEALL                       |  4 ++--
 Makefile                      | 26 +++++++++++++-------------
 cpu/mpc83xx/pci.c             |  1 +
 include/configs/MPC8313ERDB.h |  4 ++--
 4 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index 0f0ec296f..a6b93b3c5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -132,8 +132,8 @@ LIST_8260="	\
 #########################################################################
 
 LIST_83xx="	\
-	MPC832XEMDS	MPC8349EMDS	MPC8349ITX	MPC8349ITXGP	\
-	MPC8360EMDS	sbc8349		TQM834x				\
+	MPC8313ERDB	MPC832XEMDS	MPC8349EMDS	MPC8349ITX
+	MPC8349ITXGP	MPC8360EMDS	sbc8349		TQM834x
 "
 
 
diff --git a/Makefile b/Makefile
index 0b0c0d00e..f7fde1ebc 100644
--- a/Makefile
+++ b/Makefile
@@ -1624,6 +1624,19 @@ r5200_config :		unconfig
 ## MPC83xx Systems
 #########################################################################
 
+MPC8313ERDB_33_config \
+MPC8313ERDB_66_config: unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "...33M ..." ; \
+		echo "#define CFG_33MHZ" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _66_,$@)" ] ; then \
+		echo -n "...66M..." ; \
+		echo "#define CFG_66MHZ" >>include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+
 MPC832XEMDS_config \
 MPC832XEMDS_HOST_33_config \
 MPC832XEMDS_HOST_66_config \
@@ -1689,19 +1702,6 @@ MPC8360EMDS_SLAVE_config:	unconfig
 	fi ;
 	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
 
-MPC8313ERDB_33_config \
-MPC8313ERDB_66_config: unconfig
-	@echo "" >include/config.h ; \
-	if [ "$(findstring _33_,$@)" ] ; then \
-		echo -n "...33M ..." ; \
-		echo "#define CFG_33MHZ" >>include/config.h ; \
-	fi ; \
-	if [ "$(findstring _66_,$@)" ] ; then \
-		echo -n "...66M..." ; \
-		echo "#define CFG_66MHZ" >>include/config.h ; \
-	fi ;
-	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
-
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
 
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index 2a2b0bd90..785d6129d 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <pci.h>
+#include <ft_build.h>
 #include <asm/mpc8349_pci.h>
 
 #ifdef CONFIG_83XX_GENERIC_PCI
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 2519c6b8b..11858bfb8 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -47,9 +47,9 @@
 #define CONFIG_83XX_GENERIC_PCI
 
 #ifdef CFG_66MHZ
-#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CFG_33MHZ)
-#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
 #else
 #error Unknown oscillator frequency.
 #endif

From 54b2d434ae9d01787936f34fe1759cf3d7624ae3 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Mon, 30 Apr 2007 15:26:21 -0500
Subject: [PATCH 14/38] mpc83xx: replace elaborate boottime verbosity with
 'clocks' command

and fix CPU: to align with Board: display text.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 cpu/mpc83xx/cpu.c   |  8 +++++---
 cpu/mpc83xx/speed.c | 10 ++++++++--
 include/common.h    |  2 --
 lib_ppc/board.c     |  4 ----
 4 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 332afaad9..e078f27a2 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -52,7 +52,7 @@ int checkcpu(void)
 
 	immr = (immap_t *)CFG_IMMR;
 
-	puts("CPU: ");
+	puts("CPU:   ");
 
 	switch (pvr & 0xffff0000) {
 		case PVR_E300C1:
@@ -158,10 +158,12 @@ int checkcpu(void)
 	/* Multiple revisons of 834x processors may have the same SPRIDR value.
 	 * So use PVR to identify the revision number.
 	 */
-	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
+	printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 #else
-	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
+	printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
 #endif
+	printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+
 	return 0;
 }
 
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 1a440310e..bf3061654 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <mpc83xx.h>
+#include <command.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -365,11 +366,11 @@ ulong get_bus_freq(ulong dummy)
 	return gd->csb_clk;
 }
 
-int print_clock_conf(void)
+int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	printf("Clock configuration:\n");
-	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 	printf("  Core:                %4d MHz\n", gd->core_clk / 1000000);
+	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 	printf("  QE:                  %4d MHz\n", gd->qe_clk / 1000000);
 	printf("  BRG:                 %4d MHz\n", gd->brg_clk / 1000000);
@@ -395,3 +396,8 @@ int print_clock_conf(void)
 #endif
 	return 0;
 }
+
+U_BOOT_CMD(clocks, 1, 0, do_clocks,
+	"clocks  - print clock configuration\n",
+	"    clocks\n"
+);
diff --git a/include/common.h b/include/common.h
index b162dbd7c..c4fc2b344 100644
--- a/include/common.h
+++ b/include/common.h
@@ -440,8 +440,6 @@ int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
 #if defined(CONFIG_8260)
 int	prt_8260_clks (void);
-#elif defined(CONFIG_MPC83XX)
-int print_clock_conf(void);
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 24e8e970b..1e7f172d6 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -310,10 +310,6 @@ init_fnc_t *init_sequence[] = {
 	prt_8260_clks,
 #endif /* CONFIG_8260 */
 
-#if defined(CONFIG_MPC83XX)
-	print_clock_conf,
-#endif
-
 	checkcpu,
 #if defined(CONFIG_MPC5xxx)
 	prt_mpc5xxx_clks,

From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Mon, 30 Apr 2007 13:59:50 -0500
Subject: [PATCH 15/38] Fix memory initialization on MPC8349E-mITX

Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized.  This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.

Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Michael Benedict <MBenedict@twacs.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/mpc8349itx/mpc8349itx.c | 3 +--
 cpu/mpc83xx/spd_sdram.c       | 5 -----
 include/configs/MPC8349ITX.h  | 3 +++
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
index 2b3ded176..178b1d36f 100644
--- a/board/mpc8349itx/mpc8349itx.c
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -80,8 +80,7 @@ int fixed_sdram(void)
 	im->ddr.sdram_interval =
 	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
 						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	im->ddr.sdram_clk_cntl =
-	    DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
 
 	udelay(200);
 
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 41a1f1fc7..647813f68 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -693,11 +693,6 @@ long int spd_sdram()
 
 #ifdef CFG_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
 	ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-#else
-	/* SS_EN = 0, source synchronous disable
-	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
-	 */
-	ddr->sdram_clk_cntl = 0x00000000;
 #endif
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37bbfb336..906339e9d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -154,6 +154,9 @@
 #define CFG_MEMTEST_START	0x1000		/* memtest region */
 #define CFG_MEMTEST_END		0x2000
 
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 #endif

From 068aab660bc3912b930be5540e6b3f3fd6ad3c96 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 3 May 2007 19:43:52 -0500
Subject: [PATCH 16/38] mpc83xx: fix trivial error in MAKEALL

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 MAKEALL | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index a6b93b3c5..6391b61d5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -132,8 +132,8 @@ LIST_8260="	\
 #########################################################################
 
 LIST_83xx="	\
-	MPC8313ERDB	MPC832XEMDS	MPC8349EMDS	MPC8349ITX
-	MPC8349ITXGP	MPC8360EMDS	sbc8349		TQM834x
+	MPC8313ERDB	MPC832XEMDS	MPC8349EMDS	MPC8349ITX	\
+	MPC8349ITXGP	MPC8360EMDS	sbc8349		TQM834x		\
 "
 
 

From f7e2e0eb0668136305f78bb9c21be79b48a34247 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 5 May 2007 18:27:16 +0200
Subject: [PATCH 17/38] new: FSL and MSR support

---
 common/cmd_mfsl.c            | 265 +++++++++++++++++++++++++++++++++++
 include/asm-microblaze/asm.h |  37 +++++
 2 files changed, 302 insertions(+)
 create mode 100644 common/cmd_mfsl.c
 create mode 100644 include/asm-microblaze/asm.h

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
new file mode 100644
index 000000000..827b75e6c
--- /dev/null
+++ b/common/cmd_mfsl.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Microblaze FSL support
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/asm.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_MFSL)
+
+int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int fslnum;
+	unsigned int num;
+	unsigned int blocking;
+
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	blocking = (unsigned int)simple_strtoul (argv[2], NULL, 16);
+	if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
+		puts ("Bad number of FSL\n");
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	switch (fslnum) {
+#if (XILINX_FSL_NUMBER > 0)
+	case 0:
+		if (blocking) {
+			GET (num, 0);
+		} else {
+			NGET (num, 0);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 1)
+	case 1:
+		if (blocking) {
+			GET (num, 1);
+		} else {
+			NGET (num, 1);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 2)
+	case 2:
+		if (blocking) {
+			GET (num, 2);
+		} else {
+			NGET (num, 2);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 3)
+	case 3:
+		if (blocking) {
+			GET (num, 3);
+		} else {
+			NGET (num, 3);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 4)
+	case 4:
+		if (blocking) {
+			GET (num, 4);
+		} else {
+			NGET (num, 4);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 5)
+	case 5:
+		if (blocking) {
+			GET (num, 5);
+		} else {
+			NGET (num, 5);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 6)
+	case 6:
+		if (blocking) {
+			GET (num, 6);
+		} else {
+			NGET (num, 6);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 7)
+	case 7:
+		if (blocking) {
+			GET (num, 7);
+		} else {
+			NGET (num, 7);
+		}
+		break;
+#endif
+	default:
+		return 1;
+	}
+
+	printf ("%01x: 0x%08lx - %s read\n", fslnum, num,
+		blocking ? "blocking" : "non blocking");
+	return 0;
+}
+
+int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int fslnum;
+	unsigned int num;
+	unsigned int blocking;
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	num = (unsigned int)simple_strtoul (argv[2], NULL, 16);
+	blocking = (unsigned int)simple_strtoul (argv[3], NULL, 16);
+	if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
+		printf ("Bad number of FSL\nUsage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	switch (fslnum) {
+#if (XILINX_FSL_NUMBER > 0)
+	case 0:
+		if (blocking) {
+			PUT (num, 0);
+		} else {
+			NPUT (num, 0);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 1)
+	case 1:
+		if (blocking) {
+			PUT (num, 1);
+		} else {
+			NPUT (num, 1);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 2)
+	case 2:
+		if (blocking) {
+			PUT (num, 2);
+		} else {
+			NPUT (num, 2);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 3)
+	case 3:
+		if (blocking) {
+			PUT (num, 3);
+		} else {
+			NPUT (num, 3);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 4)
+	case 4:
+		if (blocking) {
+			PUT (num, 4);
+		} else {
+			NPUT (num, 4);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 5)
+	case 5:
+		if (blocking) {
+			PUT (num, 5);
+		} else {
+			NPUT (num, 5);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 6)
+	case 6:
+		if (blocking) {
+			PUT (num, 6);
+		} else {
+			NPUT (num, 6);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 7)
+	case 7:
+		if (blocking) {
+			PUT (num, 7);
+		} else {
+			NPUT (num, 7);
+		}
+		break;
+#endif
+	default:
+		return 1;
+	}
+
+	printf ("%01x: 0x%08lx - %s write\n", fslnum, num,
+		blocking ? "blocking" : "non blocking");
+	return 0;
+
+}
+
+int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int val = 0;
+
+	if (argc < 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	RMSR (val);
+	printf ("rmsr: 0x%08lx\n", val);
+	return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD (frd, 3, 1, do_frd,
+	    "frd     - read data from FSL\n",
+	    "- [fslnum [0|x]],  (0 - non blocking|x - blocking).\n");
+
+U_BOOT_CMD (fwr, 4, 1, do_fwr,
+	    "fwr     - write data to FSL\n",
+	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
+
+U_BOOT_CMD (rmsr, 1, 1, do_rmsr,
+	    "rmsr    - read MSR register\n", "- read MSR register.\n");
+
+#endif	/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
new file mode 100644
index 000000000..67475725e
--- /dev/null
+++ b/include/asm-microblaze/asm.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* FSL macros */
+#define NGET(val, fslnum) \
+	__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+#define GET(val, fslnum) \
+	__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+#define NPUT(val, fslnum) \
+	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+#define PUT(val, fslnum) \
+	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
+								
+/* CPU dependent */
+#define RMSR(val) \
+	__asm__ __volatile__ ("mfs %0,rmsr":"=r" (val));

From ffc50f9bb194343c6303517a517708457a5eb6b8 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 5 May 2007 18:54:42 +0200
Subject: [PATCH 18/38] new: FSL and MSR support #2

---
 README                           | 1 +
 board/xilinx/ml401/xparameters.h | 3 +++
 common/Makefile                  | 2 +-
 include/cmd_confdefs.h           | 2 ++
 include/configs/ml401.h          | 3 +++
 5 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/README b/README
index 15428643e..33039f1d9 100644
--- a/README
+++ b/README
@@ -703,6 +703,7 @@ The following options need to be configured:
 		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		CFG_CMD_CDP	* Cisco Discover Protocol support
+		CFG_CMD_FSL	* Microblaze FSL support
 		-----------------------------------------------
 		CFG_CMD_ALL	all
 
diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 4fe36f8a9..f63ffed3d 100644
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -29,6 +29,9 @@
 /* System Clock Frequency */
 #define XILINX_CLOCK_FREQ	100000000
 
+/* Microblaze is microblaze_0 */
+#define XILINX_FSL_NUMBER	2
+
 /* Interrupt controller is intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
 #define XILINX_INTC_NUM_INTR_INPUTS	4
diff --git a/common/Makefile b/common/Makefile
index 6f81c4abc..c088821a5 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -50,7 +50,7 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  memsize.o miiphybb.o miiphyutil.o \
 	  s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
 	  usb.o usb_kbd.o usb_storage.o \
-	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
+	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o
 
 SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
index cf3658310..b3ccdcea2 100644
--- a/include/cmd_confdefs.h
+++ b/include/cmd_confdefs.h
@@ -94,6 +94,7 @@
 #define CFG_CMD_EXT2	0x1000000000000000ULL	/* EXT2 Support			*/
 #define CFG_CMD_SNTP	0x2000000000000000ULL	/* SNTP support			*/
 #define CFG_CMD_DISPLAY	0x4000000000000000ULL	/* Display support		*/
+#define CFG_CMD_MFSL	0x8000000000000000ULL	/* FSL support for Microblaze	*/
 
 #define CFG_CMD_ALL	0xFFFFFFFFFFFFFFFFULL	/* ALL commands			*/
 
@@ -125,6 +126,7 @@
 			CFG_CMD_IRQ	| \
 			CFG_CMD_JFFS2	| \
 			CFG_CMD_KGDB	| \
+			CFG_CMD_MFSL	| \
 			CFG_CMD_MII	| \
 			CFG_CMD_MMC	| \
 			CFG_CMD_NAND	| \
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index acaa1e4f2..f3ef962a7 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -161,6 +161,7 @@
 				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 	#else	/* !RAMENV */
@@ -185,6 +186,7 @@
 				CFG_CMD_EXT2 |\
 				CFG_CMD_JFFS2 |\
 				CFG_CMD_ECHO |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +208,7 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 #endif	/* !FLASH */

From 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 17:11:09 +0200
Subject: [PATCH 19/38] new: add writing to msr register

---
 board/xilinx/ml401/xparameters.h | 34 ++++++++++++++++++--------------
 common/cmd_mfsl.c                | 14 +++++++++----
 include/asm-microblaze/asm.h     | 12 ++++++++---
 3 files changed, 38 insertions(+), 22 deletions(-)
 mode change 100644 => 100755 board/xilinx/ml401/xparameters.h

diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
old mode 100644
new mode 100755
index f63ffed3d..2b0c045b9
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -21,50 +21,54 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- *
  * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+ * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
  */
 
 /* System Clock Frequency */
 #define XILINX_CLOCK_FREQ	100000000
 
 /* Microblaze is microblaze_0 */
-#define XILINX_FSL_NUMBER	2
+#define XILINX_FSL_NUMBER	3
 
-/* Interrupt controller is intc_0 */
+/* Interrupt controller is opb_intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS	4
+#define XILINX_INTC_NUM_INTR_INPUTS	5
 
-/* Timer pheriphery is opb_timer_0 */
+/* Timer pheriphery is opb_timer_1 */
 #define XILINX_TIMER_BASEADDR	0x41c00000
 #define XILINX_TIMER_IRQ	0
 
-/* Uart pheriphery is console_uart */
+/* Uart pheriphery is RS232_Uart */
 #define XILINX_UART_BASEADDR	0x40600000
 #define XILINX_UART_BAUDRATE	115200
 
-/* GPIO is opb_gpio_0*/
-#define XILINX_GPIO_BASEADDR	0x90000000
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR	0x40800000
+#define XILINX_IIC_0_FREQ	100000
+#define XILINX_IIC_0_BIT	0
 
-/* Flash Memory is opb_emc_0 */
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR	0x40000000
+
+/* Flash Memory is FLASH_2Mx32 */
 #define XILINX_FLASH_START	0x2c000000
 #define XILINX_FLASH_SIZE	0x00800000
 
-/* Main Memory is plb_ddr_0 */
+/* Main Memory is DDR_SDRAM_64Mx32 */
 #define XILINX_RAM_START	0x28000000
 #define XILINX_RAM_SIZE	0x04000000
 
-/* Sysace Controller is opb_sysace_0 */
+/* Sysace Controller is SysACE_CompactFlash */
 #define XILINX_SYSACE_BASEADDR	0x41800000
-#define XILINX_SYSACE_HIGHADDR	0x4180FFFF
+#define XILINX_SYSACE_HIGHADDR	0x4180ffff
 #define XILINX_SYSACE_MEM_WIDTH	16
 
-/* Ethernet controller is opb_ethernet_0 */
+/* Ethernet controller is Ethernet_MAC */
 #define XPAR_XEMAC_NUM_INSTANCES	1
 #define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
 #define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0fFFF
+#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0ffff
 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
 #define XPAR_OPB_ETHERNET_0_MII_EXIST	1
diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 827b75e6c..ca8a8897d 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -238,13 +238,19 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	int val = 0;
+	unsigned int val = 0;
 
+	val = (unsigned int)simple_strtoul (argv[1], NULL, 16);
 	if (argc < 1) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
-	RMSR (val);
+	if (argc > 1) {
+		MTS (val);
+		MFS (val);
+	} else {
+		MFS (val);
+	}
 	printf ("rmsr: 0x%08lx\n", val);
 	return 0;
 }
@@ -259,7 +265,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 	    "fwr     - write data to FSL\n",
 	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
 
-U_BOOT_CMD (rmsr, 1, 1, do_rmsr,
+U_BOOT_CMD (rmsr, 3, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
 
-#endif	/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
+#endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 67475725e..fcda31f4a 100644
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -31,7 +31,13 @@
 	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
 #define PUT(val, fslnum) \
 	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
-								
+
 /* CPU dependent */
-#define RMSR(val) \
-	__asm__ __volatile__ ("mfs %0,rmsr":"=r" (val));
+#define MFS(val) \
+	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
+
+#define MTS(val) \
+	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
+
+#define R14(val) \
+	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));

From 42efed6130c8fcf7da881385b5427065d2801757 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 17:22:25 +0200
Subject: [PATCH 20/38] fix: interrupt handler for multiple sources

---
 cpu/microblaze/interrupts.c              | 19 ++++++++++++-------
 cpu/microblaze/timer.c                   |  4 +---
 include/asm-microblaze/microblaze_intc.h |  2 ++
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 2db847cd0..115e58d7f 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/microblaze_intc.h>
+#include <asm/asm.h>
 
 #undef DEBUG_INT
 
@@ -106,7 +107,6 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
 		act->count = 0;
 		enable_one_interrupt (irq);
 	} else {		/* disable */
-
 		act->handler = (interrupt_handler_t *) def_hdlr;
 		act->arg = (void *)irq;
 		disable_one_interrupt (irq);
@@ -147,12 +147,13 @@ int interrupts_init (void)
 
 void interrupt_handler (void)
 {
-	int irqs;
-	irqs = (intc->isr & intc->ier);	/* find active interrupt */
-
+	int irqs = (intc->isr & intc->ier);	/* find active interrupt */
+	int i = 1;
 #ifdef DEBUG_INT
+	int value;
 	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
+	R14(value);
 	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 	struct irq_action *act = vecs;
@@ -165,15 +166,19 @@ void interrupt_handler (void)
 #endif
 			act->handler (act->arg);
 			act->count++;
+			intc->iar = i;
+			return;
 		}
 		irqs >>= 1;
 		act++;
+		i <<= 1;
 	}
-	intc->iar = 0xFFFFFFFF;	/* erase all events */
-#ifdef DEBUG
+
+#ifdef DEBUG_INT
 	printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
 		intc->ier, intc->iar, intc->mer);
-	printf ("Interrupt handler on %x line, r14\n", irqs);
+	R14(value);
+	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 }
 #endif
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
index be4fd57cc..ab1cb1274 100644
--- a/cpu/microblaze/timer.c
+++ b/cpu/microblaze/timer.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <asm/microblaze_timer.h>
+#include <asm/microblaze_intc.h>
 
 volatile int timestamp = 0;
 
@@ -44,9 +45,6 @@ void set_timer (ulong t)
 
 #ifdef CFG_INTC_0
 #ifdef CFG_TIMER_0
-extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
-				       void *arg);
-
 microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
 
 void timer_isr (void *arg)
diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h
index 73f732c56..4c385aa24 100644
--- a/include/asm-microblaze/microblaze_intc.h
+++ b/include/asm-microblaze/microblaze_intc.h
@@ -39,3 +39,5 @@ struct irq_action {
 	int count; /* number of interrupt */
 };
 
+void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+				       void *arg);

From fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:12:43 +0200
Subject: [PATCH 21/38] fix: clean interrupt

---
 cpu/microblaze/Makefile     |  3 ++-
 cpu/microblaze/interrupts.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index db1afa553..b7be5e146 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+SOBJS	= dcache.o icache.o irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 115e58d7f..c0c92ec55 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,14 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	microblaze_enable_interrupts ();
+	__asm__ __volatile__ ("msrset r0, 0x2");
+	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
-	microblaze_disable_interrupts ();
+	__asm__ __volatile__ ("msrclr r0, 0x2");
+	//microblaze_disable_interrupts ();
 	return 0;
 }
 
@@ -49,6 +51,10 @@ int disable_interrupts (void)
 #ifdef CFG_TIMER_0
 extern void timer_init (void);
 #endif
+#ifdef CFG_FSL_2
+extern void fsl_init2 (void);
+#endif
+
 
 static struct irq_action vecs[CFG_INTC_0_NUM];
 
@@ -140,6 +146,9 @@ int interrupts_init (void)
 	intc_init ();
 #ifdef CFG_TIMER_0
 	timer_init ();
+#endif
+#ifdef CFG_FSL_2
+	fsl_init2 ();
 #endif
 	enable_interrupts ();
 	return 0;

From f3f001a341ef185d0f13841be5b5dc3395aacc31 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:25:08 +0200
Subject: [PATCH 22/38] fix: remove asm code

---
 cpu/microblaze/Makefile      |  3 +-
 cpu/microblaze/cache.c       | 16 +++++++++
 cpu/microblaze/dcache.S      | 68 -----------------------------------
 cpu/microblaze/disable_int.S | 46 ------------------------
 cpu/microblaze/enable_int.S  | 38 --------------------
 cpu/microblaze/icache.S      | 69 ------------------------------------
 6 files changed, 17 insertions(+), 223 deletions(-)
 delete mode 100644 cpu/microblaze/dcache.S
 delete mode 100644 cpu/microblaze/disable_int.S
 delete mode 100644 cpu/microblaze/enable_int.S
 delete mode 100644 cpu/microblaze/icache.S

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index b7be5e146..9d542013c 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,8 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
-SOBJS	= dcache.o icache.o irq.o
+SOBJS	= irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
index fc388ebb5..683044cae 100644
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -45,4 +45,20 @@ int icache_status (void)
 	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
 	return i;
 }
+
+void	icache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x80");
+}
+
+void	icache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x80");
+}
+
+void	dcache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x20");
+}
+
+void	dcache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x20");
+}
 #endif
diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S
deleted file mode 100644
index eaf96717e..000000000
--- a/cpu/microblaze/dcache.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-	.text
-	.globl	dcache_enable
-	.ent	dcache_enable
-	.align	2
-dcache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_enable
-
-	.text
-	.globl	dcache_disable
-	.ent	dcache_disable
-	.align	2
-dcache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the data cache enable bit */
-	andi	r12, r12, ~0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_disable
diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S
deleted file mode 100644
index aecd79513..000000000
--- a/cpu/microblaze/disable_int.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_disable_interrupts
-	.ent	microblaze_disable_interrupts
-	.align	2
-microblaze_disable_interrupts:
-	#Make space on stack for a temporary
-	addi	r1, r1, -4
-	#Save register r12
-	swi	r12, r1, 0
-	#Read the MSR register
-	mfs	r12, rmsr
-	#Clear the interrupt enable bit
-	andi	r12, r12, ~2
-	#Save the MSR register
-	mts	rmsr, r12
-	#Load register r12
-	lwi	r12, r1, 0
-	#Return
-	rtsd	r15, 8
-	#Update stack in the delay slot
-	addi	r1, r1, 4
-	.end	microblaze_disable_interrupts
diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S
deleted file mode 100644
index c096c6c3c..000000000
--- a/cpu/microblaze/enable_int.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstrmonstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_enable_interrupts
-	.ent	microblaze_enable_interrupts
-	.align	2
-microblaze_enable_interrupts:
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	rtsd	r15, 8
-	addi	r1, r1, 4
-	.end	microblaze_enable_interrupts
diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S
deleted file mode 100644
index 25940d106..000000000
--- a/cpu/microblaze/icache.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	icache_enable
-	.ent	icache_enable
-	.align	2
-icache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_enable
-
-	.text
-	.globl	icache_disable
-	.ent	icache_disable
-	.align	2
-icache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the instruction enable bit */
-	andi	r12, r12, ~0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_disable

From 792032baa7d625e34c981ab6df521911bd8dc861 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:30:12 +0200
Subject: [PATCH 23/38] fix: interrupt handler remove asm code

---
 cpu/microblaze/interrupts.c | 2 --
 cpu/microblaze/irq.S        | 9 +--------
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index c0c92ec55..dd6a0c777 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -37,13 +37,11 @@ extern void microblaze_enable_interrupts (void);
 void enable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrset r0, 0x2");
-	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrclr r0, 0x2");
-	//microblaze_disable_interrupts ();
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
index a4e3fbfad..393d6e8dd 100644
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -151,14 +151,7 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	addi	r1, r1, 4
-	nop
+	msrset	r0, 2
 	bra	r14
 	nop
 	nop

From 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:33:51 +0200
Subject: [PATCH 24/38] new: fsl interrupt support FSL_Has_data is connected to
 INTC.

---
 board/xilinx/ml401/ml401.c | 22 +++++++++++++++++++++-
 include/configs/ml401.h    |  4 ++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c
index b48103fdc..955936d90 100644
--- a/board/xilinx/ml401/ml401.c
+++ b/board/xilinx/ml401/ml401.c
@@ -27,6 +27,8 @@
 
 #include <common.h>
 #include <config.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
 
 void do_reset (void)
 {
@@ -43,7 +45,25 @@ void do_reset (void)
 int gpio_init (void)
 {
 #ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
+	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF;
 #endif
 	return 0;
 }
+
+#ifdef CFG_FSL_2
+void fsl_isr2 (void *arg) {
+	volatile int num;
+	*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) =
+	    ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)));
+	GET (num, 2);
+	NGET (num, 2);
+	puts("*");
+}
+
+void fsl_init2 (void) {
+	puts("fsl_init2\n");
+	install_interrupt_handler (FSL_INTR_2,\
+ fsl_isr2,\
+ NULL);
+}
+#endif
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f3ef962a7..327d31c10 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -58,6 +58,10 @@
 #define	FREQUENCE		XILINX_CLOCK_FREQ
 #define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
 
+/* FSL */
+#define	CFG_FSL_2
+#define	FSL_INTR_2	1
+
 /*
  * memory layout - Example
  * TEXT_BASE = 0x1200_0000;

From a7bac7e9b57ba948051beb19ec5be3a75ce75383 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:43:10 +0200
Subject: [PATCH 25/38] fix: read and write MSR - repair number of parameters

---
 common/cmd_mfsl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index ca8a8897d..7aa37afd3 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -265,7 +265,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 	    "fwr     - write data to FSL\n",
 	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
 
-U_BOOT_CMD (rmsr, 3, 1, do_rmsr,
+U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
 
 #endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */

From 008861a2f3ef2c062744d733787c7e530a1b8761 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Mon, 7 May 2007 22:36:15 +0200
Subject: [PATCH 26/38] [MPC5xxx] There are networking problems on the
 Motion-PRO board with current PHY initalization code (tftp timeouts all the
 time). This commit temporarily disables PHY initalization sequence to make
 the networking operational, until a fix is found.

---
 cpu/mpc5xxx/fec.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index e6392340a..0b8f24d18 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -395,7 +395,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 {
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
+#ifndef CONFIG_MOTIONPRO
 	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
+#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init_phy... Begin\n");
@@ -428,6 +430,14 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->imask = 0x00000000;
 
+/*
+ * In original Promess-provided code PHY initialization is disabled with the
+ * following comment: "Phy initialization is DISABLED for now.  There was a
+ * problem with running 100 Mbps on PRO board". Thus we temporarily disable
+ * PHY initialization for the Motion-PRO board, until a proper fix is found.
+ */
+
+#ifndef CONFIG_MOTIONPRO
 	if (fec->xcv_type != SEVENWIRE) {
 		/*
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -550,6 +560,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 		}
 
 	}
+#endif /* !CONFIG_MOTIONPRO */
 
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)

From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 23:58:31 +0200
Subject: [PATCH 27/38] new: USE_MSR_INTR support

---
 board/xilinx/ml401/xparameters.h |  3 ++-
 cpu/microblaze/cache.c           |  9 ++++----
 cpu/microblaze/interrupts.c      |  4 ++--
 cpu/microblaze/irq.S             | 14 ++++++++++++
 include/asm-microblaze/asm.h     | 37 ++++++++++++++++++++++++++++++++
 5 files changed, 60 insertions(+), 7 deletions(-)
 mode change 100644 => 100755 cpu/microblaze/cache.c
 mode change 100644 => 100755 cpu/microblaze/interrupts.c
 mode change 100644 => 100755 cpu/microblaze/irq.S
 mode change 100644 => 100755 include/asm-microblaze/asm.h

diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 2b0c045b9..1a116ead1 100755
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -29,11 +29,12 @@
 #define XILINX_CLOCK_FREQ	100000000
 
 /* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR	1
 #define XILINX_FSL_NUMBER	3
 
 /* Interrupt controller is opb_intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS	5
+#define XILINX_INTC_NUM_INTR_INPUTS	6
 
 /* Timer pheriphery is opb_timer_1 */
 #define XILINX_TIMER_BASEADDR	0x41c00000
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
old mode 100644
new mode 100755
index 683044cae..4f36a84ec
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_CACHE)
 
@@ -47,18 +48,18 @@ int icache_status (void)
 }
 
 void	icache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x80");
+	MSRSET(0x20);
 }
 
 void	icache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x80");
+	MSRCLR(0x20);
 }
 
 void	dcache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x20");
+	MSRSET(0x80);
 }
 
 void	dcache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x20");
+	MSRCLR(0x80);
 }
 #endif
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
old mode 100644
new mode 100755
index dd6a0c777..b61153f8e
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,12 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrset r0, 0x2");
+	MSRSET(0x2);
 }
 
 int disable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrclr r0, 0x2");
+	MSRCLR(0x2);
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
old mode 100644
new mode 100755
index 393d6e8dd..e1fc19046
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -23,6 +23,7 @@
  */
 
 #include <config.h>
+#include <asm/asm.h>
 	.text
 	.global _interrupt_handler
 _interrupt_handler:
@@ -151,7 +152,20 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
+#ifdef XILINX_USE_MSR_INSTR
 	msrset	r0, 2
+#else
+	/* FIXME unstable in stressed mode - two irqs */
+	nop
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	nop
+#endif
 	bra	r14
 	nop
 	nop
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
old mode 100644
new mode 100755
index fcda31f4a..c59854a86
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -39,5 +39,42 @@
 #define MTS(val) \
 	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
 
+/* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+
+/* use machine status registe USE_MSR_REG */
+#ifdef XILINX_USE_MSR_INSTR
+#define MSRSET(val) \
+	__asm__ __volatile__ ("msrset r0," #val );
+
+#define MSRCLR(val) \
+	__asm__ __volatile__ ("msrclr r0," #val );
+
+#else
+#define MSRSET(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs 	%0, rmsr;			\
+			ori	%0, %0, "#val";			\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+
+#define MSRCLR(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs 	%0, rmsr;			\
+			andi	%0, %0, ~"#val";		\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+#endif

From 1f1369c34b629be94702684d41d3fddf0f6193e7 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 09:21:57 +0200
Subject: [PATCH 28/38] [Motion-PRO] Enable Flat Device Tree support and modify
 default environment to allow booting of FDT-expecting kernels.

---
 board/motionpro/motionpro.c | 11 +++++++++
 include/configs/motionpro.h | 49 +++++++++++++++++++++++--------------
 2 files changed, 41 insertions(+), 19 deletions(-)

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 95576ed56..887aadeee 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -29,6 +29,9 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
 
 /* Kollmorgen DPR initialization data */
 struct init_elem {
@@ -169,3 +172,11 @@ int checkboard (void)
 	puts("Board: Promess Motion-PRO board\n");
 	return 0;
 }
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5328e8d6b..b1edde8b4 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -26,7 +26,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /*
  * High Level Configuration Options
  */
@@ -94,42 +93,44 @@
  * Default environment settings
  */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	"sdram_test=0\0"						\
 	"netdev=eth0\0"							\
 	"hostname=motionpro\0"						\
 	"netmask=255.255.0.0\0"						\
 	"ipaddr=192.168.160.22\0"					\
 	"serverip=192.168.1.1\0"					\
 	"gatewayip=192.168.1.1\0"					\
-	"kernel_addr=200000\0"						\
+	"console=ttyPSC0,115200\0"					\
 	"u-boot_addr=100000\0"						\
-	"kernel_sector=20\0"						\
-	"kernel_size=1000\0"						\
-	"console=ttyS0,115200\0"					\
+	"kernel_addr=200000\0"						\
+	"fdt_addr=400000\0"						\
+	"ramdisk_addr=500000\0"						\
 	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
-	"bootfile=/tftpboot/motionpro/uImage\0"				\
 	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
+	"bootfile=/tftpboot/motionpro/uImage\0"				\
+	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
+	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
 	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
 		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
 		"prot on fff00000 fff3ffff\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) console=$(console) "		\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; "	\
-		"bootm $(kernel_addr)\0"				\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"fstype=ext3\0"							\
-	"fatargs=setenv bootargs init=/linuxrc rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
+		"console=$(console)\0"					\
+	"net_nfs=tftp $(kernel_addr) $(bootfile); "			\
+		"tftp $(fdt_addr) $(fdt_file); run nfsargs addip; "	\
+		"bootm $(kernel_addr) - $(fdt_addr)\0"			\
+	"net_self=tftp $(kernel_addr) $(bootfile); "			\
+		"tftp $(fdt_addr) $(fdt_file); "			\
+		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
+		"run ramargs addip; "					\
+		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
-
 /*
  * do board-specific init
  */
@@ -146,7 +147,6 @@
  */
 #define CFG_MPC5XXX_CLKIN	25000000
 
-
 /*
  * Memory map
  */
@@ -302,4 +302,15 @@
 /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
 #define CFG_RESET_ADDRESS	0xfff00100
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PAT		"/soc5200@f0000000/serial@2000"
+
 #endif /* __CONFIG_H */

From 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 09:39:12 +0200
Subject: [PATCH 29/38] [Motion-PRO] Change IPB clock frequency from 50MHz to
 100MHz. This eliminates networking problems in Linux (timeouts).

---
 include/configs/motionpro.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index b1edde8b4..74ba800cb 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -147,6 +147,13 @@
  */
 #define CFG_MPC5XXX_CLKIN	25000000
 
+
+/*
+ * Set IPB speed to 100MHz (yes, the #define is misnamed)
+ */
+#define CFG_IPBSPEED_133
+
+
 /*
  * Memory map
  */

From fa5c2ba123b1bf88455bfc21db5e786ca045029d Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 10:23:56 +0200
Subject: [PATCH 30/38] [Motion-PRO] Add ATA support. Add CF-booting commands
 to the default environment.

---
 include/configs/motionpro.h | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 74ba800cb..989a534e6 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -30,7 +30,6 @@
  * High Level Configuration Options
  */
 
-
 /* CPU and board */
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
@@ -49,7 +48,9 @@
 				CFG_CMD_MII	| \
 				CFG_CMD_BEDBUG	| \
 				CFG_CMD_NET	| \
-				CFG_CMD_PING)
+				CFG_CMD_PING	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -104,11 +105,13 @@
 	"kernel_addr=200000\0"						\
 	"fdt_addr=400000\0"						\
 	"ramdisk_addr=500000\0"						\
+	"multi_image_addr=800000\0"					\
 	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
 	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
 	"bootfile=/tftpboot/motionpro/uImage\0"				\
 	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
 	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
+	"multi_image_file=kernel+initrd+dtb.img\0"			\
 	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
 		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
@@ -116,6 +119,7 @@
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"fat_args=setenv bootargs rw\0"					\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
 		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
@@ -128,6 +132,9 @@
 		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
 		"run ramargs addip; "					\
 		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
+	"fat_multi=run fat_args addip; fatload ide 0:1 "		\
+		"${multi_image_addr} ${multi_image_file}; "		\
+		"bootm ${multi_image_addr}\0"				\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
@@ -251,6 +258,20 @@
 #define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
 
 
+/*
+ * IDE/ATA configuration
+ */
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_ATA_DATA_OFFSET	0x0060
+#define CFG_ATA_REG_OFFSET	CFG_ATA_DATA_OFFSET
+#define CFG_ATA_STRIDE		4
+#define CONFIG_DOS_PARTITION
+
+
 /*
  * Environment settings
  */

From de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3 Mon Sep 17 00:00:00 2001
From: Piotr Kruszynski <ppk@semihalf.com>
Date: Tue, 8 May 2007 13:05:44 +0200
Subject: [PATCH 31/38] [Motion-PRO] Add support for I2C, EEPROM and RTC.

---
 include/configs/motionpro.h | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 989a534e6..f1f7e2ba0 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -50,7 +50,10 @@
 				CFG_CMD_NET	| \
 				CFG_CMD_PING	| \
 				CFG_CMD_IDE	| \
-				CFG_CMD_FAT)
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -272,6 +275,31 @@
 #define CONFIG_DOS_PARTITION
 
 
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* select I2C module #2 */
+#define CFG_I2C_SPEED		100000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
+
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337	1
+#define CFG_I2C_RTC_ADDR	0x68
+
+
 /*
  * Environment settings
  */

From ab874d5047e5d30dbc1e517ff26083efffa98ecb Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:39:11 +0200
Subject: [PATCH 32/38] add: FSL control read and write

---
 common/cmd_mfsl.c            | 267 +++++++++++++++++++++++++----------
 include/asm-microblaze/asm.h |  15 ++
 2 files changed, 210 insertions(+), 72 deletions(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 7aa37afd3..3032489f0 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -55,73 +55,129 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	switch (fslnum) {
 #if (XILINX_FSL_NUMBER > 0)
 	case 0:
-		if (blocking) {
-			GET (num, 0);
-		} else {
-			NGET (num, 0);
+		switch (blocking) {
+		case 0:	NGET (num, 0);
+			break;
+		case 1:	NCGET (num, 0);
+			break;
+		case 2:	GET (num, 0);
+			break;
+		case 3:	CGET (num, 0);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 1)
 	case 1:
-		if (blocking) {
-			GET (num, 1);
-		} else {
-			NGET (num, 1);
+		switch (blocking) {
+		case 0:	NGET (num, 1);
+			break;
+		case 1:	NCGET (num, 1);
+			break;
+		case 2:	GET (num, 1);
+			break;
+		case 3:	CGET (num, 1);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 2)
 	case 2:
-		if (blocking) {
-			GET (num, 2);
-		} else {
-			NGET (num, 2);
+		switch (blocking) {
+		case 0:	NGET (num, 2);
+			break;
+		case 1:	NCGET (num, 2);
+			break;
+		case 2:	GET (num, 2);
+			break;
+		case 3:	CGET (num, 2);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 3)
 	case 3:
-		if (blocking) {
-			GET (num, 3);
-		} else {
-			NGET (num, 3);
+		switch (blocking) {
+		case 0:	NGET (num, 3);
+			break;
+		case 1:	NCGET (num, 3);
+			break;
+		case 2:	GET (num, 3);
+			break;
+		case 3:	CGET (num, 3);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 4)
 	case 4:
-		if (blocking) {
-			GET (num, 4);
-		} else {
-			NGET (num, 4);
+		switch (blocking) {
+		case 0:	NGET (num, 4);
+			break;
+		case 1:	NCGET (num, 4);
+			break;
+		case 2:	GET (num, 4);
+			break;
+		case 3:	CGET (num, 4);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 5)
 	case 5:
-		if (blocking) {
-			GET (num, 5);
-		} else {
-			NGET (num, 5);
+		switch (blocking) {
+		case 0:	NGET (num, 5);
+			break;
+		case 1:	NCGET (num, 5);
+			break;
+		case 2:	GET (num, 5);
+			break;
+		case 3:	CGET (num, 5);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 6)
 	case 6:
-		if (blocking) {
-			GET (num, 6);
-		} else {
-			NGET (num, 6);
+		switch (blocking) {
+		case 0:	NGET (num, 6);
+			break;
+		case 1:	NCGET (num, 6);
+			break;
+		case 2:	GET (num, 6);
+			break;
+		case 3:	CGET (num, 6);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 7)
 	case 7:
-		if (blocking) {
-			GET (num, 7);
-		} else {
-			NGET (num, 7);
+		switch (blocking) {
+		case 0:	NGET (num, 7);
+			break;
+		case 1:	NCGET (num, 7);
+			break;
+		case 2:	GET (num, 7);
+			break;
+		case 3:	CGET (num, 7);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
@@ -129,8 +185,9 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	printf ("%01x: 0x%08lx - %s read\n", fslnum, num,
-		blocking ? "blocking" : "non blocking");
+	printf ("%01x: 0x%08lx - %s %s read\n", fslnum, num,
+		blocking < 2  ? "non blocking" : "blocking",
+		((blocking == 1) || (blocking == 3)) ? "control" : "data" );
 	return 0;
 }
 
@@ -156,73 +213,129 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	switch (fslnum) {
 #if (XILINX_FSL_NUMBER > 0)
 	case 0:
-		if (blocking) {
-			PUT (num, 0);
-		} else {
-			NPUT (num, 0);
+		switch (blocking) {
+		case 0:	NPUT (num, 0);
+			break;
+		case 1:	NCPUT (num, 0);
+			break;
+		case 2:	PUT (num, 0);
+			break;
+		case 3:	CPUT (num, 0);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 1)
 	case 1:
-		if (blocking) {
-			PUT (num, 1);
-		} else {
-			NPUT (num, 1);
+		switch (blocking) {
+		case 0:	NPUT (num, 1);
+			break;
+		case 1:	NCPUT (num, 1);
+			break;
+		case 2:	PUT (num, 1);
+			break;
+		case 3:	CPUT (num, 1);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 2)
 	case 2:
-		if (blocking) {
-			PUT (num, 2);
-		} else {
-			NPUT (num, 2);
+		switch (blocking) {
+		case 0:	NPUT (num, 2);
+			break;
+		case 1:	NCPUT (num, 2);
+			break;
+		case 2:	PUT (num, 2);
+			break;
+		case 3:	CPUT (num, 2);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 3)
 	case 3:
-		if (blocking) {
-			PUT (num, 3);
-		} else {
-			NPUT (num, 3);
+		switch (blocking) {
+		case 0:	NPUT (num, 3);
+			break;
+		case 1:	NCPUT (num, 3);
+			break;
+		case 2:	PUT (num, 3);
+			break;
+		case 3:	CPUT (num, 3);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 4)
 	case 4:
-		if (blocking) {
-			PUT (num, 4);
-		} else {
-			NPUT (num, 4);
+		switch (blocking) {
+		case 0:	NPUT (num, 4);
+			break;
+		case 1:	NCPUT (num, 4);
+			break;
+		case 2:	PUT (num, 4);
+			break;
+		case 3:	CPUT (num, 4);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 5)
 	case 5:
-		if (blocking) {
-			PUT (num, 5);
-		} else {
-			NPUT (num, 5);
+		switch (blocking) {
+		case 0:	NPUT (num, 5);
+			break;
+		case 1:	NCPUT (num, 5);
+			break;
+		case 2:	PUT (num, 5);
+			break;
+		case 3:	CPUT (num, 5);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 6)
 	case 6:
-		if (blocking) {
-			PUT (num, 6);
-		} else {
-			NPUT (num, 6);
+		switch (blocking) {
+		case 0:	NPUT (num, 6);
+			break;
+		case 1:	NCPUT (num, 6);
+			break;
+		case 2:	PUT (num, 6);
+			break;
+		case 3:	CPUT (num, 6);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 7)
 	case 7:
-		if (blocking) {
-			PUT (num, 7);
-		} else {
-			NPUT (num, 7);
+		switch (blocking) {
+		case 0:	NPUT (num, 7);
+			break;
+		case 1:	NCPUT (num, 7);
+			break;
+		case 2:	PUT (num, 7);
+			break;
+		case 3:	CPUT (num, 7);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
@@ -230,8 +343,9 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	printf ("%01x: 0x%08lx - %s write\n", fslnum, num,
-		blocking ? "blocking" : "non blocking");
+	printf ("%01x: 0x%08lx - %s %s write\n", fslnum, num,
+		blocking < 2  ? "non blocking" : "blocking",
+		((blocking == 1) || (blocking == 3)) ? "control" : "data" );
 	return 0;
 
 }
@@ -258,12 +372,21 @@ int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 /***************************************************/
 
 U_BOOT_CMD (frd, 3, 1, do_frd,
-	    "frd     - read data from FSL\n",
-	    "- [fslnum [0|x]],  (0 - non blocking|x - blocking).\n");
+		"frd     - read data from FSL\n",
+		"- [fslnum [0|1|2|3]]\n"
+		" 0 - non blocking data read\n"
+		" 1 - non blocking control read\n"
+		" 2 - blocking data read\n"
+		" 3 - blocking control read\n");
+
 
 U_BOOT_CMD (fwr, 4, 1, do_fwr,
-	    "fwr     - write data to FSL\n",
-	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
+		"fwr     - write data to FSL\n",
+		"- [fslnum [0|1|2|3]]\n"
+		" 0 - non blocking data write\n"
+		" 1 - non blocking control write\n"
+		" 2 - blocking data write\n"
+		" 3 - blocking control write\n");
 
 U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index c59854a86..26e369119 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -25,13 +25,28 @@
 /* FSL macros */
 #define NGET(val, fslnum) \
 	__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+
 #define GET(val, fslnum) \
 	__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+
+#define NCGET(val, fslnum) \
+	__asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
+
+#define CGET(val, fslnum) \
+	__asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
+
 #define NPUT(val, fslnum) \
 	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+
 #define PUT(val, fslnum) \
 	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
 
+#define NCPUT(val, fslnum) \
+	__asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
+
+#define CPUT(val, fslnum) \
+	__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
+
 /* CPU dependent */
 #define MFS(val) \
 	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));

From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:52:52 +0200
Subject: [PATCH 33/38] add: Microblaze V5 exception handling

---
 cpu/microblaze/exception.c   | 10 ++++++++--
 include/asm-microblaze/asm.h |  8 ++++++++
 include/configs/ml401.h      |  1 +
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index b135acbad..87ecbeaa4 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -23,15 +23,16 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 void _hw_exception_handler (void)
 {
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
+	MFSEAR(address);
 	/* loading excetpion state register ESR */
-	__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
+	MFSESR(state);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
@@ -49,6 +50,11 @@ void _hw_exception_handler (void)
 	case 0x5:
 		puts ("Divide by zero exception\n");
 		break;
+#ifdef MICROBLAZE_V5
+	case 0x1000:
+		puts ("Exception in delay slot\n");
+		break;
+#endif
 	default:
 		puts ("Undefined cause\n");
 		break;
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 26e369119..8302ed885 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -48,12 +48,20 @@
 	__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
 
 /* CPU dependent */
+/* machine status register */
 #define MFS(val) \
 	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
 
 #define MTS(val) \
 	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
 
+/* exception status register */
+#define MFSEAR(val) \
+	__asm__ __volatile ("mfs %0,rear":"=r" (val));
+
+#define MFSESR(val) \
+	__asm__ __volatile ("mfs %0,resr":"=r" (val));
+
 /* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 327d31c10..4cfe802c3 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
 #include "../board/xilinx/ml401/xparameters.h"
 
 #define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
+#define	MICROBLAZE_V5		1
 #define	CONFIG_ML401		1	/* ML401 Board */
 
 /* uart */

From e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 15:57:43 +0200
Subject: [PATCH 34/38] add: reading special purpose registers

---
 common/cmd_mfsl.c            | 43 +++++++++++++++++++++++++++---------
 cpu/microblaze/exception.c   |  4 ++--
 include/asm-microblaze/asm.h | 17 +++++---------
 3 files changed, 41 insertions(+), 23 deletions(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 3032489f0..26786aa8c 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -350,22 +350,41 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 }
 
-int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
+	unsigned int reg = 0;
 	unsigned int val = 0;
 
-	val = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
 	if (argc < 1) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
-	if (argc > 1) {
-		MTS (val);
-		MFS (val);
-	} else {
-		MFS (val);
+	switch (reg) {
+	case 0x1:
+		if (argc > 2) {
+			MTS (val, rmsr);
+			NOP;
+			MFS (val, rmsr);
+
+		} else {
+			MFS (val, rmsr);
+		}
+		puts ("MSR");
+		break;
+	case 0x3:
+		MFS (val, rear);
+		puts ("EAR");
+		break;
+	case 0x5:
+		MFS (val, resr);
+		puts ("ESR");
+		break;
+	default:
+		return 1;
 	}
-	printf ("rmsr: 0x%08lx\n", val);
+	printf (": 0x%08lx\n", val);
 	return 0;
 }
 
@@ -388,7 +407,11 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 		" 2 - blocking data write\n"
 		" 3 - blocking control write\n");
 
-U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
-	    "rmsr    - read MSR register\n", "- read MSR register.\n");
+U_BOOT_CMD (rspr, 3, 1, do_rspr,
+		"rmsr    - read/write special purpose register\n",
+		"- reg_num [write value] read/write special purpose register\n"
+		" 0 - MSR - Machine status register\n"
+		" 1 - EAR - Exception address register\n"
+		" 2 - ESR - Exception status register\n");
 
 #endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index 87ecbeaa4..d76b05a52 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -30,9 +30,9 @@ void _hw_exception_handler (void)
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	MFSEAR(address);
+	MFS (address, rear);
 	/* loading excetpion state register ESR */
-	MFSESR(state);
+	MFS (state, resr);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 8302ed885..f10f89c94 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -49,23 +49,18 @@
 
 /* CPU dependent */
 /* machine status register */
-#define MFS(val) \
-	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
+#define MFS(val, reg) \
+	__asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
 
-#define MTS(val) \
-	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
-
-/* exception status register */
-#define MFSEAR(val) \
-	__asm__ __volatile ("mfs %0,rear":"=r" (val));
-
-#define MFSESR(val) \
-	__asm__ __volatile ("mfs %0,resr":"=r" (val));
+#define MTS(val, reg) \
+	__asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
 
 /* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
 
+#define NOP	__asm__ __volatile__ ("nop");
+
 /* use machine status registe USE_MSR_REG */
 #ifdef XILINX_USE_MSR_INSTR
 #define MSRSET(val) \

From 7d98ba770a7eaefa29ce927f31a0956df85bf650 Mon Sep 17 00:00:00 2001
From: Piotr Kruszynski <ppk@semihalf.com>
Date: Thu, 10 May 2007 16:55:52 +0200
Subject: [PATCH 35/38] [Motion-PRO] Add MTD and JFFS2 support, also add
 default partition definition.

---
 include/configs/motionpro.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index f1f7e2ba0..e6e0eb1ff 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -51,6 +51,7 @@
 				CFG_CMD_PING	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_FAT	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_EEPROM)
@@ -260,6 +261,14 @@
 #define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 #define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
 
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=motionpro-0"
+#define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
+					"13m(fs),2m(kernel),256k(uboot)," \
+					"64k(env),64k(dtb),-(user_data)"
 
 /*
  * IDE/ATA configuration

From d62f64cc23a940eafe712c776b3249e4160753d1 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 16 May 2007 00:13:33 +0200
Subject: [PATCH 36/38] Coding Style Cleanup, new CHANGELOG

---
 CHANGELOG               | 252 ++++++++++++++++++++++++++++++++++++++++
 drivers/systemace.c     |   2 +-
 include/configs/ml401.h |   4 +-
 3 files changed, 255 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 184e9418c..cdcb9870e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,231 @@
+commit 7d98ba770a7eaefa29ce927f31a0956df85bf650
+Author: Piotr Kruszynski <ppk@semihalf.com>
+Date:	Thu May 10 16:55:52 2007 +0200
+
+    [Motion-PRO] Add MTD and JFFS2 support, also add default partition
+    definition.
+
+commit e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue May 8 15:57:43 2007 +0200
+
+    add: reading special purpose registers
+
+commit 1a50f164beb065f360fbddb76029607d6b099698
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue May 8 14:52:52 2007 +0200
+
+    add: Microblaze V5 exception handling
+
+commit ab874d5047e5d30dbc1e517ff26083efffa98ecb
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue May 8 14:39:11 2007 +0200
+
+    add: FSL control read and write
+
+commit de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3
+Author: Piotr Kruszynski <ppk@semihalf.com>
+Date:	Tue May 8 13:05:44 2007 +0200
+
+    [Motion-PRO] Add support for I2C, EEPROM and RTC.
+
+commit fa5c2ba123b1bf88455bfc21db5e786ca045029d
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue May 8 10:23:56 2007 +0200
+
+    [Motion-PRO] Add ATA support. Add CF-booting commands to the default
+    environment.
+
+commit 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue May 8 09:39:12 2007 +0200
+
+    [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. This
+    eliminates networking problems in Linux (timeouts).
+
+commit 1f1369c34b629be94702684d41d3fddf0f6193e7
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue May 8 09:21:57 2007 +0200
+
+    [Motion-PRO] Enable Flat Device Tree support and modify default environment
+    to allow booting of FDT-expecting kernels.
+
+commit fb05f6da35ea1c15c553abe6f23f656bf18dc5db
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 23:58:31 2007 +0200
+
+    new: USE_MSR_INTR support
+
+commit 008861a2f3ef2c062744d733787c7e530a1b8761
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Mon May 7 22:36:15 2007 +0200
+
+    [MPC5xxx] There are networking problems on the Motion-PRO board with
+    current PHY initalization code (tftp timeouts all the time). This commit
+    temporarily disables PHY initalization sequence to make the networking
+    operational, until a fix is found.
+
+commit abca901869c3760b6c5fecb825db6c1d91a78a93
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon May 7 22:10:36 2007 +0200
+
+    Get rid of duplicated file (see include/configs/sbc8560.h instead)
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 207b7b2c9d9752e0f6478c30c29b7087f6e6cbb6
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon May 7 22:07:08 2007 +0200
+
+    Get rid of duplicated file (see doc/README.SBC8560 instead)
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a7bac7e9b57ba948051beb19ec5be3a75ce75383
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 19:43:10 2007 +0200
+
+    fix: read and write MSR - repair number of parameters
+
+commit 19bf1fbad7f19d5a120be9b1daf136e052fcab39
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 19:33:51 2007 +0200
+
+    new: fsl interrupt support
+    FSL_Has_data is connected to INTC.
+
+commit 792032baa7d625e34c981ab6df521911bd8dc861
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 19:30:12 2007 +0200
+
+    fix: interrupt handler
+    remove asm code
+
+commit f3f001a341ef185d0f13841be5b5dc3395aacc31
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 19:25:08 2007 +0200
+
+    fix: remove asm code
+
+commit fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 19:12:43 2007 +0200
+
+    fix: clean interrupt
+
+commit 42efed6130c8fcf7da881385b5427065d2801757
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 17:22:25 2007 +0200
+
+    fix: interrupt handler for multiple sources
+
+commit 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Mon May 7 17:11:09 2007 +0200
+
+    new: add writing to msr register
+
+commit ac4cd59d59c9bf3f89cb7a344abf8184d678f562
+Author: Timur Tabi <timur@freescale.com>
+Date:	Sat May 5 08:12:30 2007 +0200
+
+    5xxx: write MAC address to mac-address and local-mac-address
+
+    Some device trees have a mac-address property, some have local-mac-address,
+    and some have both.  To support all of these device trees, ftp_cpu_setup()
+    should write the MAC address to mac-address and local-mac-address, if they
+    exist.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Acked-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2
+Author: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
+Date:	Sun Apr 29 14:01:54 2007 +0200
+
+    [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message
+
+    MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
+    message. Use PVR to distinguish between the two variants, and print proper CPU
+    information.
+
+    Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
+    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 4ec5bd55ed1ffa91a774af298769621f4fbb18c1
+Author: Ladislav Michl <ladis@linux-mips.org>
+Date:	Wed Apr 25 16:01:26 2007 +0200
+
+    [PATCH] simplify silent console
+
+    Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit b7598a43f2b421a713d8135e98a42c37d9eb9df0
+Author: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+Date:	Mon Apr 23 15:30:39 2007 +0200
+
+    [PATCH] Avoid assigning PCI resources from zero address
+
+    If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE
+    core complains and IDE drivers fails to work.  Also, assigning zero to a BAR
+    was illegal according to PCI 2.1 (the later revisions seem to have excluded the
+    sentence about "0" being considered an invalid address) -- so, use a reasonable
+    starting value of 0x1000 (that's what the most Linux archs are using).
+
+    Alternatively, one might have fixed the calls to pci_set_region() individually
+    (some code even seems to have taken care of this issue) but that would have
+    been a lot more work. :-)
+
+    Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 9ffd451afeb08e5be7ddae680487ec962b2bca25
+Author: Jeffrey Mann <mannj@embeddedplanet.com>
+Date:	Mon Apr 23 14:00:11 2007 +0200
+
+    [patch] setenv(...) can delete environmentalvariables
+
+    update setenv() function so that entering a NULL value for the
+    variable's value will delete the environmental variable
+
+    Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit ebd0a0ae05a44769c4e27458ad4e9f3438250443
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Mon Apr 23 13:54:24 2007 +0200
+
+    [patch] use unsigned char in smc91111 driver for mac
+
+    the v_mac variable in the smc91111 driver is declared as a signed char ...
+    this causes problems when one of the bytes in the MAC is "signed" like 0xE0
+    because when it gets printed out, you get a display like:
+    0xFFFFFFE0 and that's no good
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ffc50f9bb194343c6303517a517708457a5eb6b8
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat May 5 18:54:42 2007 +0200
+
+    new: FSL and MSR support #2
+
+commit f7e2e0eb0668136305f78bb9c21be79b48a34247
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat May 5 18:27:16 2007 +0200
+
+    new: FSL and MSR support
+
+commit 2f15278c2eb911c668b4fe562130b78cf554d139
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat May 5 18:23:11 2007 +0200
+
+    Coding stylke cleanup; update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 885ec89b648a899a2f32393fd3ffd9f7234c4402
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat May 5 18:05:02 2007 +0200
@@ -167,6 +395,12 @@ Date:	Sun Apr 29 14:13:01 2007 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 144876a380f5756f57412caf74c1d6dc201dd796
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue Apr 24 23:01:02 2007 +0200
+
+    [PATCH] MTD partition support, JFFS2 support
+
 commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb
 Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 Date:	Tue Apr 24 14:03:45 2007 +0200
@@ -400,6 +634,24 @@ Date:	Mon Apr 23 12:00:22 2007 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 32556443840f127170e4baa8bdd5b567039f6c36
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Apr 21 21:07:22 2007 +0200
+
+    [PATCH] SystemACE support for Microblaze
+
+commit 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Apr 21 21:02:40 2007 +0200
+
+    16bit read/write little endian
+
+commit 9d1d6a34d26c5933bc097ce73c9348f95573cdd4
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Sat Apr 21 20:53:31 2007 +0200
+
+    Change ML401 parameters - Xilinx BSP
+
 commit 2e343b9a57f32e1bd08c35c9976910333fb4e13d
 Author: Ed Swarthout <Ed.Swarthout@freescale.com>
 Date:	Wed Feb 28 05:37:29 2007 -0600
diff --git a/drivers/systemace.c b/drivers/systemace.c
index c9fd5f167..7d82c27c6 100644
--- a/drivers/systemace.c
+++ b/drivers/systemace.c
@@ -211,7 +211,7 @@ static unsigned long systemace_read(int dev, unsigned long start,
 		/* Write sector count | ReadMemCardData. */
 		ace_writew((trans & 0xff) | 0x0300, 0x14);
 
-/* 
+/*
  * For FPGA configuration via SystemACE is reset unacceptable
  * CFGDONE bit in STATUSREG is not set to 1.
  */
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 4cfe802c3..3db287784 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -37,7 +37,7 @@
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 /* setting reset address */
-//#define	CFG_RESET_ADDRESS	TEXT_BASE
+/*#define	CFG_RESET_ADDRESS	TEXT_BASE*/
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
@@ -99,7 +99,7 @@
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
 /* start of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
 
 /* monitor code */
 #define	SIZE			0x40000

From a7676ea7732f3c596805079fed7e5c9fac652cfc Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 16 May 2007 01:16:53 +0200
Subject: [PATCH 37/38] Minor Coding Style cleanup, update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 CHANGELOG                     | 124 ++++++++++++++++++++++++++++++++++
 include/configs/MPC8313ERDB.h |  40 +++++------
 2 files changed, 140 insertions(+), 24 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index cdcb9870e..24d805eb3 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,9 @@
+commit d62f64cc23a940eafe712c776b3249e4160753d1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed May 16 00:13:33 2007 +0200
+
+    Coding Style Cleanup, new CHANGELOG
+
 commit 7d98ba770a7eaefa29ce927f31a0956df85bf650
 Author: Piotr Kruszynski <ppk@semihalf.com>
 Date:	Thu May 10 16:55:52 2007 +0200
@@ -295,6 +301,14 @@ Date:	Fri May 4 10:02:33 2007 +0200
 
     Signed-off-by: Wolfgang Denk <wd@denx.de>
 
+commit 068aab660bc3912b930be5540e6b3f3fd6ad3c96
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu May 3 19:43:52 2007 -0500
+
+    mpc83xx: fix trivial error in MAKEALL
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
 commit c64a89d6ce8584b9fc64f4e85da9ecac3cfc2c2a
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu May 3 16:34:41 2007 +0200
@@ -376,6 +390,33 @@ Date:	Wed Feb 7 15:28:04 2007 -0600
     Signed-off-by: James Yang <James.Yang@freescale.com>
     Signed-off-by: Jon Loeliger <jdl@freescale.com>
 
+commit f64702b7fc8f8df39d31add770df6e372f9e9ce3
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Apr 30 13:59:50 2007 -0500
+
+    Fix memory initialization on MPC8349E-mITX
+
+    Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
+    This allows ddr->sdram_clk_cntl to be properly initialized.  This is necessary
+    on some ITX boards, notably those with a revision 3.1 CPU.
+
+    Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
+    ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Acked-by: Michael Benedict <MBenedict@twacs.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 54b2d434ae9d01787936f34fe1759cf3d7624ae3
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Mon Apr 30 15:26:21 2007 -0500
+
+    mpc83xx: replace elaborate boottime verbosity with 'clocks' command
+
+    and fix CPU: to align with Board: display text.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
 commit c1ab82669d9525998c34e802a12cad662723f22a
 Author: James Yang <James.Yang@freescale.com>
 Date:	Fri Mar 16 13:02:53 2007 -0500
@@ -395,6 +436,12 @@ Date:	Sun Apr 29 14:13:01 2007 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 5c5d3242935cf3543af01142627494434834cf98
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Apr 25 12:34:38 2007 -0500
+
+    mpc83xx: minor fixups for 8313rdb introduction
+
 commit 144876a380f5756f57412caf74c1d6dc201dd796
 Author: Michal Simek <monstr@monstr.eu>
 Date:	Tue Apr 24 23:01:02 2007 +0200
@@ -626,6 +673,71 @@ Date:	Thu Dec 14 14:14:55 2006 +0800
     board.
     Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
 
+commit 96b8a05432f346f36493535c85320b70ec9c7c1b
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:54:15 2007 -0500
+
+    mpc83xx: Add MPC8313ERDB support.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 49ea3b6eafe606285ae4d5c378026153dde53200
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:34:21 2007 -0500
+
+    mpc83xx: Add generic PCI setup code.
+
+    Board code can now request the generic setup code rather than having to
+    copy-and-paste it for themselves.  Boards should be converted to use this
+    once they're tested with it.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 7c98e5193e93df6b9b651851d54b638a61ebb0ea
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:34:19 2007 -0500
+
+    mpc83xx: Add 831x support to speed.c.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 0f253283a32d91e06844d7f87f9b33f4f4fbce8f
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:34:18 2007 -0500
+
+    mpc83xx: Add 831x support to global_data.h
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 95e7ef897e54591e615fc1b458b74c286fe1fb06
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:34:16 2007 -0500
+
+    mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().
+
+    Rather than misleadingly define PVR_83xx as the specific type of 83xx
+    being built for, the PVR of each core revision is defined. checkcpu() now
+    prints the core that it detects, rather than aborting if it doesn't find
+    what it thinks it wants.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit a35b0c4950d84cf9e3a9e32b916135956d1ac636
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:34:15 2007 -0500
+
+    mpc83xx: Recognize SPR values for MPC8311 and MPC8313.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit d87c57b201b4572d16f1b642998faa00c9912b16
+Author: Scott Wood <scottwood@freescale.com>
+Date:	Mon Apr 16 14:31:55 2007 -0500
+
+    mpc83xx: Add register definitions for MPC831x.
+
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
 commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522
 Author: Stefan Roese <sr@denx.de>
 Date:	Mon Apr 23 12:00:22 2007 +0200
@@ -1134,6 +1246,18 @@ Date:	Fri Apr 13 08:02:24 2007 +0200
     Signed-of-by: Greg Lopp <lopp@pobox.com>
     Acked-by: Grant Likely <grant.likely@secretlab.ca>
 
+commit 6fbf261f8df294e589cfadebebe5468e3c0f29e9
+Author: Xie Xiaobo <r63061@freescale.com>
+Date:	Fri Mar 9 19:08:25 2007 +0800
+
+    Fix two bugs for MPC83xx DDR2 controller SPD Init
+
+    There are a few bugs in the cpu/mpc83xx/spd_sdram.c
+    the first bug is that the picos_to_clk routine introduces a huge
+    rounding error in 83xx.
+    the second bug is that the mode register write recovery field is
+    tWR-1, not tWR >> 1.
+
 commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13
 Author: Jeffrey Mann <mannj@embeddedplanet.com>
 Date:	Thu Apr 12 14:15:59 2007 +0200
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 11858bfb8..697631345 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -18,14 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * History
- * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
- *           Initialized
- * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
- *           Code Cleanup
- * 20070410: Scott Wood <scottwood@freescale.com>
- *           More cleanup
  */
 /*
  * mpc8313epb board configuration file
@@ -154,10 +146,10 @@
 #define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
 #define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |    /* flash Base address */ \
-				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
-				BR_V)		     /* valid */
-#define CFG_OR0_PRELIM		( 0xFF000000         /* 16 MByte */ \
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
+				BR_V)			/* valid */
+#define CFG_OR0_PRELIM		( 0xFF000000		/* 16 MByte */ \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
@@ -197,20 +189,20 @@
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */
 
-#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB refresh timer prescal, 266MHz/32 */
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */ 	/* LB refresh timer prescal, 266MHz/32 */
 
 /* drivers/nand/nand.c */
-#define CFG_NAND_BASE		0xE2800000 /* 0xF0000000 */
+#define CFG_NAND_BASE		0xE2800000	/* 0xF0000000 */
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CFG_BR1_PRELIM		( CFG_NAND_BASE \
-				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
-				| BR_PS_8            /* Port Size = 8 bit */ \
-				| BR_MS_FCM          /* MSEL = FCM */ \
-				| BR_V )             /* valid */
-#define CFG_OR1_PRELIM		( 0xFFFF8000	/* length 32K */ \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000		/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
@@ -378,7 +370,7 @@
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args */
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
 #define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
@@ -395,7 +387,7 @@
 #define CFG_CACHELINE_SIZE	32
 #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define CFG_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
 #ifdef CFG_66MHZ
 
@@ -439,12 +431,12 @@
 	HRCWH_LALE_NORMAL)
 
 /* System IO Config */
-#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB Phy  */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+#define CFG_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
 
 #define CFG_HID0_INIT	0x000000000
 #define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-                         HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+			 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
 #define CFG_HID2 HID2_HBE
 

From 70124c2602ae2d4c5d3dba05b482d91548242de8 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 16 May 2007 14:49:12 +0200
Subject: [PATCH 38/38] Fix compile problem cause my Microblaze merge

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 common/cmd_mfsl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 26786aa8c..ffa266693 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -29,9 +29,9 @@
 #include <common.h>
 #include <config.h>
 #include <command.h>
-#include <asm/asm.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_MFSL)
+#include <asm/asm.h>
 
 int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {