diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index d3c223360..0b16b5050 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -70,8 +70,6 @@ void dflush(void);
 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
 	/* disable caching on DDR2 */
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-
 void board_add_ram_info(int use_default)
 {
 	PPC4xx_SYS_INFO board_cfg;
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index ed493f1a7..2bfcba19b 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -31,9 +31,9 @@
 #include <asm/mmu.h>
 
 typedef struct region {
-	unsigned long base;
-	unsigned long size;
-	unsigned long tlb_word2_i_value;
+	u64 base;
+	u32 size;
+	u32 tlb_word2_i_value;
 } region_t;
 
 void remove_tlb(u32 vaddr, u32 size)
@@ -182,10 +182,10 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
 	asm("isync");
 }
 
-static int add_tlb_entry(unsigned long phys_addr,
-			 unsigned long virt_addr,
-			 unsigned long tlb_word0_size_value,
-			 unsigned long tlb_word2_i_value)
+static int add_tlb_entry(u64 phys_addr,
+			 u32 virt_addr,
+			 u32 tlb_word0_size_value,
+			 u32 tlb_word2_i_value)
 {
 	int i;
 	unsigned long tlb_word0_value;
@@ -204,7 +204,8 @@ static int add_tlb_entry(unsigned long phys_addr,
 	/* Second, create the TLB entry */
 	tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
 		TLB_WORD0_TS_0 | tlb_word0_size_value;
-	tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
+	tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) |
+		TLB_WORD1_ERPN_ENCODE(phys_addr >> 32);
 	tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 		TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 		TLB_WORD2_W_DISABLE | tlb_word2_i_value |
@@ -228,10 +229,10 @@ static int add_tlb_entry(unsigned long phys_addr,
 	return 0;
 }
 
-static void program_tlb_addr(unsigned long phys_addr,
-			     unsigned long virt_addr,
-			     unsigned long mem_size,
-			     unsigned long tlb_word2_i_value)
+static void program_tlb_addr(u64 phys_addr,
+			     u32 virt_addr,
+			     u32 mem_size,
+			     u32 tlb_word2_i_value)
 {
 	int rc;
 	int tlb_i;
@@ -331,7 +332,7 @@ static void program_tlb_addr(unsigned long phys_addr,
  * Common usage for boards with SDRAM DIMM modules to dynamically
  * configure the TLB's for the SDRAM
  */
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
+void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 {
 	region_t region_array;
 
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 5af22af99..49d6860fc 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -549,14 +549,14 @@ extern int num_tlb_entries;
 /*----------------------------------------------------------------------------+
 | TLB specific defines.
 +----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xF0000000
-#define TLB_16MB_ALIGN_MASK  0xFF000000
-#define TLB_1MB_ALIGN_MASK   0xFFF00000
-#define TLB_256KB_ALIGN_MASK 0xFFFC0000
-#define TLB_64KB_ALIGN_MASK  0xFFFF0000
-#define TLB_16KB_ALIGN_MASK  0xFFFFC000
-#define TLB_4KB_ALIGN_MASK   0xFFFFF000
-#define TLB_1KB_ALIGN_MASK   0xFFFFFC00
+#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
+#define TLB_16MB_ALIGN_MASK  0xFFF000000ULL
+#define TLB_1MB_ALIGN_MASK   0xFFFF00000ULL
+#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
+#define TLB_64KB_ALIGN_MASK  0xFFFFF0000ULL
+#define TLB_16KB_ALIGN_MASK  0xFFFFFC000ULL
+#define TLB_4KB_ALIGN_MASK   0xFFFFFF000ULL
+#define TLB_1KB_ALIGN_MASK   0xFFFFFFC00ULL
 #define TLB_256MB_SIZE       0x10000000
 #define TLB_16MB_SIZE        0x01000000
 #define TLB_1MB_SIZE         0x00100000
@@ -697,7 +697,7 @@ unsigned long mftlb1(unsigned long index);
 unsigned long mftlb2(unsigned long index);
 unsigned long mftlb3(unsigned long index);
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void remove_tlb(u32 vaddr, u32 size);
 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
 #endif /* __ASSEMBLY__ */
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index c86a15069..466ca926b 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -42,8 +42,6 @@
 
 #define CACHE_POST_SIZE	1024
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-
 int cache_post_test1 (int tlb, void *p, int size);
 int cache_post_test2 (int tlb, void *p, int size);
 int cache_post_test3 (int tlb, void *p, int size);