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ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia 

The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Gary Jennejohn 2007-08-31 15:21:46 +02:00 committed by Stefan Roese
parent 9c02defc29
commit 81b73dec16
3 changed files with 12 additions and 2 deletions
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3
board/amcc/sequoia/init.S
View File

@ -126,6 +126,9 @@ tlbtab:
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry PCI IO Space - from sr@denx.de */
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

8
drivers/pci_auto.c
View File

@ -28,6 +28,11 @@
#define PCIAUTO_IDE_MODE_MASK 0x05
/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CFG_PCI_CACHE_LINE_SIZE
#define CFG_PCI_CACHE_LINE_SIZE 8
#endif
/*
*
*/
@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose,
}
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
CFG_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

3
include/configs/sequoia.h
View File

@ -400,7 +400,8 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/