Changed API name to coloured_led.h
Removed code using deprecated ifdef CONFIG_BOOTBINFUNC Tidied other cpu/arm920t/start.S code
This commit is contained in:
Peter Pearse
parent
9f5c3d3720
commit
80767a6cea
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@ -66,7 +66,7 @@ void red_LED_off(void)
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}
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void LED_init (void)
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void coloured_LED_init (void)
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{
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AT91PS_PIO PIOB = AT91C_BASE_PIOB;
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AT91PS_PMC PMC = AT91C_BASE_PMC;
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@ -27,7 +27,7 @@
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#include <config.h>
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#include <version.h>
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#include <asm/led.h>
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#include <asm/coloured_led.h>
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/*
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*************************************************************************
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@ -39,7 +39,7 @@
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.globl _start
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_start: b reset
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_start: b start_code
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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@ -62,7 +62,7 @@ _fiq: .word fiq
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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* Startup Code (called from the ARM reset exception vector)
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*
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* do important init only if we don't start from memory!
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* relocate armboot to ram
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@ -104,10 +104,10 @@ FIQ_STACK_START:
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/*
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* the actual reset code
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* the actual start code
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*/
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reset:
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start_code:
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/*
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* set the cpu to SVC32 mode
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*/
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@ -115,59 +115,13 @@ reset:
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* if board has a red led use it to show U-Boot is running
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*/
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bl coloured_LED_init
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bl red_LED_on
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#ifdef CONFIG_AT91RM9200
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#ifdef CONFIG_BOOTBINFUNC
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/* code based on entry.S from ATMEL */
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#define AT91C_BASE_CKGR 0xFFFFFC20
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#define CKGR_MOR 0
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/* Get the CKGR Base Address */
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ldr r1, =AT91C_BASE_CKGR
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/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
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/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
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ldr r0, =0x0000FF01
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str r0, [r1, #CKGR_MOR]
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/* Add loop to compensate Main Oscillator startup time */
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ldr r0, =0x00000010
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LoopOsc:
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subs r0, r0, #1
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bhi LoopOsc
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/* scratch stack */
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ldr r1, =0x00204000
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/* Insure word alignment */
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bic r1, r1, #3
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/* Init stack SYS */
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mov sp, r1
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#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
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/*
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* This does a lot more than just set up the memory, which
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* is why it's called lowlevelinit
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*/
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bl lowlevelinit /* in memsetup.S */
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bl icache_enable;
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/* ------------------------------------
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* Read/modify/write CP15 control register
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* -------------------------------------
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* read cp15 control register (cp15 r1) in r0
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* ------------------------------------
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*/
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mrc p15, 0, r0, c1, c0, 0
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/* Reset bit :Little Endian end fast bus mode */
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ldr r3, =0xC0000080
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/* Set bit :Asynchronous clock mode, Not Fast Bus */
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ldr r4, =0xC0000000
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bic r0, r0, r3
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orr r0, r0, r4
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/* write r0 in cp15 control register (cp15 r1) */
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mcr p15, 0, r0, c1, c0, 0
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#endif /* CONFIG_BOOTBINFUNC */
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/*
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* relocate exeception table
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* relocate exception table
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*/
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ldr r0, =_start
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ldr r1, =0x0
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@ -179,19 +133,20 @@ copyex:
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bne copyex
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#endif
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/* turn off the watchdog */
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#if defined(CONFIG_S3C2400)
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# define pWTCON 0x15300000
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# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
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# define CLKDIVN 0x14800014 /* clock divisor register */
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#elif defined(CONFIG_S3C2410)
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# define pWTCON 0x53000000
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# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
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# define INTSUBMSK 0x4A00001C
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# define CLKDIVN 0x4C000014 /* clock divisor register */
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#endif
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#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
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/* turn off the watchdog */
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# if defined(CONFIG_S3C2400)
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# define pWTCON 0x15300000
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# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
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# define CLKDIVN 0x14800014 /* clock divisor register */
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#else
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# define pWTCON 0x53000000
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# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
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# define INTSUBMSK 0x4A00001C
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# define CLKDIVN 0x4C000014 /* clock divisor register */
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# endif
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ldr r0, =pWTCON
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mov r1, #0x0
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str r1, [r0]
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@ -224,25 +179,7 @@ copyex:
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#endif
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#ifdef CONFIG_AT91RM9200
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#ifdef CONFIG_BOOTBINFUNC
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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ldr r2, _armboot_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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#endif /* CONFIG_BOOTBINFUNC */
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#else
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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@ -282,27 +219,6 @@ clbss_l:str r2, [r0] /* clear loop... */
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cmp r0, r1
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ble clbss_l
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#if 0
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/* try doing this stuff after the relocation */
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ldr r0, =pWTCON
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mov r1, #0x0
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str r1, [r0]
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/*
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* mask all IRQs by setting all bits in the INTMR - default
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*/
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mov r1, #0xffffffff
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ldr r0, =INTMR
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str r1, [r0]
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/* FCLK:HCLK:PCLK = 1:2:4 */
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/* default FCLK is 120 MHz ! */
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ldr r0, =CLKDIVN
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mov r1, #3
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str r1, [r0]
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/* END stuff after relocation */
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#endif
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ldr pc, _start_armboot
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_start_armboot: .word start_armboot
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