sh: Renesas Solutions SH7763RDP board support
SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC. In this patch, support SCIF, NOR Flash, and Ethernet. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
60179098a9
commit
7faddaecea
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@ -718,6 +718,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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MS7722SE SH7722
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R7780MP SH7780
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R2DPlus SH7751R
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SH7763RDP SH7763
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Mark Jonas <mark.jonas@de.bosch.com>
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1
MAKEALL
1
MAKEALL
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@ -749,6 +749,7 @@ LIST_sh4=" \
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Migo-R \
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r7780mp \
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r2dplus \
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sh7763rdp \
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"
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LIST_sh=" \
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5
Makefile
5
Makefile
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@ -2941,6 +2941,11 @@ r2dplus_config : unconfig
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@echo "#define CONFIG_R2DPLUS 1" >> include/config.h
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@./mkconfig -a $(@:_config=) sh sh4 r2dplus
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sh7763rdp_config : unconfig
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@ >include/config.h
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@echo "#define CONFIG_SH7763RDP 1" >> include/config.h
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@./mkconfig -a $(@:_config=) sh sh4 sh7763rdp
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#========================================================================
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# SPARC
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#========================================================================
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@ -0,0 +1,47 @@
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#
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# Copyright (C) 2008 Renesas Solutions Corp.
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# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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# Copyright (C) 2007 Kenati Technologies, Inc.
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#
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# board/sh7763rdp/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := sh7763rdp.o
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SOBJS := lowlevel_init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,11 @@
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#
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# board/sh7763rdp/config.mk
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#
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# TEXT_BASE refers to image _after_ relocation.
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#
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# NOTE: Must match value used in u-boot.lds (in this directory).
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#
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TEXT_BASE = 0x8FFC0000
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# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT
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@ -0,0 +1,351 @@
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2007 Kenati Technologies, Inc.
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*
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* board/sh7763rdp/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
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mov.l WDTCSR_D, r0
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mov.l r0, @r1
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mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
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mov.l WDTST_D, r0
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mov.l r0, @r1
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mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
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mov.l WDTBST_D, r0
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mov.l r0, @r1
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mov.l CCR_A, r1 /* Address of Cache Control Register */
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mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
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mov.l r0, @r1
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mov.l MMUCR_A, r1 /* Address of MMU Control Register */
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mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */
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mov.l r0, @r1
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mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */
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mov.l MSTPCR0_D, r0
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mov.l r0, @r1
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mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */
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mov.l MSTPCR1_D, r0
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mov.l r0, @r1
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mov.l RAMCR_A,r1
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mov.l RAMCR_D,r0
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mov.l r0, @r1
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mov.l MMSELR_A,r1
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mov.l MMSELR_D,r0
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synco
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mov.l r0, @r1
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mov.l @r1,r2 /* execute two reads after setting MMSELR*/
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mov.l @r1,r2
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synco
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/* issue memory read */
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mov.l DDRSD_START_A,r1 /* memory address to read*/
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mov.l @r1,r0
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synco
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mov.l MIM8_A,r1
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mov.l MIM8_D,r0
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mov.l r0,@r1
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mov.l MIMC_A,r1
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mov.l MIMC_D1,r0
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mov.l r0,@r1
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mov.l STRC_A,r1
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mov.l STRC_D,r0
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mov.l r0,@r1
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mov.l SDR4_A,r1
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mov.l SDR4_D,r0
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mov.l r0,@r1
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mov.l MIMC_A,r1
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mov.l MIMC_D2,r0
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mov.l r0,@r1
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nop
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nop
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nop
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mov.l SCR4_A,r1
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mov.l SCR4_D3,r0
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mov.l r0,@r1
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mov.l SCR4_A,r1
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mov.l SCR4_D2,r0
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mov.l r0,@r1
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mov.l SDMR02000_A,r1
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mov.l SDMR02000_D,r0
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mov.l r0,@r1
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mov.l SDMR00B08_A,r1
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mov.l SDMR00B08_D,r0
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mov.l r0,@r1
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mov.l SCR4_A,r1
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mov.l SCR4_D2,r0
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mov.l r0,@r1
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mov.l SCR4_A,r1
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mov.l SCR4_D4,r0
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mov.l r0,@r1
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nop
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nop
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nop
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nop
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mov.l SCR4_A,r1
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mov.l SCR4_D4,r0
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mov.l r0,@r1
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nop
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nop
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nop
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nop
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mov.l SDMR00308_A,r1
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mov.l SDMR00308_D,r0
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mov.l r0,@r1
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mov.l MIMC_A,r1
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mov.l MIMC_D3,r0
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mov.l r0,@r1
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mov.l SCR4_A,r1
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mov.l SCR4_D1,r0
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mov.l DELAY60_D,r3
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delay_loop_60:
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mov.l r0,@r1
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dt r3
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bf delay_loop_60
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nop
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mov.l CCR_A, r1 /* Address of Cache Control Register */
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mov.l CCR_CACHE_D_2, r0
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mov.l r0, @r1
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bsc_init:
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mov.l BCR_A, r1
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mov.l BCR_D, r0
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mov.l r0, @r1
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mov.l CS0BCR_A, r1
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mov.l CS0BCR_D, r0
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mov.l r0, @r1
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mov.l CS1BCR_A,r1
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mov.l CS1BCR_D,r0
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mov.l r0,@r1
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mov.l CS2BCR_A, r1
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mov.l CS2BCR_D, r0
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mov.l r0, @r1
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mov.l CS4BCR_A, r1
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mov.l CS4BCR_D, r0
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mov.l r0, @r1
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mov.l CS5BCR_A, r1
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mov.l CS5BCR_D, r0
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mov.l r0, @r1
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mov.l CS6BCR_A, r1
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mov.l CS6BCR_D, r0
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mov.l r0, @r1
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mov.l CS0WCR_A, r1
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mov.l CS0WCR_D, r0
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mov.l r0, @r1
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mov.l CS1WCR_A, r1
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mov.l CS1WCR_D, r0
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mov.l r0, @r1
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mov.l CS2WCR_A, r1
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mov.l CS2WCR_D, r0
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mov.l r0, @r1
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mov.l CS4WCR_A, r1
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mov.l CS4WCR_D, r0
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mov.l r0, @r1
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mov.l CS5WCR_A, r1
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mov.l CS5WCR_D, r0
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mov.l r0, @r1
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mov.l CS6WCR_A, r1
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mov.l CS6WCR_D, r0
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mov.l r0, @r1
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mov.l CS5PCR_A, r1
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mov.l CS5PCR_D, r0
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mov.l r0, @r1
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mov.l CS6PCR_A, r1
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mov.l CS6PCR_D, r0
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mov.l r0, @r1
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mov.l DELAY200_D,r3
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delay_loop_200:
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dt r3
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bf delay_loop_200
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nop
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mov.l PSEL0_A,r1
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mov.l PSEL0_D,r0
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mov.w r0,@r1
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mov.l PSEL1_A,r1
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mov.l PSEL1_D,r0
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mov.w r0,@r1
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mov.l ICR0_A,r1
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mov.l ICR0_D,r0
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mov.l r0,@r1
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stc sr, r0 /* BL bit off(init=ON) */
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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nop
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.align 2
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DELAY60_D: .long 60
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DELAY200_D: .long 17800
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CCR_A: .long 0xFF00001C
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MMUCR_A: .long 0xFF000010
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RAMCR_A: .long 0xFF000074
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/* Low power mode control */
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MSTPCR0_A: .long 0xFFC80030
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MSTPCR1_A: .long 0xFFC80038
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/* RWBT */
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WDTST_A: .long 0xFFCC0000
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WDTCSR_A: .long 0xFFCC0004
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WDTBST_A: .long 0xFFCC0008
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/* BSC */
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MMSELR_A: .long 0xFE600020
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BCR_A: .long 0xFF801000
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CS0BCR_A: .long 0xFF802000
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CS1BCR_A: .long 0xFF802010
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CS2BCR_A: .long 0xFF802020
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CS4BCR_A: .long 0xFF802040
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CS5BCR_A: .long 0xFF802050
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CS6BCR_A: .long 0xFF802060
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CS0WCR_A: .long 0xFF802008
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CS1WCR_A: .long 0xFF802018
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CS2WCR_A: .long 0xFF802028
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CS4WCR_A: .long 0xFF802048
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CS5WCR_A: .long 0xFF802058
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CS6WCR_A: .long 0xFF802068
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CS5PCR_A: .long 0xFF802070
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CS6PCR_A: .long 0xFF802080
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DDRSD_START_A: .long 0xAC000000
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/* INTC */
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ICR0_A: .long 0xFFD00000
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/* DDR I/F */
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MIM8_A: .long 0xFE800008
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MIMC_A: .long 0xFE80000C
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SCR4_A: .long 0xFE800014
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STRC_A: .long 0xFE80001C
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SDR4_A: .long 0xFE800034
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SDMR00308_A: .long 0xFE900308
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SDMR00B08_A: .long 0xFE900B08
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SDMR02000_A: .long 0xFE902000
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/* GPIO */
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PSEL0_A: .long 0xFFEF0070
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PSEL1_A: .long 0xFFEF0072
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CCR_CACHE_ICI_D:.long 0x00000800
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CCR_CACHE_D_2: .long 0x00000103
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MMU_CONTROL_TI_D:.long 0x00000004
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RAMCR_D: .long 0x00000200
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MSTPCR0_D: .long 0x00000000
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MSTPCR1_D: .long 0x00000000
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MMSELR_D: .long 0xa5a50000
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BCR_D: .long 0x00000000
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CS0BCR_D: .long 0x77777770
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CS1BCR_D: .long 0x77777670
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CS2BCR_D: .long 0x77777670
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CS4BCR_D: .long 0x77777670
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CS5BCR_D: .long 0x77777670
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CS6BCR_D: .long 0x77777670
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CS0WCR_D: .long 0x7777770F
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CS1WCR_D: .long 0x22000002
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CS2WCR_D: .long 0x7777770F
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CS4WCR_D: .long 0x7777770F
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CS5WCR_D: .long 0x7777770F
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CS6WCR_D: .long 0x7777770F
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CS5PCR_D: .long 0x77000000
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CS6PCR_D: .long 0x77000000
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ICR0_D: .long 0x00E00000
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MIM8_D: .long 0x00000000
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MIMC_D1: .long 0x01d10008
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MIMC_D2: .long 0x01d10009
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MIMC_D3: .long 0x01d10209
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SCR4_D1: .long 0x00000001
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SCR4_D2: .long 0x00000002
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SCR4_D3: .long 0x00000003
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SCR4_D4: .long 0x00000004
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STRC_D: .long 0x000f3980
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SDR4_D: .long 0x00000300
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SDMR00308_D: .long 0x00000000
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SDMR00B08_D: .long 0x00000000
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SDMR02000_D: .long 0x00000000
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PSEL0_D: .long 0x00000001
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PSEL1_D: .long 0x00000244
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SR_MASK_D: .long 0xEFFFFF0F
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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@ -0,0 +1,76 @@
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/*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
* Copyright (C) 2007 Kenati Technologies, Inc.
|
||||
*
|
||||
* board/sh7763rdp/sh7763rdp.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#define CPU_CMDREG 0xB1000006
|
||||
#define PDCR 0xffef0006
|
||||
#define PECR 0xffef0008
|
||||
#define PFCR 0xffef000a
|
||||
#define PGCR 0xffef000c
|
||||
#define PHCR 0xffef000e
|
||||
#define PJCR 0xffef0012
|
||||
#define PKCR 0xffef0014
|
||||
#define PLCR 0xffef0016
|
||||
#define PMCR 0xffef0018
|
||||
#define PSEL1 0xffef0072
|
||||
#define PSEL2 0xffef0074
|
||||
#define PSEL3 0xffef0076
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("BOARD: Renesas SH7763 RDP\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
vu_short dat;
|
||||
|
||||
*(vu_short *)(CPU_CMDREG) |= 0x0001;
|
||||
|
||||
/* GPIO Setting (eth1) */
|
||||
dat = *(vu_short *)(PSEL1);
|
||||
*(vu_short *)PSEL1 = ((dat & ~0xff00) | 0x2400);
|
||||
*(vu_short *)PFCR = 0;
|
||||
*(vu_short *)PGCR = 0;
|
||||
*(vu_short *)PHCR = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_memstart = CFG_SDRAM_BASE;
|
||||
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
|
||||
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void led_set_state (unsigned short value)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyrigth (c) 2007,2008
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||
OUTPUT_ARCH(sh)
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
Base address of internal SDRAM is 0x0C000000.
|
||||
Although size of SDRAM can be either 16 or 32 MBytes,
|
||||
we assume 16 MBytes (ie ignore upper half if the full
|
||||
32 MBytes is present).
|
||||
|
||||
NOTE: This address must match with the definition of
|
||||
TEXT_BASE in config.mk (in this directory).
|
||||
|
||||
*/
|
||||
. = 0x8C000000 + (64*1024*1024) - (256*1024);
|
||||
|
||||
PROVIDE (reloc_dst = .);
|
||||
|
||||
PROVIDE (_ftext = .);
|
||||
PROVIDE (_fcode = .);
|
||||
PROVIDE (_start = .);
|
||||
|
||||
.text :
|
||||
{
|
||||
cpu/sh4/start.o (.text)
|
||||
. = ALIGN(8192);
|
||||
common/environment.o (.ppcenv)
|
||||
. = ALIGN(8192);
|
||||
common/environment.o (.ppcenvr)
|
||||
. = ALIGN(8192);
|
||||
*(.text)
|
||||
. = ALIGN(4);
|
||||
} =0xFF
|
||||
PROVIDE (_ecode = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_etext = .);
|
||||
|
||||
|
||||
PROVIDE (_fdata = .);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_edata = .);
|
||||
|
||||
PROVIDE (_fgot = .);
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_egot = .);
|
||||
|
||||
PROVIDE (__u_boot_cmd_start = .);
|
||||
.u_boot_cmd :
|
||||
{
|
||||
*(.u_boot_cmd)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (__u_boot_cmd_end = .);
|
||||
|
||||
PROVIDE (reloc_dst_end = .);
|
||||
/* _reloc_dst_end = .; */
|
||||
|
||||
PROVIDE (bss_start = .);
|
||||
PROVIDE (__bss_start = .);
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (bss_end = .);
|
||||
|
||||
PROVIDE (_end = .);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Configuation settings for the Renesas SH7763RDP board
|
||||
*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SH7763RDP_H
|
||||
#define __SH7763RDP_H
|
||||
|
||||
#define CONFIG_SH 1
|
||||
#define CONFIG_SH4 1
|
||||
#define CONFIG_CPU_SH7763 1
|
||||
#define CONFIG_SH7763RDP 1
|
||||
#define __LITTLE_ENDIAN 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* SCIF */
|
||||
#define CFG_SCIF_CONSOLE 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_CONS_SCIF2 1
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
|
||||
#define CFG_PBSIZE 256 /* Buffer size for Console output */
|
||||
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
|
||||
#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments
|
||||
passed to kernel */
|
||||
#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
|
||||
settings for this board */
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
|
||||
#define CFG_RX_ETH_BUFFER (8)
|
||||
|
||||
/* SDRAM */
|
||||
#define CFG_SDRAM_BASE (0x8C000000)
|
||||
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
|
||||
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
|
||||
|
||||
/* Flash(NOR) */
|
||||
#define CFG_FLASH_BASE (0xA0000000)
|
||||
#define CFG_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
|
||||
#define CFG_MAX_FLASH_BANKS (1)
|
||||
#define CFG_MAX_FLASH_SECT (520)
|
||||
|
||||
/* U-boot setting */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
|
||||
#define CFG_MONITOR_LEN (128 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CFG_MALLOC_LEN (1024 * 1024)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_SIZE (256)
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#undef CFG_FLASH_QUIET_TEST
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CFG_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CFG_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
/* Use hardware flash sectors protection instead of U-Boot software protection */
|
||||
#undef CFG_FLASH_PROTECTION
|
||||
#undef CFG_DIRECT_FLASH_TFTP
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
|
||||
/* Offset of env Flash sector relative to CFG_FLASH_BASE */
|
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
|
||||
|
||||
/* Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
|
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
|
||||
|
||||
#endif /* __SH7763RDP_H */
|
||||
Loading…
Reference in New Issue