* Patch by Stefan Roese, 06 Apr 2005:
Updates for OCOTEA board: - Changed U-Boot size from 512kByte to 256kByte - Fixed flash driver to support boot from soldered user flash - Added README for switch from PIBS firmware to U-Boot
This commit is contained in:
stroese
parent
0a7c5391a0
commit
7ec2550238
10
CHANGELOG
10
CHANGELOG
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@ -2,6 +2,16 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patch by Stefan Roese, 06 Apr 2005:
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Updates for OCOTEA board:
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- Changed U-Boot size from 512kByte to 256kByte
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- Fixed flash driver to support boot from soldered user flash
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- Added README for switch from PIBS firmware to U-Boot
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* Patch by Travis Sawyer, 05 Apr 2005:
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- Change timer frequency for ppc 440 from 10 ms to 1 ms.
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Problem found by Andrew Wozniak.
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* Patch by Steven Scholz, 06 Apr 2005:
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- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
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- moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
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@ -30,7 +30,7 @@
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ifeq ($(ramsym),1)
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TEXT_BASE = 0x07FD0000
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else
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TEXT_BASE = 0xFFF80000
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TEXT_BASE = 0xFFFC0000
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endif
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2004
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* (C) Copyright 2004-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
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@ -43,7 +43,9 @@
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#define DEBUGF(x...)
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#endif /* DEBUG */
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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@ -55,8 +57,8 @@
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
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{0xFF800000, 0xFF900000, 0xFFC00000}, /* 0:000: configuraton 4 */
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{0xFF900000, 0xFF800000, 0xFFC00000}, /* 1:001: configuraton 3 */
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{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
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{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
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{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
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{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
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{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
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@ -131,6 +133,12 @@ unsigned long flash_init(void)
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total_b += flash_info[i].size;
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}
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[2]);
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return total_b;
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}
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@ -153,6 +161,9 @@ void flash_print_info(flash_info_t * info)
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case FLASH_MAN_AMD:
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printf("AMD ");
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break;
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case FLASH_MAN_STM:
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printf("STM ");
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break;
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case FLASH_MAN_FUJ:
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printf("FUJITSU ");
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break;
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@ -300,6 +311,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
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info->sector_count = 8;
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info->size = 0x0080000; /* => 512 ko */
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break;
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case (FLASH_WORD_SIZE) STM_ID_M29W040B:
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info->flash_id += FLASH_AM040;
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info->sector_count = 8;
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info->size = 0x0080000; /* => 512 ko */
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break;
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case (FLASH_WORD_SIZE) AMD_ID_LV033C:
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info->flash_id += FLASH_AMDLV033C;
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info->sector_count = 64;
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@ -312,8 +328,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
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/* set up sector start address table */
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
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(info->flash_id == FLASH_AM040) ||
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(info->flash_id == FLASH_AMD016)) {
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((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
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((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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} else {
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@ -343,6 +359,15 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* D0 = 1 if protected */
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addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
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/* For AMD29033C flash we need to resend the command of *
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* reading flash protection for upper 8 Mb of flash */
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if ( i == 32 ) {
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addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
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addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
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addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
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info->protect[i] = 0;
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else
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@ -432,7 +457,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
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printf("Erasing sector %p\n", addr2);
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
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addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
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@ -37,6 +37,15 @@ void fpga_init (void);
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int board_early_init_f (void)
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{
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unsigned long mfr;
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unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
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unsigned char switch_status;
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unsigned long cs0_base;
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unsigned long cs0_size;
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unsigned long cs0_twt;
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unsigned long cs2_base;
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unsigned long cs2_size;
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unsigned long cs2_twt;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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@ -47,17 +56,49 @@ int board_early_init_f (void)
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*-------------------------------------------------------------------------+
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| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
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| FPGA. Initialize bank 7 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
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mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
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EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
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EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/* read FPGA base register FPGA_REG0 */
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switch_status = *fpga_base;
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if (switch_status & 0x40) {
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cs0_base = 0xFFE00000;
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cs0_size = EBC_BXCR_BS_2MB;
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cs0_twt = 8;
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cs2_base = 0xFF800000;
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cs2_size = EBC_BXCR_BS_4MB;
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cs2_twt = 10;
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} else {
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cs0_base = 0xFFC00000;
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cs0_size = EBC_BXCR_BS_4MB;
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cs0_twt = 10;
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cs2_base = 0xFF800000;
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cs2_size = EBC_BXCR_BS_2MB;
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cs2_twt = 8;
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}
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/*-------------------------------------------------------------------------+
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| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
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cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| 8KB NVRAM/RTC. Initialize bank 1 with default values.
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/*-------------------------------------------------------------------------+
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| 4 MB FLASH. Initialize bank 2 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
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mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
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EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
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cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| FPGA. Initialize bank 7 with default values.
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@ -0,0 +1,99 @@
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------------------------------------------
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Installation of U-Boot using PIBS firmware
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------------------------------------------
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This document describes how to install U-Boot on the Ocotea PPC440GX
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Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the
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soldered FLASH. After this you should be able to switch between PIBS and
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U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before
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continuing.
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Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu
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program. See the hints for configuring cu above. Make sure you can
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communicate with the PIBS firmware: reset the board and hit ENTER a couple of
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times until you see the PIBS prompt (PIBS $). Then proceed as follows:
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Read MAC Addresses from PIBS
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----------------------------
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To read the configured MAC addresses available on your Ocotea board please use
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the following commands:
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PIBS $ echo $hwdaddr0
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000173017FE3
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PIBS $ echo $hwdaddr1
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000173017FE4
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PIBS $ echo $hwdaddr2
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000173017FE1
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PIBS $ echo $hwdaddr3
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000173017FE2
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In U-Boot this is stored in the following environment variables:
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* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3)
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* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4)
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* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1)
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* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2)
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Configure the network interface (ent0 == emac0)
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-----------------------------------------------
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To download the U-Boot image we need to configure the ethernet interface with
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the following commands:
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PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up
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PIBS $ set ipdstaddr0=192.168.1.1
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status: writing PIBS variable value to FLASH
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PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin
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status: writing PIBS variable value to FLASH
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Please insert correct parameters for your configuration (ip-addresses and
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file-location).
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Program U-Boot into soldered User-FLASH
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---------------------------------------
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Please make sure to use a newer version of U-Boot (at least 1.1.3), since
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older versions don't support running from user-FLASH.
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To program U-Boot into the soldered user-FLASH use the following command:
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PIBS $ storefile bin eth 0xffbc0000
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This commands loads the file vis ethernet into ram and copies it into the
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user-FLASH.
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Switch to U-Boot
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----------------
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Now you can turn your board off and switch SW1 (U46) to on (= closed). After
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powering the board you should see the following message:
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U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
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IBM PowerPC 440 GX Rev. C
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Board: IBM 440GX Evaluation Board
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VCO: 1066 MHz
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CPU: 533 MHz
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PLB: 152 MHz
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OPB: 76 MHz
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EPB: 76 MHz
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I2C: ready
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DRAM: 256 MB
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FLASH: 5 MB
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PCI: Bus Dev VenId DevId Class Int
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In: serial
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Out: serial
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Err: serial
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KGDB: kgdb ready
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ready
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Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3
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BEDBUG:ready
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=>
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April 06 2005, Stefan Roese <sr@denx.de>
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@ -49,7 +49,7 @@
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
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#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
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#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
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