mpc83xx: MPC837XERDB: Add PCIe support
On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe slots. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -13,6 +13,7 @@
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#include <common.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <pci.h>
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#include <asm/io.h>
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#if defined(CONFIG_PCI)
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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static struct pci_region pci_regions[] = {
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@ -36,12 +37,46 @@ static struct pci_region pci_regions[] = {
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}
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}
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};
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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void pci_init_board(void)
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{
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* Enable all 5 PCI_CLK_OUTPUTS */
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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clk->occr |= 0xf8000000;
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@ -55,5 +90,27 @@ void pci_init_board(void)
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg, 0);
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mpc83xx_pci_init(1, reg, 0);
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/* There is no PEX in MPC8379 parts. */
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if (PARTID_NO_E(spridr) == SPR_8379)
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return;
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/* Configure the clock for PCIE controller */
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
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SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(2, pcie_reg, 0);
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}
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}
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#endif /* CONFIG_PCI */
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#endif /* CONFIG_PCI */
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@ -49,6 +49,7 @@
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#else
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#else
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#define CONFIG_83XX_GENERIC_PCI 1
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#define CONFIG_83XX_GENERIC_PCI 1
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#define CONFIG_83XX_GENERIC_PCIE 1
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#endif
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#ifndef CONFIG_SYS_CLK_FREQ
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@ -375,6 +376,26 @@
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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