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Merge with /home/stefan/git/u-boot/acadia-nand

This commit is contained in:
Stefan Roese 2007-05-24 09:50:17 +02:00
parent d756894722 5d4a179013
commit 7d075ee1d8
4 changed files with 25 additions and 27 deletions
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9
board/amcc/acadia/acadia.c
View File

@ -62,6 +62,10 @@ int board_early_init_f(void)
acadia_gpio_init();
/* Configure 405EZ for NAND usage */
mtsdr(sdrnand0, 0x80c00000);
mtsdr(sdrultra0, 0x8d110000);
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
@ -91,8 +95,11 @@ int misc_init_f(void)
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
rev = in8(CFG_CPLD_BASE + 0);
printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);

8
cpu/ppc4xx/ndfc.c
View File

@ -33,12 +33,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EZ))
#include <nand.h>
#include <linux/mtd/ndfc.h>
#include <asm/processor.h>
#include <ppc440.h>
#include <ppc4xx.h>
static u8 hwctl = 0;
@ -176,8 +177,7 @@ int board_nand_init(struct nand_chip *nand)
/*
* Setup EBC (CS0 only right now)
*/
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
mtebc(EBC0_CFG, 0xb8400000);
mtebc(pb0cr, CFG_EBC_PB0CR);
mtebc(pb0ap, CFG_EBC_PB0AP);

27
include/configs/acadia.h
View File

@ -34,7 +34,9 @@
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
/* Detect Acadia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
66666666 : 33333000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
@ -224,16 +226,6 @@
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#if 0 /* test-only */
#define TEST_ONLY_NAND
#endif
#ifdef TEST_ONLY_NAND
#define CMD_NAND CFG_CMD_NAND
#else
#define CMD_NAND 0
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@ -252,7 +244,7 @@
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CMD_NAND | \
CFG_CMD_NAND | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
@ -300,7 +292,6 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
@ -308,7 +299,6 @@
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
@ -322,7 +312,7 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
@ -358,7 +348,8 @@
/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
* GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
* GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
* GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
* GPIO0[4] - External Bus Controller Hold Input
* GPIO0[5] - External Bus Controller Priority Input
* GPIO0[6] - External Bus Controller HLDA Output
@ -376,10 +367,10 @@
*/
#define CFG_GPIO0_TCR 0xC0000000
#define CFG_GPIO0_OSRL 0x50000000
#define CFG_GPIO0_OSRH 0x00000055
#define CFG_GPIO0_OSRH 0x02000055
#define CFG_GPIO0_ISR1L 0x00000000
#define CFG_GPIO0_ISR1H 0x00000055
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TSRL 0x02000000
#define CFG_GPIO0_TSRH 0x00000055
/*-----------------------------------------------------------------------

8
include/ppc405.h
View File

@ -547,8 +547,8 @@
#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
#define sdrnand0 0x4000
#define sdrultra0 0x4040
@ -593,8 +593,8 @@
/*
* Macro for accessing the indirect CPR register
*/
#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */