ColdFire: Add modules header files
Add CF specific modules header files Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Signed-off-by: John Rigby <jrigby@freescale.com>
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TsiChungLiew
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/*
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* Cross Bar Switch Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CROSSBAR_H__
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#define __CROSSBAR_H__
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/*********************************************************************
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* Cross-bar switch (XBS)
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*********************************************************************/
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typedef struct xbs {
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u32 prs1; /* 0x100 Priority Register Slave 1 */
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u32 res1[3]; /* 0x104 - 0F */
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u32 crs1; /* 0x110 Control Register Slave 1 */
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u32 res2[187]; /* 0x114 - 0x3FF */
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u32 prs4; /* 0x400 Priority Register Slave 4 */
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u32 res3[3]; /* 0x404 - 0F */
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u32 crs4; /* 0x410 Control Register Slave 4 */
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u32 res4[123]; /* 0x414 - 0x5FF */
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u32 prs6; /* 0x600 Priority Register Slave 6 */
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u32 res5[3]; /* 0x604 - 0F */
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u32 crs6; /* 0x610 Control Register Slave 6 */
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u32 res6[59]; /* 0x614 - 0x6FF */
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u32 prs7; /* 0x700 Priority Register Slave 7 */
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u32 res7[3]; /* 0x704 - 0F */
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u32 crs7; /* 0x710 Control Register Slave 7 */
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} xbs_t;
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/* Bit definitions and macros for PRS group */
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#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
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#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
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#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
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#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
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#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
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#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
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#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
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/* Bit definitions and macros for CRS group */
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#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
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#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
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#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
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#define XBS_CRS_RO (0x80000000) /* Read Only */
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#define XBS_CRS_PCTL_PARK_FIELD (0)
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#define XBS_CRS_PCTL_PARK_ON_LAST (1)
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#define XBS_CRS_PCTL_PARK_NONE (2)
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#define XBS_CRS_PCTL_PARK_CORE (0)
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#define XBS_CRS_PCTL_PARK_EDMA (1)
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#define XBS_CRS_PCTL_PARK_FEC0 (2)
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#define XBS_CRS_PCTL_PARK_FEC1 (3)
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#define XBS_CRS_PCTL_PARK_PCI (5)
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#define XBS_CRS_PCTL_PARK_USB (6)
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#define XBS_CRS_PCTL_PARK_SBF (7)
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#endif /* __CROSSBAR_H__ */
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/*
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* MCF5227x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __DSPI_H__
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#define __DSPI_H__
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/*********************************************************************
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* DMA Serial Peripheral Interface (DSPI)
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*********************************************************************/
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typedef struct dspi {
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u32 dmcr;
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u8 resv0[0x4];
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u32 dtcr;
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u32 dctar0;
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u32 dctar1;
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u32 dctar2;
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u32 dctar3;
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u32 dctar4;
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u32 dctar5;
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u32 dctar6;
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u32 dctar7;
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u32 dsr;
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u32 dirsr;
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u32 dtfr;
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u32 drfr;
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u32 dtfdr0;
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u32 dtfdr1;
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u32 dtfdr2;
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u32 dtfdr3;
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u8 resv1[0x30];
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u32 drfdr0;
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u32 drfdr1;
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u32 drfdr2;
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u32 drfdr3;
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} dspi_t;
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/* Bit definitions and macros for DMCR */
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#define DSPI_DMCR_HALT (0x00000001)
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#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
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#define DSPI_DMCR_CRXF (0x00000400)
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#define DSPI_DMCR_CTXF (0x00000800)
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#define DSPI_DMCR_DRXF (0x00001000)
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#define DSPI_DMCR_DTXF (0x00002000)
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#define DSPI_DMCR_CSIS0 (0x00010000)
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#define DSPI_DMCR_CSIS2 (0x00040000)
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#define DSPI_DMCR_CSIS3 (0x00080000)
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#define DSPI_DMCR_CSIS5 (0x00200000)
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#define DSPI_DMCR_ROOE (0x01000000)
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#define DSPI_DMCR_PCSSE (0x02000000)
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#define DSPI_DMCR_MTFE (0x04000000)
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#define DSPI_DMCR_FRZ (0x08000000)
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#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
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#define DSPI_DMCR_CSCK (0x40000000)
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#define DSPI_DMCR_MSTR (0x80000000)
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/* Bit definitions and macros for DTCR */
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#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for DCTAR group */
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#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
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#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
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#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
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#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
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#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
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#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
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#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
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#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
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#define DSPI_DCTAR_LSBFE (0x01000000)
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#define DSPI_DCTAR_CPHA (0x02000000)
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#define DSPI_DCTAR_CPOL (0x04000000)
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#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
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#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
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#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
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#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
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#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
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#define DSPI_DCTAR_PASC_1CLK (0x00000000)
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#define DSPI_DCTAR_PASC_3CLK (0x00100000)
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#define DSPI_DCTAR_PASC_5CLK (0x00200000)
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#define DSPI_DCTAR_PASC_7CLK (0x00300000)
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#define DSPI_DCTAR_PDT_1CLK (0x00000000)
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#define DSPI_DCTAR_PDT_3CLK (0x00040000)
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#define DSPI_DCTAR_PDT_5CLK (0x00080000)
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#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
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#define DSPI_DCTAR_PBR_1CLK (0x00000000)
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#define DSPI_DCTAR_PBR_3CLK (0x00010000)
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#define DSPI_DCTAR_PBR_5CLK (0x00020000)
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#define DSPI_DCTAR_PBR_7CLK (0x00030000)
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/* Bit definitions and macros for DSR */
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#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
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#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
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#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
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#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
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#define DSPI_DSR_RFDF (0x00020000)
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#define DSPI_DSR_RFOF (0x00080000)
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#define DSPI_DSR_TFFF (0x02000000)
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#define DSPI_DSR_TFUF (0x08000000)
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#define DSPI_DSR_EOQF (0x10000000)
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#define DSPI_DSR_TXRXS (0x40000000)
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#define DSPI_DSR_TCF (0x80000000)
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/* Bit definitions and macros for DIRSR */
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#define DSPI_DIRSR_RFDFS (0x00010000)
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#define DSPI_DIRSR_RFDFE (0x00020000)
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#define DSPI_DIRSR_RFOFE (0x00080000)
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#define DSPI_DIRSR_TFFFS (0x01000000)
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#define DSPI_DIRSR_TFFFE (0x02000000)
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#define DSPI_DIRSR_TFUFE (0x08000000)
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#define DSPI_DIRSR_EOQFE (0x10000000)
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#define DSPI_DIRSR_TCFE (0x80000000)
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/* Bit definitions and macros for DTFR */
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#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
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#define DSPI_DTFR_CS0 (0x00010000)
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#define DSPI_DTFR_CS2 (0x00040000)
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#define DSPI_DTFR_CS3 (0x00080000)
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#define DSPI_DTFR_CS5 (0x00200000)
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#define DSPI_DTFR_CTCNT (0x04000000)
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#define DSPI_DTFR_EOQ (0x08000000)
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#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
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#define DSPI_DTFR_CONT (0x80000000)
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/* Bit definitions and macros for DRFR */
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#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
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/* Bit definitions and macros for DTFDR group */
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#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
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#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for DRFDR group */
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#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
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#endif /* __DSPI_H__ */
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/*
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* EDMA Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __EDMA_H__
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#define __EDMA_H__
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/*********************************************************************
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* Enhanced DMA (EDMA)
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*********************************************************************/
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/* eDMA module registers */
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typedef struct edma_ctrl {
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u32 cr; /* 0x00 Control Register */
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u32 es; /* 0x04 Error Status Register */
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u16 res1[3]; /* 0x08 - 0x0D */
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u16 erq; /* 0x0E Enable Request Register */
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u16 res2[3]; /* 0x10 - 0x15 */
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u16 eei; /* 0x16 Enable Error Interrupt Request */
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u8 serq; /* 0x18 Set Enable Request */
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u8 cerq; /* 0x19 Clear Enable Request */
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u8 seei; /* 0x1A Set En Error Interrupt Request */
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u8 ceei; /* 0x1B Clear En Error Interrupt Request */
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u8 cint; /* 0x1C Clear Interrupt Enable */
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u8 cerr; /* 0x1D Clear Error */
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u8 ssrt; /* 0x1E Set START Bit */
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u8 cdne; /* 0x1F Clear DONE Status Bit */
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u16 res3[3]; /* 0x20 - 0x25 */
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u16 intr; /* 0x26 Interrupt Request */
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u16 res4[3]; /* 0x28 - 0x2D */
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u16 err; /* 0x2E Error Register */
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u32 res5[52]; /* 0x30 - 0xFF */
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u8 dchpri0; /* 0x100 Channel 0 Priority */
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u8 dchpri1; /* 0x101 Channel 1 Priority */
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u8 dchpri2; /* 0x102 Channel 2 Priority */
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u8 dchpri3; /* 0x103 Channel 3 Priority */
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u8 dchpri4; /* 0x104 Channel 4 Priority */
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u8 dchpri5; /* 0x105 Channel 5 Priority */
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u8 dchpri6; /* 0x106 Channel 6 Priority */
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u8 dchpri7; /* 0x107 Channel 7 Priority */
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u8 dchpri8; /* 0x108 Channel 8 Priority */
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u8 dchpri9; /* 0x109 Channel 9 Priority */
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u8 dchpri10; /* 0x110 Channel 10 Priority */
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u8 dchpri11; /* 0x111 Channel 11 Priority */
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u8 dchpri12; /* 0x112 Channel 12 Priority */
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u8 dchpri13; /* 0x113 Channel 13 Priority */
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u8 dchpri14; /* 0x114 Channel 14 Priority */
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u8 dchpri15; /* 0x115 Channel 15 Priority */
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} edma_t;
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/* TCD - eDMA*/
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typedef struct tcd_ctrl {
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u32 saddr; /* 0x00 Source Address */
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u16 attr; /* 0x04 Transfer Attributes */
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u16 soff; /* 0x06 Signed Source Address Offset */
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u32 nbytes; /* 0x08 Minor Byte Count */
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u32 slast; /* 0x0C Last Source Address Adjustment */
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u32 daddr; /* 0x10 Destination address */
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u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
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u16 doff; /* 0x16 Signed Destination Address Offset */
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u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
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u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */
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u16 csr; /* 0x1E Control and Status */
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} tcd_st;
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typedef struct tcd_multiple {
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tcd_st tcd[16];
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} tcd_t;
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/* Bit definitions and macros for EPPAR */
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#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
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#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
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#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
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#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
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#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
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#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
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#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
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#define EPORT_EPPAR_LEVEL (0)
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#define EPORT_EPPAR_RISING (1)
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#define EPORT_EPPAR_FALLING (2)
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#define EPORT_EPPAR_BOTH (3)
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#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA7_RISING (0x4000)
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#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
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#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
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#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA6_RISING (0x1000)
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#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
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#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
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#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA5_RISING (0x0400)
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#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
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#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
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#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA4_RISING (0x0100)
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#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
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#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
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#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA3_RISING (0x0040)
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#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
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#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
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#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA2_RISING (0x0010)
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#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
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#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
|
||||
#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
|
||||
#define EPORT_EPPAR_EPPA1_RISING (0x0004)
|
||||
#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
|
||||
#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
|
||||
|
||||
/* Bit definitions and macros for EPDDR */
|
||||
#define EPORT_EPDDR_EPDD1 (0x02)
|
||||
#define EPORT_EPDDR_EPDD2 (0x04)
|
||||
#define EPORT_EPDDR_EPDD3 (0x08)
|
||||
#define EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for EPIER */
|
||||
#define EPORT_EPIER_EPIE1 (0x02)
|
||||
#define EPORT_EPIER_EPIE2 (0x04)
|
||||
#define EPORT_EPIER_EPIE3 (0x08)
|
||||
#define EPORT_EPIER_EPIE4 (0x10)
|
||||
#define EPORT_EPIER_EPIE5 (0x20)
|
||||
#define EPORT_EPIER_EPIE6 (0x40)
|
||||
#define EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for EPDR */
|
||||
#define EPORT_EPDR_EPD1 (0x02)
|
||||
#define EPORT_EPDR_EPD2 (0x04)
|
||||
#define EPORT_EPDR_EPD3 (0x08)
|
||||
#define EPORT_EPDR_EPD4 (0x10)
|
||||
#define EPORT_EPDR_EPD5 (0x20)
|
||||
#define EPORT_EPDR_EPD6 (0x40)
|
||||
#define EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for EPPDR */
|
||||
#define EPORT_EPPDR_EPPD1 (0x02)
|
||||
#define EPORT_EPPDR_EPPD2 (0x04)
|
||||
#define EPORT_EPPDR_EPPD3 (0x08)
|
||||
#define EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for EPFR */
|
||||
#define EPORT_EPFR_EPF1 (0x02)
|
||||
#define EPORT_EPFR_EPF2 (0x04)
|
||||
#define EPORT_EPFR_EPF3 (0x08)
|
||||
#define EPORT_EPFR_EPF4 (0x10)
|
||||
#define EPORT_EPFR_EPF5 (0x20)
|
||||
#define EPORT_EPFR_EPF6 (0x40)
|
||||
#define EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
#endif /* __EDMA_H__ */
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* FlexBus Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __FLEXBUS_H
|
||||
#define __FLEXBUS_H
|
||||
|
||||
/*********************************************************************
|
||||
* FlexBus Chip Selects (FBCS)
|
||||
*********************************************************************/
|
||||
|
||||
typedef struct fbcs {
|
||||
u32 csar0; /* Chip-select Address Register */
|
||||
u32 csmr0; /* Chip-select Mask Register */
|
||||
u32 cscr0; /* Chip-select Control Register */
|
||||
u32 csar1; /* Chip-select Address Register */
|
||||
u32 csmr1; /* Chip-select Mask Register */
|
||||
u32 cscr1; /* Chip-select Control Register */
|
||||
u32 csar2; /* Chip-select Address Register */
|
||||
u32 csmr2; /* Chip-select Mask Register */
|
||||
u32 cscr2; /* Chip-select Control Register */
|
||||
u32 csar3; /* Chip-select Address Register */
|
||||
u32 csmr3; /* Chip-select Mask Register */
|
||||
u32 cscr3; /* Chip-select Control Register */
|
||||
u32 csar4; /* Chip-select Address Register */
|
||||
u32 csmr4; /* Chip-select Mask Register */
|
||||
u32 cscr4; /* Chip-select Control Register */
|
||||
u32 csar5; /* Chip-select Address Register */
|
||||
u32 csmr5; /* Chip-select Mask Register */
|
||||
u32 cscr5; /* Chip-select Control Register */
|
||||
} fbcs_t;
|
||||
|
||||
/* Bit definitions and macros for CSAR group */
|
||||
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for CSMR group */
|
||||
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
|
||||
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
|
||||
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
|
||||
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define FBCS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define FBCS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define FBCS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define FBCS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define FBCS_CSMR_BAM_8M (0x007F0000)
|
||||
#define FBCS_CSMR_BAM_4M (0x003F0000)
|
||||
#define FBCS_CSMR_BAM_2M (0x001F0000)
|
||||
#define FBCS_CSMR_BAM_1M (0x000F0000)
|
||||
#define FBCS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define FBCS_CSMR_BAM_512K (0x00070000)
|
||||
#define FBCS_CSMR_BAM_256K (0x00030000)
|
||||
#define FBCS_CSMR_BAM_128K (0x00010000)
|
||||
#define FBCS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for CSCR group */
|
||||
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
|
||||
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
|
||||
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
|
||||
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
|
||||
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
|
||||
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
|
||||
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
|
||||
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
|
||||
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
|
||||
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
|
||||
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
|
||||
|
||||
#define FBCS_CSCR_PS_8 (0x00000040)
|
||||
#define FBCS_CSCR_PS_16 (0x00000080)
|
||||
#define FBCS_CSCR_PS_32 (0x00000000)
|
||||
|
||||
#endif /* __FLEXBUS_H */
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* LCD controller Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __LCDC_H__
|
||||
#define __LCDC_H__
|
||||
|
||||
/* LCD module registers */
|
||||
typedef struct lcd_ctrl {
|
||||
u32 ssar; /* 0x00 Screen Start Address Register */
|
||||
u32 sr; /* 0x04 LCD Size Register */
|
||||
u32 vpw; /* 0x08 Virtual Page Width Register */
|
||||
u32 cpr; /* 0x0C Cursor Position Register */
|
||||
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
|
||||
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
|
||||
u32 pcr; /* 0x18 Panel Configuration Register */
|
||||
u32 hcr; /* 0x1C Horizontal Configuration Register */
|
||||
u32 vcr; /* 0x20 Vertical Configuration Register */
|
||||
u32 por; /* 0x24 Panning Offset Register */
|
||||
u32 scr; /* 0x28 Sharp Configuration Register */
|
||||
u32 pccr; /* 0x2C PWM Contrast Control Register */
|
||||
u32 dcr; /* 0x30 DMA Control Register */
|
||||
u32 rmcr; /* 0x34 Refresh Mode Control Register */
|
||||
u32 icr; /* 0x38 Refresh Mode Control Register */
|
||||
u32 ier; /* 0x3C Interrupt Enable Register */
|
||||
u32 isr; /* 0x40 Interrupt Status Register */
|
||||
u32 res[4];
|
||||
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
|
||||
u32 gwsr; /* 0x54 Graphic Window Size Register */
|
||||
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
|
||||
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
|
||||
u32 gwpr; /* 0x60 Graphic Window Position Register */
|
||||
u32 gwcr; /* 0x64 Graphic Window Control Register */
|
||||
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
|
||||
} lcd_t;
|
||||
|
||||
typedef struct lcdbg_ctrl {
|
||||
u32 bglut[255];
|
||||
} lcdbg_t;
|
||||
|
||||
typedef struct lcdgw_ctrl {
|
||||
u32 gwlut[255];
|
||||
} lcdgw_t;
|
||||
|
||||
/* Bit definitions and macros for LCDC_LSSAR */
|
||||
#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LSR */
|
||||
#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20)
|
||||
#define LCDC_SR_YMAX(x) ((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LVPWR */
|
||||
#define LCDC_VPWR_VPW(x) (((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LCPR */
|
||||
#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30)
|
||||
#define LCDC_CPR_CC_AND (0xC0000000)
|
||||
#define LCDC_CPR_CC_XOR (0x80000000)
|
||||
#define LCDC_CPR_CC_OR (0x40000000)
|
||||
#define LCDC_CPR_CC_TRANSPARENT (0x00000000)
|
||||
#define LCDC_CPR_OP (0x10000000)
|
||||
#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16)
|
||||
#define LCDC_CPR_CYP(x) ((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LCWHBR */
|
||||
#define LCDC_CWHBR_BK_EN (0x80000000)
|
||||
#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24)
|
||||
#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16)
|
||||
#define LCDC_CWHBR_BD(x) ((x)&0x000000FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LCCMR */
|
||||
#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
|
||||
#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
|
||||
#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LPCR */
|
||||
#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
|
||||
#define LCDC_PCR_MODE_TFT (0xC0000000)
|
||||
#define LCDC_PCR_MODE_CSTN (0x40000000)
|
||||
#define LCDC_PCR_MODE_MONOCHROME (0x00000000)
|
||||
#define LCDC_PCR_TFT (0x80000000)
|
||||
#define LCDC_PCR_COLOR (0x40000000)
|
||||
#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28)
|
||||
#define LCDC_PCR_PBSIZ_8 (0x30000000)
|
||||
#define LCDC_PCR_PBSIZ_4 (0x20000000)
|
||||
#define LCDC_PCR_PBSIZ_2 (0x10000000)
|
||||
#define LCDC_PCR_PBSIZ_1 (0x00000000)
|
||||
#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25)
|
||||
#define LCDC_PCR_BPIX_18bpp (0x0C000000)
|
||||
#define LCDC_PCR_BPIX_16bpp (0x0A000000)
|
||||
#define LCDC_PCR_BPIX_12bpp (0x08000000)
|
||||
#define LCDC_PCR_BPIX_8bpp (0x06000000)
|
||||
#define LCDC_PCR_BPIX_4bpp (0x04000000)
|
||||
#define LCDC_PCR_BPIX_2bpp (0x02000000)
|
||||
#define LCDC_PCR_BPIX_1bpp (0x00000000)
|
||||
#define LCDC_PCR_PIXPOL (0x01000000)
|
||||
#define LCDC_PCR_FLM (0x00800000)
|
||||
#define LCDC_PCR_LPPOL (0x00400000)
|
||||
#define LCDC_PCR_CLKPOL (0x00200000)
|
||||
#define LCDC_PCR_OEPOL (0x00100000)
|
||||
#define LCDC_PCR_SCLKIDLE (0x00080000)
|
||||
#define LCDC_PCR_ENDSEL (0x00040000)
|
||||
#define LCDC_PCR_SWAP_SEL (0x00020000)
|
||||
#define LCDC_PCR_REV_VS (0x00010000)
|
||||
#define LCDC_PCR_ACDSEL (0x00008000)
|
||||
#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8)
|
||||
#define LCDC_PCR_SCLKSEL (0x00000080)
|
||||
#define LCDC_PCR_SHARP (0x00000040)
|
||||
#define LCDC_PCR_PCD(x) ((x)&0x0000003F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LHCR */
|
||||
#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
|
||||
#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
|
||||
#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LVCR */
|
||||
#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
|
||||
#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
|
||||
#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_SCR */
|
||||
#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26)
|
||||
#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16)
|
||||
#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8)
|
||||
#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4)
|
||||
#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LPCCR */
|
||||
#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16)
|
||||
#define LCDC_PCCR_LDMSK (0x00008000)
|
||||
#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9)
|
||||
#define LCDC_PCCR_SCR_LCDCLK (0x00000400)
|
||||
#define LCDC_PCCR_SCR_PIXCLK (0x00000200)
|
||||
#define LCDC_PCCR_SCR_LNPULSE (0x00000000)
|
||||
#define LCDC_PCCR_CC_EN (0x00000100)
|
||||
#define LCDC_PCCR_PW(x) ((x)&0x000000FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LDCR */
|
||||
#define LCDC_DCR_BURST (0x80000000)
|
||||
#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16)
|
||||
#define LCDC_DCR_TM(x) ((x)&0x0000001F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LRMCR */
|
||||
#define LCDC_RMCR_SEL_REF (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LICR */
|
||||
#define LCDC_ICR_GW_INT_CON (0x00000010)
|
||||
#define LCDC_ICR_INTSYN (0x00000004)
|
||||
#define LCDC_ICR_INTCON (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LIER */
|
||||
#define LCDC_IER_GW_UDR (0x00000080)
|
||||
#define LCDC_IER_GW_ERR (0x00000040)
|
||||
#define LCDC_IER_GW_EOF (0x00000020)
|
||||
#define LCDC_IER_GW_BOF (0x00000010)
|
||||
#define LCDC_IER_UDR (0x00000008)
|
||||
#define LCDC_IER_ERR (0x00000004)
|
||||
#define LCDC_IER_EOF (0x00000002)
|
||||
#define LCDC_IER_BOF (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWSAR */
|
||||
#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWSR */
|
||||
#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20)
|
||||
#define LCDC_GWSR_GWH(x) ((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWVPWR */
|
||||
#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWPOR */
|
||||
#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWPR */
|
||||
#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16)
|
||||
#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWCR */
|
||||
#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24)
|
||||
#define LCDC_GWCR_GWCKE (0x00800000)
|
||||
#define LCDC_LGWCR_GWE (0x00400000)
|
||||
#define LCDC_LGWCR_GW_RVS (0x00200000)
|
||||
#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
|
||||
#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
|
||||
#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F)
|
||||
|
||||
/* Bit definitions and macros for LCDC_LGWDCR */
|
||||
#define LCDC_LGWDCR_GWBT (0x80000000)
|
||||
#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
|
||||
#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F)
|
||||
|
||||
#endif /* __LCDC_H__ */
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* SSI Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __SSI_H__
|
||||
#define __SSI_H__
|
||||
|
||||
/*********************************************************************
|
||||
* Synchronous Serial Interface (SSI)
|
||||
*********************************************************************/
|
||||
|
||||
typedef struct ssi {
|
||||
u32 tx0;
|
||||
u32 tx1;
|
||||
u32 rx0;
|
||||
u32 rx1;
|
||||
u32 cr;
|
||||
u32 isr;
|
||||
u32 ier;
|
||||
u32 tcr;
|
||||
u32 rcr;
|
||||
u32 ccr;
|
||||
u8 resv0[0x4];
|
||||
u32 fcsr;
|
||||
u8 resv1[0x8];
|
||||
u32 acr;
|
||||
u32 acadd;
|
||||
u32 acdat;
|
||||
u32 atag;
|
||||
u32 tmask;
|
||||
u32 rmask;
|
||||
} ssi_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Synchronous Serial Interface (SSI)
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for SSI_CR */
|
||||
#define SSI_CR_CIS (0x00000200)
|
||||
#define SSI_CR_TCH (0x00000100)
|
||||
#define SSI_CR_MCE (0x00000080)
|
||||
#define SSI_CR_I2S_SLAVE (0x00000040)
|
||||
#define SSI_CR_I2S_MASTER (0x00000020)
|
||||
#define SSI_CR_I2S_NORMAL (0x00000000)
|
||||
#define SSI_CR_SYN (0x00000010)
|
||||
#define SSI_CR_NET (0x00000008)
|
||||
#define SSI_CR_RE (0x00000004)
|
||||
#define SSI_CR_TE (0x00000002)
|
||||
#define SSI_CR_SSI_EN (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_ISR */
|
||||
#define SSI_ISR_CMDAU (0x00040000)
|
||||
#define SSI_ISR_CMDDU (0x00020000)
|
||||
#define SSI_ISR_RXT (0x00010000)
|
||||
#define SSI_ISR_RDR1 (0x00008000)
|
||||
#define SSI_ISR_RDR0 (0x00004000)
|
||||
#define SSI_ISR_TDE1 (0x00002000)
|
||||
#define SSI_ISR_TDE0 (0x00001000)
|
||||
#define SSI_ISR_ROE1 (0x00000800)
|
||||
#define SSI_ISR_ROE0 (0x00000400)
|
||||
#define SSI_ISR_TUE1 (0x00000200)
|
||||
#define SSI_ISR_TUE0 (0x00000100)
|
||||
#define SSI_ISR_TFS (0x00000080)
|
||||
#define SSI_ISR_RFS (0x00000040)
|
||||
#define SSI_ISR_TLS (0x00000020)
|
||||
#define SSI_ISR_RLS (0x00000010)
|
||||
#define SSI_ISR_RFF1 (0x00000008)
|
||||
#define SSI_ISR_RFF0 (0x00000004)
|
||||
#define SSI_ISR_TFE1 (0x00000002)
|
||||
#define SSI_ISR_TFE0 (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_IER */
|
||||
#define SSI_IER_RDMAE (0x00400000)
|
||||
#define SSI_IER_RIE (0x00200000)
|
||||
#define SSI_IER_TDMAE (0x00100000)
|
||||
#define SSI_IER_TIE (0x00080000)
|
||||
#define SSI_IER_CMDAU (0x00040000)
|
||||
#define SSI_IER_CMDU (0x00020000)
|
||||
#define SSI_IER_RXT (0x00010000)
|
||||
#define SSI_IER_RDR1 (0x00008000)
|
||||
#define SSI_IER_RDR0 (0x00004000)
|
||||
#define SSI_IER_TDE1 (0x00002000)
|
||||
#define SSI_IER_TDE0 (0x00001000)
|
||||
#define SSI_IER_ROE1 (0x00000800)
|
||||
#define SSI_IER_ROE0 (0x00000400)
|
||||
#define SSI_IER_TUE1 (0x00000200)
|
||||
#define SSI_IER_TUE0 (0x00000100)
|
||||
#define SSI_IER_TFS (0x00000080)
|
||||
#define SSI_IER_RFS (0x00000040)
|
||||
#define SSI_IER_TLS (0x00000020)
|
||||
#define SSI_IER_RLS (0x00000010)
|
||||
#define SSI_IER_RFF1 (0x00000008)
|
||||
#define SSI_IER_RFF0 (0x00000004)
|
||||
#define SSI_IER_TFE1 (0x00000002)
|
||||
#define SSI_IER_TFE0 (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_TCR */
|
||||
#define SSI_TCR_TXBIT0 (0x00000200)
|
||||
#define SSI_TCR_TFEN1 (0x00000100)
|
||||
#define SSI_TCR_TFEN0 (0x00000080)
|
||||
#define SSI_TCR_TFDIR (0x00000040)
|
||||
#define SSI_TCR_TXDIR (0x00000020)
|
||||
#define SSI_TCR_TSHFD (0x00000010)
|
||||
#define SSI_TCR_TSCKP (0x00000008)
|
||||
#define SSI_TCR_TFSI (0x00000004)
|
||||
#define SSI_TCR_TFSL (0x00000002)
|
||||
#define SSI_TCR_TEFS (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_RCR */
|
||||
#define SSI_RCR_RXEXT (0x00000400)
|
||||
#define SSI_RCR_RXBIT0 (0x00000200)
|
||||
#define SSI_RCR_RFEN1 (0x00000100)
|
||||
#define SSI_RCR_RFEN0 (0x00000080)
|
||||
#define SSI_RCR_RSHFD (0x00000010)
|
||||
#define SSI_RCR_RSCKP (0x00000008)
|
||||
#define SSI_RCR_RFSI (0x00000004)
|
||||
#define SSI_RCR_RFSL (0x00000002)
|
||||
#define SSI_RCR_REFS (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_CCR */
|
||||
#define SSI_CCR_DIV2 (0x00040000)
|
||||
#define SSI_CCR_PSR (0x00020000)
|
||||
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
|
||||
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
|
||||
#define SSI_CCR_PM(x) ((x)&0x000000FF)
|
||||
|
||||
/* Bit definitions and macros for SSI_FCSR */
|
||||
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
|
||||
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
|
||||
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
|
||||
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
|
||||
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
|
||||
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
|
||||
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
|
||||
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
|
||||
|
||||
/* Bit definitions and macros for SSI_ACR */
|
||||
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
|
||||
#define SSI_ACR_WR (0x00000010)
|
||||
#define SSI_ACR_RD (0x00000008)
|
||||
#define SSI_ACR_TIF (0x00000004)
|
||||
#define SSI_ACR_FV (0x00000002)
|
||||
#define SSI_ACR_AC97EN (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for SSI_ACADD */
|
||||
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
|
||||
|
||||
/* Bit definitions and macros for SSI_ACDAT */
|
||||
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
|
||||
|
||||
/* Bit definitions and macros for SSI_ATAG */
|
||||
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
|
||||
|
||||
#endif /* __SSI_H__ */
|
||||
Loading…
Reference in New Issue