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Patch by Pantelis Antoniou, 5 May 2004: 

- Intracom board update.
- Add Codec POST.
This commit is contained in:
wdenk 2004-06-07 23:46:25 +00:00
parent cea655a224
commit 79fa88f3ed
24 changed files with 4241 additions and 171 deletions
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4
CHANGELOG
View File

@ -2,6 +2,10 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Pantelis Antoniou, 5 May 2004:
- Intracom board update.
- Add Codec POST.
* Add support for the second Ethernet interface for the 'PPChameleon'
board.

33
MAKEALL
View File

@ -33,22 +33,23 @@ LIST_5xxx=" \
#########################################################################
LIST_8xx=" \
AdderII ADS860 AMX860 c2mon \
CCM cogent_mpc8xx MPC885ADS ESTEEM192E \
ETX094 ELPT860 FADS823 FADS850SAR \
FADS860T FLAGADM FPS850L GEN860T \
GEN860T_SC GENIETV GTH hermes \
IAD210 ICU862_100MHz IP860 IVML24 \
IVML24_128 IVML24_256 IVMS8 IVMS8_128 \
IVMS8_256 KUP4K KUP4X LANTEC \
lwmon MBX MBX860T MHPC \
MPC86xADS MVS1 NETVIA NETVIA_V2 \
NX823 pcu_e QS823 QS850 \
QS860T R360MPI RBC823 rmu \
RPXClassic RPXlite RRvision SM850 \
SPD823TS svm_sc8xx SXNI855T TOP860 \
TQM823L TQM823L_LCD TQM850L TQM855L \
TQM860L v37 NETTA NETPHONE \
ADS860 ICU862_100MHz NETPHONE SPD823TS \
AMX860 IP860 NETTA SXNI855T \
AdderII IVML24 NETTA2 TOP860 \
CCM IVML24_128 NETTA_ISDN TQM823L \
ELPT860 IVML24_256 NETVIA TQM823L_LCD \
ESTEEM192E IVMS8 NETVIA_V2 TQM850L \
ETX094 IVMS8_128 NX823 TQM855L \
FADS823 IVMS8_256 QS823 TQM860L \
FADS850SAR KUP4K QS850 c2mon \
FADS860T KUP4X QS860T cogent_mpc8xx \
FLAGADM LANTEC R360MPI hermes \
FPS850L MBX RBC823 lwmon \
GEN860T MBX860T RPXClassic pcu_e \
GEN860T_SC MHPC RPXlite rmu \
GENIETV MPC86xADS RRvision svm_sc8xx \
GTH MPC885ADS SM850 v37 \
IAD210 MVS1
"
#########################################################################

41
Makefile
View File

@ -417,19 +417,50 @@ NETPHONE_config: unconfig
}
@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1))
xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))
NETTA_ISDN_6412_SWAPHOOK_config \
NETTA_ISDN_SWAPHOOK_config \
NETTA_6412_SWAPHOOK_config \
NETTA_SWAPHOOK_config \
NETTA_ISDN_6412_config \
NETTA_ISDN_config \
NETTA_6412_config \
NETTA_config: unconfig
@ >include/config.h
@[ -z "$(findstring NETTA_config,$@)" ] || \
{ echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
}
@[ -z "$(findstring NETTA_ISDN_config,$@)" ] || \
@[ -z "$(findstring ISDN_,$@)" ] || \
{ echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
}
@[ -n "$(findstring ISDN_,$@)" ] || \
{ echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
}
@[ -z "$(findstring 6412_,$@)" ] || \
{ echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
}
@[ -n "$(findstring 6412_,$@)" ] || \
{ echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
}
@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
{ echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
}
@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
{ echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
}
@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta
xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
NETTA2_V2_config \
NETTA2_config: unconfig
@ >include/config.h
@[ -z "$(findstring NETTA2_config,$@)" ] || \
{ echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
}
@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
{ echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
}
@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
NX823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx nx823

23
board/netphone/flash.c
View File

@ -87,21 +87,22 @@ unsigned long flash_init(void)
#if CONFIG_NETPHONE_VERSION == 2
size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
if (size1 > 0) {
if (flash_info[1].flash_id == FLASH_UNKNOWN)
printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
if (flash_info[1].flash_id == FLASH_UNKNOWN && size1 > 0) {
printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
}
/* Remap FLASH according to real size */
memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
/* Remap FLASH according to real size */
memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
/* Re-do sizing to get full correct info */
size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
size += size1;
size += size1;
} else
memctl->memc_br4 &= ~BR_V;
#endif
return (size);

104
board/netphone/phone_console.c
View File

@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -52,7 +52,7 @@
/*************************************************************************************************/
#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat
#define DISPLAY_BACKLIT_MASK 0x0010
#define DISPLAY_BACKLIT_MASK 0x0010
/*************************************************************************************************/
@ -63,23 +63,23 @@
#define KP_IDLE_DELAY_HZ (CFG_HZ/2) /* key was released and idle */
#if CONFIG_NETPHONE_VERSION == 1
#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_RXD_MASK 0x0008
#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_RXD_MASK 0x0008
#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_TXD_MASK 0x0004
#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_TXD_MASK 0x0004
#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_CLK_MASK 0x0001
#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
#define KP_SPI_CLK_MASK 0x0001
#elif CONFIG_NETPHONE_VERSION == 2
#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_RXD_MASK 0x00000008
#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_RXD_MASK 0x00000008
#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_TXD_MASK 0x00000004
#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_TXD_MASK 0x00000004
#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_CLK_MASK 0x00000002
#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define KP_SPI_CLK_MASK 0x00000002
#endif
#define KP_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat)
@ -115,8 +115,8 @@
KP_CS_PORT &= ~KP_CS_MASK; \
} while(0)
#define KP_ROWS 7
#define KP_COLS 4
#define KP_ROWS 7
#define KP_COLS 4
#define KP_ROWS_MASK ((1 << KP_ROWS) - 1)
#define KP_COLS_MASK ((1 << KP_COLS) - 1)
@ -124,29 +124,29 @@
#define SCAN 0
#define SCAN_FILTER 1
#define SCAN_COL 2
#define SCAN_COL_FILTER 3
#define SCAN_COL_FILTER 3
#define PRESSED 4
#define KP_F1 0 /* leftmost dot (tab) */
#define KP_F2 1 /* middle left dot */
#define KP_F3 2 /* up */
#define KP_F4 3 /* middle right dot */
#define KP_F5 4 /* rightmost dot */
#define KP_F6 5 /* C */
#define KP_F7 6 /* left */
#define KP_F8 7 /* down */
#define KP_F9 8 /* right */
#define KP_F10 9 /* enter */
#define KP_F11 10 /* R */
#define KP_F12 11 /* save */
#define KP_F13 12 /* redial */
#define KP_F14 13 /* speaker */
#define KP_F15 14 /* unused */
#define KP_F16 15 /* unused */
#define KP_F1 0 /* leftmost dot (tab) */
#define KP_F2 1 /* middle left dot */
#define KP_F3 2 /* up */
#define KP_F4 3 /* middle right dot */
#define KP_F5 4 /* rightmost dot */
#define KP_F6 5 /* C */
#define KP_F7 6 /* left */
#define KP_F8 7 /* down */
#define KP_F9 8 /* right */
#define KP_F10 9 /* enter */
#define KP_F11 10 /* R */
#define KP_F12 11 /* save */
#define KP_F13 12 /* redial */
#define KP_F14 13 /* speaker */
#define KP_F15 14 /* unused */
#define KP_F16 15 /* unused */
#define KP_RELEASE -1 /* key depressed */
#define KP_FORCE -2 /* key was pressed for more than force hz */
#define KP_IDLE -3 /* key was released and idle */
#define KP_RELEASE -1 /* key depressed */
#define KP_FORCE -2 /* key was pressed for more than force hz */
#define KP_IDLE -3 /* key was released and idle */
#define KP_1 '1'
#define KP_2 '2'
@ -158,8 +158,8 @@
#define KP_8 '8'
#define KP_9 '9'
#define KP_0 '0'
#define KP_STAR '*'
#define KP_HASH '#'
#define KP_STAR '*'
#define KP_HASH '#'
/*************************************************************************************************/
@ -198,7 +198,7 @@ static const char *whspace = " 0\n";
/* per mode character select (for 2-9) */
static const char *digits_sel[2][8] = {
{ /* small */
"abc2", /* 2 */
"abc2", /* 2 */
"def3", /* 3 */
"ghi4", /* 4 */
"jkl5", /* 5 */
@ -206,8 +206,8 @@ static const char *digits_sel[2][8] = {
"pqrs7", /* 7 */
"tuv8", /* 8 */
"wxyz9", /* 9 */
}, { /* capital */
"ABC2", /* 2 */
}, { /* capital */
"ABC2", /* 2 */
"DEF3", /* 3 */
"GHI4", /* 4 */
"JKL5", /* 5 */
@ -810,10 +810,10 @@ static void ensure_visible(int col, int row, int dx, int dy)
/* move to easier to use vars */
x1 = disp_col; y1 = disp_row;
x1 = disp_col; y1 = disp_row;
x2 = x1 + width; y2 = y1 + height;
a1 = col; b1 = row;
a2 = a1 + dx; b2 = b1 + dy;
a1 = col; b1 = row;
a2 = a1 + dx; b2 = b1 + dy;
/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
@ -891,7 +891,7 @@ void phone_putc(const char c)
blink_time = BLINK_HZ;
switch (c) {
case '\a': /* ignore bell */
case '\a': /* ignore bell */
case '\r': /* ignore carriage return */
break;
@ -900,7 +900,7 @@ void phone_putc(const char c)
ensure_visible(curs_col, curs_row, 1, 1);
break;
case 9: /* tab 8 */
case 9: /* tab 8 */
/* move to tab */
i = curs_col;
i |= 0x0008;
@ -1006,13 +1006,13 @@ unsigned int kp_get_col_mask(unsigned int row_mask)
/**************************************************************************************/
static const int kp_scancodes[KP_ROWS * KP_COLS] = {
KP_F1, KP_F3, KP_F4, KP_F2,
KP_F6, KP_F8, KP_F9, KP_F7,
KP_1, KP_3, KP_F11, KP_2,
KP_4, KP_6, KP_F12, KP_5,
KP_7, KP_9, KP_F13, KP_8,
KP_F1, KP_F3, KP_F4, KP_F2,
KP_F6, KP_F8, KP_F9, KP_F7,
KP_1, KP_3, KP_F11, KP_2,
KP_4, KP_6, KP_F12, KP_5,
KP_7, KP_9, KP_F13, KP_8,
KP_STAR, KP_HASH, KP_F14, KP_0,
KP_F5, KP_F15, KP_F16, KP_F10,
KP_F5, KP_F15, KP_F16, KP_F10,
};
static const int kp_repeats[KP_ROWS * KP_COLS] = {

2
board/netta/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o dsp.o
OBJS = $(BOARD).o flash.o dsp.o codec.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)

1475
board/netta/codec.c Normal file
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File diff suppressed because it is too large Load Diff

293
board/netta/dsp.c
View File

@ -1,5 +1,5 @@
/*
* Intracom TI6711 DSP
* Intracom TI6711/TI6412 DSP
*/
#include <common.h>
@ -12,6 +12,38 @@ struct ram_range {
u32 size;
};
#if defined(CONFIG_NETTA_6412)
static const struct ram_range int_ram[] = {
{ 0x00000000U, 0x00040000U },
};
static const struct ram_range ext_ram[] = {
{ 0x80000000U, 0x00100000U },
};
static const struct ram_range ranges[] = {
{ 0x00000000U, 0x00040000U },
{ 0x80000000U, 0x00100000U },
};
static inline u16 bit_invert(u16 d)
{
register u8 i;
register u16 r;
register u16 bit;
r = 0;
for (i = 0; i < 16; i++) {
bit = d & (1 << i);
if (bit != 0)
r |= 1 << (15 - i);
}
return r;
}
#else
static const struct ram_range int_ram[] = {
{ 0x00000000U, 0x00010000U },
};
@ -25,6 +57,8 @@ static const struct ram_range ranges[] = {
{ 0x80000000U, 0x00100000U },
};
#endif
/*******************************************************************************************************/
static inline int addr_in_int_ram(u32 addr)
@ -62,8 +96,11 @@ static volatile u32 *ti6711_delay = &dummy_delay;
static inline void dsp_go_slow(void)
{
volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
#if defined(CONFIG_NETTA_6412)
memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
#else
memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
#endif
memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
ti6711_delay = (u32 *)DUMMY_BASE;
@ -72,8 +109,11 @@ static inline void dsp_go_slow(void)
static inline void dsp_go_fast(void)
{
volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
#if defined(CONFIG_NETTA_6412)
memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
#else
memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
#endif
memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
ti6711_delay = &dummy_delay;
@ -89,62 +129,50 @@ static inline void dsp_delay(void)
static inline u16 dsp_read_hpic(void)
{
#if defined(CONFIG_NETTA_6412)
return bit_invert(*((volatile u16 *)DSP_BASE));
#else
return *((volatile u16 *)DSP_BASE);
#endif
}
static inline void dsp_write_hpic(u16 val)
{
#if defined(CONFIG_NETTA_6412)
*((volatile u16 *)DSP_BASE) = bit_invert(val);
#else
*((volatile u16 *)DSP_BASE) = val;
#endif
}
static inline void dsp_reset(void)
{
#if defined(CONFIG_NETTA_6412)
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
udelay(500);
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15));
udelay(500);
#else
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
udelay(250);
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7));
udelay(250);
}
static inline void dsp_init_hpic(void)
{
int i;
volatile u16 *p;
dsp_go_slow();
i = 0;
while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
dsp_delay();
i++;
}
dsp_delay();
/* write control register */
p = (volatile u16 *)DSP_BASE;
p[0] = 0x0000;
dsp_delay();
p[1] = 0x0000;
dsp_delay();
dsp_go_fast();
}
static inline void dsp_wait_hrdy(void)
{
int i;
i = 0;
while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
dsp_delay();
i++;
}
#endif
}
static inline u32 dsp_read_hpic_word(u32 addr)
{
u32 val;
volatile u16 *p;
#if defined(CONFIG_NETTA_6412)
p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
val = ((u32) bit_invert(p[0]) << 16);
/* dsp_delay(); */
val |= bit_invert(p[1]);
/* dsp_delay(); */
#else
p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
val = ((u32) p[0] << 16);
@ -152,40 +180,80 @@ static inline u32 dsp_read_hpic_word(u32 addr)
val |= p[1];
dsp_delay();
#endif
return val;
}
static inline u16 dsp_read_hpic_hi_hword(u32 addr)
{
#if defined(CONFIG_NETTA_6412)
return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
#else
return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
#endif
}
static inline u16 dsp_read_hpic_lo_hword(u32 addr)
{
#if defined(CONFIG_NETTA_6412)
return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
#else
return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
#endif
}
static inline void dsp_wait_hrdy(void)
{
int i;
i = 0;
#if defined(CONFIG_NETTA_6412)
while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
#else
while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
#endif
dsp_delay();
i++;
}
}
static inline void dsp_write_hpic_word(u32 addr, u32 val)
{
volatile u16 *p;
#if defined(CONFIG_NETTA_6412)
p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
p[0] = bit_invert((u16)(val >> 16));
/* dsp_delay(); */
p[1] = bit_invert((u16)val);
/* dsp_delay(); */
#else
p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
p[0] = (u16)(val >> 16);
dsp_delay();
p[1] = (u16)val;
dsp_delay();
#endif
}
static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
{
#if defined(CONFIG_NETTA_6412)
*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
#else
*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
#endif
}
static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
{
#if defined(CONFIG_NETTA_6412)
*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
#else
*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
#endif
}
/********************************************************************/
@ -193,21 +261,29 @@ static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
static inline void c62_write_word(u32 addr, u32 val)
{
dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
dsp_wait_hrdy();
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
dsp_wait_hrdy();
dsp_delay();
/* dsp_wait_hrdy();
dsp_delay(); */
#endif
dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
}
static u32 c62_read_word(u32 addr)
@ -215,26 +291,36 @@ static u32 c62_read_word(u32 addr)
u32 val;
dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
/* FETCH */
#if defined(CONFIG_NETTA_6412)
dsp_write_hpic_word(DSP_HPIC, 0x00100010);
#else
dsp_write_hpic(0x10);
dsp_delay();
#endif
dsp_wait_hrdy();
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
dsp_wait_hrdy();
dsp_delay();
/* dsp_wait_hrdy();
dsp_delay(); */
#endif
val |= dsp_read_hpic_lo_hword(DSP_HPID2);
#if !defined(CONFIG_NETTA_6412)
dsp_delay();
#endif
return val;
}
@ -300,8 +386,88 @@ static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
return 0;
}
#if defined(CONFIG_NETTA_6412)
#define DRAM_REGS_BASE 0x1800000
#define GBLCTL DRAM_REGS_BASE
#define CECTL1 (DRAM_REGS_BASE + 0x4)
#define CECTL0 (DRAM_REGS_BASE + 0x8)
#define CECTL2 (DRAM_REGS_BASE + 0x10)
#define CECTL3 (DRAM_REGS_BASE + 0x14)
#define SDCTL (DRAM_REGS_BASE + 0x18)
#define SDTIM (DRAM_REGS_BASE + 0x1C)
#define SDEXT (DRAM_REGS_BASE + 0x20)
#define SESEC1 (DRAM_REGS_BASE + 0x44)
#define SESEC0 (DRAM_REGS_BASE + 0x48)
#define SESEC2 (DRAM_REGS_BASE + 0x50)
#define SESEC3 (DRAM_REGS_BASE + 0x54)
#define MAR128 0x1848200
#define MAR129 0x1848204
void dsp_dram_initialize(void)
{
c62_write_word(GBLCTL, 0x120E4);
c62_write_word(CECTL1, 0x18);
c62_write_word(CECTL0, 0xD0);
c62_write_word(CECTL2, 0x18);
c62_write_word(CECTL3, 0x18);
c62_write_word(SDCTL, 0x47115000);
c62_write_word(SDTIM, 1536);
c62_write_word(SDEXT, 0x534A9);
#if 0
c62_write_word(SESEC1, 0);
c62_write_word(SESEC0, 0);
c62_write_word(SESEC2, 0);
c62_write_word(SESEC3, 0);
#endif
c62_write_word(MAR128, 1);
c62_write_word(MAR129, 0);
}
#endif
static inline void dsp_init_hpic(void)
{
int i;
volatile u16 *p;
#if defined(CONFIG_NETTA_6412)
dsp_go_fast();
#else
dsp_go_slow();
#endif
i = 0;
#if defined(CONFIG_NETTA_6412)
while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
#else
while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
#endif
dsp_delay();
i++;
}
if (i == 1000)
printf("HRDY stuck\n");
dsp_delay();
/* write control register */
p = (volatile u16 *)DSP_BASE;
p[0] = 0x0000;
dsp_delay();
p[1] = 0x0000;
dsp_delay();
#if !defined(CONFIG_NETTA_6412)
dsp_go_fast();
#endif
}
/***********************************************************************************************************/
#if !defined(CONFIG_NETTA_6412)
static const u8 bootstrap_rbin[5084] = {
0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
@ -931,18 +1097,23 @@ static void run_bootstrap(void)
dsp_go_fast();
}
#endif
/***********************************************************************************************************/
int board_post_dsp(int flags)
{
u32 ramS, ramE;
u32 data, data2;
int i, j, k, r;
int i, j, k;
#if !defined(CONFIG_NETTA_6412)
int r;
#endif
dsp_reset();
dsp_init_hpic();
#if !defined(CONFIG_NETTA_6412)
dsp_go_slow();
#endif
data = 0x11223344;
dsp_write_hpic_word(DSP_HPIA, data);
data2 = dsp_read_hpic_word(DSP_HPIA);
@ -958,7 +1129,9 @@ int board_post_dsp(int flags)
printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
goto err;
}
#if defined(CONFIG_NETTA_6412)
dsp_dram_initialize();
#else
r = load_bootstrap();
if (r < 0) {
printf("BOOTSTRAP: ** ERROR ** failed to load\n");
@ -968,7 +1141,7 @@ int board_post_dsp(int flags)
run_bootstrap();
dsp_go_fast();
#endif
printf(" ");
/* test RAMs */
@ -1001,12 +1174,12 @@ int board_post_dsp(int flags)
}
printf("\b\b\b\b \b\b\b\bOK\n");
#if !defined(CONFIG_NETTA_6412)
/* XXX assume that this works */
load_bootstrap();
run_bootstrap();
dsp_go_fast();
#endif
return 0;
err:
@ -1015,10 +1188,14 @@ err:
int board_dsp_reset(void)
{
#if !defined(CONFIG_NETTA_6412)
int r;
#endif
dsp_reset();
dsp_init_hpic();
#if defined(CONFIG_NETTA_6412)
dsp_dram_initialize();
#else
dsp_go_slow();
r = load_bootstrap();
if (r < 0)
@ -1026,6 +1203,6 @@ int board_dsp_reset(void)
run_bootstrap();
dsp_go_fast();
#endif
return 0;
}

29
board/netta/netta.c
View File

@ -63,6 +63,11 @@ int checkboard(void)
printf ("Intracom NETTA"
#if defined(CONFIG_NETTA_ISDN)
" with ISDN support"
#endif
#if defined(CONFIG_NETTA_6412)
" (DSP:TI6412)"
#else
" (DSP:TI6711)"
#endif
"\n"
);
@ -462,10 +467,10 @@ int last_stage_init(void)
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK (_B(28) | _B(31))
#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
#define PB_SP_MASK (_BR(22, 25))
#define PB_ODR_VAL 0
#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_DIRVAL 0
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
@ -479,7 +484,17 @@ int last_stage_init(void)
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
#if defined(CONFIG_NETTA_6412)
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
#else
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
#endif
#define PD_SP_DIRVAL 0
int board_early_init_f(void)
@ -492,11 +507,15 @@ int board_early_init_f(void)
/* CS1: NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
#if !defined(CONFIG_NETTA_6412)
/* CS2: DSP */
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
#else
/* CS6: DSP */
memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
#endif
/* CS4: External register chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
@ -525,7 +544,7 @@ int board_early_init_f(void)
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
ioport->iop_pdpar = PD_SP_MASK;
ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7));
/* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
return 0;
}

40
board/netta2/Makefile Normal file
View File

@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

28
board/netta2/config.mk Normal file
View File

@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# netVia Boards
#
TEXT_BASE = 0x40000000

506
board/netta2/flash.c Normal file
View File

@ -0,0 +1,506 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_byte(flash_info_t * info, ulong dest, uchar data);
static void flash_get_offsets(ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size << 20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#ifdef CFG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
flash_info[0].size = size;
return (size);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_MX:
printf("MXIC ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
uchar mid;
uchar pid;
vu_char *caddr = (vu_char *) addr;
ulong base = (ulong) addr;
/* Write auto select command: read Manufacturer ID */
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
mid = caddr[0];
switch (mid) {
case (AMD_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_FUJ;
break;
case (MX_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_MX;
break;
case (STM_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
pid = caddr[1]; /* device ID */
switch (pid) {
case (AMD_ID_LV400T & 0xFF):
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV400B & 0xFF):
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV800T & 0xFF):
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV800B & 0xFF):
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV160T & 0xFF):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV160B & 0xFF):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
case (STM_ID_M29W040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
#if 0 /* enable when device IDs are available */
case (AMD_ID_LV320T & 0xFF):
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV320B & 0xFF):
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
printf(" ");
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection: D0 = 1 if protected */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
caddr = (vu_char *) info->start[0];
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0xF0;
udelay(20000);
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
vu_char *addr = (vu_char *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_char *) (info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_char *) info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
while (cnt > 0) {
if ((rc = write_byte(info, addr++, *src++)) != 0) {
return (rc);
}
--cnt;
}
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_byte(flash_info_t * info, ulong dest, uchar data)
{
vu_char *addr = (vu_char *) (info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_char *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*((vu_char *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

664
board/netta2/netta2.c Normal file
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@ -0,0 +1,664 @@
/*
* (C) Copyright 2000-2004
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetTA4 board
*/
#include <common.h>
#include <miiphy.h>
#include "mpc8xx.h"
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif
/****************************************************************/
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
/****************************************************************/
/*
* Check Board Identity:
*
* Return 1 always.
*/
int checkboard(void)
{
printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
return (0);
}
/****************************************************************/
#define _NOT_USED_ 0xFFFFFFFF
/****************************************************************/
#define CS_0000 0x00000000
#define CS_0001 0x10000000
#define CS_0010 0x20000000
#define CS_0011 0x30000000
#define CS_0100 0x40000000
#define CS_0101 0x50000000
#define CS_0110 0x60000000
#define CS_0111 0x70000000
#define CS_1000 0x80000000
#define CS_1001 0x90000000
#define CS_1010 0xA0000000
#define CS_1011 0xB0000000
#define CS_1100 0xC0000000
#define CS_1101 0xD0000000
#define CS_1110 0xE0000000
#define CS_1111 0xF0000000
#define BS_0000 0x00000000
#define BS_0001 0x01000000
#define BS_0010 0x02000000
#define BS_0011 0x03000000
#define BS_0100 0x04000000
#define BS_0101 0x05000000
#define BS_0110 0x06000000
#define BS_0111 0x07000000
#define BS_1000 0x08000000
#define BS_1001 0x09000000
#define BS_1010 0x0A000000
#define BS_1011 0x0B000000
#define BS_1100 0x0C000000
#define BS_1101 0x0D000000
#define BS_1110 0x0E000000
#define BS_1111 0x0F000000
#define GPL0_AAAA 0x00000000
#define GPL0_AAA0 0x00200000
#define GPL0_AAA1 0x00300000
#define GPL0_000A 0x00800000
#define GPL0_0000 0x00A00000
#define GPL0_0001 0x00B00000
#define GPL0_111A 0x00C00000
#define GPL0_1110 0x00E00000
#define GPL0_1111 0x00F00000
#define GPL1_0000 0x00000000
#define GPL1_0001 0x00040000
#define GPL1_1110 0x00080000
#define GPL1_1111 0x000C0000
#define GPL2_0000 0x00000000
#define GPL2_0001 0x00010000
#define GPL2_1110 0x00020000
#define GPL2_1111 0x00030000
#define GPL3_0000 0x00000000
#define GPL3_0001 0x00004000
#define GPL3_1110 0x00008000
#define GPL3_1111 0x0000C000
#define GPL4_0000 0x00000000
#define GPL4_0001 0x00001000
#define GPL4_1110 0x00002000
#define GPL4_1111 0x00003000
#define GPL5_0000 0x00000000
#define GPL5_0001 0x00000400
#define GPL5_1110 0x00000800
#define GPL5_1111 0x00000C00
#define LOOP 0x00000080
#define EXEN 0x00000040
#define AMX_COL 0x00000000
#define AMX_ROW 0x00000020
#define AMX_MAR 0x00000030
#define NA 0x00000008
#define UTA 0x00000004
#define TODT 0x00000002
#define LAST 0x00000001
#define A10_AAAA GPL0_AAAA
#define A10_AAA0 GPL0_AAA0
#define A10_AAA1 GPL0_AAA1
#define A10_000A GPL0_000A
#define A10_0000 GPL0_0000
#define A10_0001 GPL0_0001
#define A10_111A GPL0_111A
#define A10_1110 GPL0_1110
#define A10_1111 GPL0_1111
#define RAS_0000 GPL1_0000
#define RAS_0001 GPL1_0001
#define RAS_1110 GPL1_1110
#define RAS_1111 GPL1_1111
#define CAS_0000 GPL2_0000
#define CAS_0001 GPL2_0001
#define CAS_1110 GPL2_1110
#define CAS_1111 GPL2_1111
#define WE_0000 GPL3_0000
#define WE_0001 GPL3_0001
#define WE_1110 GPL3_1110
#define WE_1111 GPL3_1111
/* #define CAS_LATENCY 3 */
#define CAS_LATENCY 2
const uint sdram_table[0x40] = {
#if CAS_LATENCY == 3
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
#endif
#if CAS_LATENCY == 2
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
_NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
#endif
/* UPT */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* EXC */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
_NOT_USED_,
/* REG */
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
};
#if CONFIG_NETTA2_VERSION == 2
static const uint nandcs_table[0x40] = {
/* RSS */
CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
CS_0000 | GPL4_0000 | GPL5_1111,
CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
/* RBS */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
CS_0000 | GPL4_1111 | GPL5_1111,
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
/* WBS */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* UPT */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* EXC */
CS_0001 | LAST,
_NOT_USED_,
/* REG */
CS_1110 ,
CS_0001 | LAST,
};
#endif
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
/* 8 */
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
void check_ram(unsigned int addr, unsigned int size)
{
unsigned int i, j, v, vv;
volatile unsigned int *p;
unsigned int pv;
p = (unsigned int *)addr;
pv = (unsigned int)p;
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
*p++ = pv;
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
v = (unsigned int)p;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
p++;
}
for (j = 0; j < 5; j++) {
switch (j) {
case 0: v = 0x00000000; break;
case 1: v = 0xffffffff; break;
case 2: v = 0x55555555; break;
case 3: v = 0xaaaaaaaa; break;
default:v = 0xdeadbeef; break;
}
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
*p = v;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
*p = ~v;
p++;
}
}
}
long int initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
/*
* Preliminary prescaler for refresh
*/
memctl->memc_mptpr = MPTPR_PTP_DIV8;
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
/* perform SDRAM initialisation sequence */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
udelay(1);
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
udelay(10000);
{
u32 d1, d2;
d1 = 0xAA55AA55;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
d1 = 0x55AA55AA;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
}
size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
if (size == 0) {
printf("SIZE is zero: LOOP on 0\n");
for (;;) {
*(volatile u32 *)0 = 0;
(void)*(volatile u32 *)0;
}
}
return size;
}
/* ------------------------------------------------------------------------- */
void reset_phys(void)
{
int phyno;
unsigned short v;
udelay(10000);
/* reset the damn phys */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
/* ------------------------------------------------------------------------- */
/* GP = general purpose, SP = special purpose (on chip peripheral) */
/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_GP_INMASK 0
#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
#define PA_SP_MASK 0
#define PA_ODR_VAL 0
#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK _B(28)
#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
#define PB_SP_MASK (_BR(22, 25))
#define PB_ODR_VAL 0
#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
#define PB_SP_DIRVAL 0
#if CONFIG_NETTA2_VERSION == 1
#define PC_GP_INMASK _BW(12)
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
#elif CONFIG_NETTA2_VERSION == 2
#define PC_GP_INMASK (_BW(13) | _BW(15))
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
#endif
#define PC_SP_MASK 0
#define PC_SOVAL 0
#define PC_INTVAL 0
#define PC_GP_OUTVAL (_BW(10) | _BW(11))
#define PC_SP_DIRVAL 0
#if CONFIG_NETTA2_VERSION == 1
#define PE_GP_INMASK _B(31)
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
#elif CONFIG_NETTA2_VERSION == 2
#define PE_GP_INMASK _BR(28, 31)
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
#endif
#define PE_SP_MASK 0
#define PE_ODR_VAL 0
#define PE_SP_DIRVAL 0
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* NAND chip select */
#if CONFIG_NETTA2_VERSION == 1
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
#elif CONFIG_NETTA2_VERSION == 2
upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
memctl->memc_mamr = 0; /* all clear */
#endif
/* DSP chip select */
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
#if CONFIG_NETTA2_VERSION == 1
memctl->memc_br4 &= ~BR_V;
#endif
memctl->memc_br5 &= ~BR_V;
memctl->memc_br6 &= ~BR_V;
memctl->memc_br7 &= ~BR_V;
ioport->iop_padat = PA_GP_OUTVAL;
ioport->iop_paodr = PA_ODR_VAL;
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
ioport->iop_papar = PA_SP_MASK;
cpm->cp_pbdat = PB_GP_OUTVAL;
cpm->cp_pbodr = PB_ODR_VAL;
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
cpm->cp_pbpar = PB_SP_MASK;
ioport->iop_pcdat = PC_GP_OUTVAL;
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
ioport->iop_pcso = PC_SOVAL;
ioport->iop_pcint = PC_INTVAL;
ioport->iop_pcpar = PC_SP_MASK;
cpm->cp_pedat = PE_GP_OUTVAL;
cpm->cp_peodr = PE_ODR_VAL;
cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
cpm->cp_pepar = PE_SP_MASK;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CFG_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
/* XXX add here the really funky stuff */
}
#endif
#ifdef CONFIG_SHOW_ACTIVITY
/* called from timer interrupt every 1/CFG_HZ sec */
void board_show_activity(ulong timestamp)
{
}
/* called when looping */
void show_activity(int arg)
{
}
#endif
#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
/* printf("overwrite_console called\n"); */
return 0;
}
#endif
extern int drv_phone_init(void);
extern int drv_phone_use_me(void);
extern int drv_phone_is_idle(void);
int misc_init_r(void)
{
return 0;
}
int last_stage_init(void)
{
#if CONFIG_NETTA2_VERSION == 2
int i;
#endif
#if CONFIG_NETTA2_VERSION == 2
/* assert peripheral reset */
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
for (i = 0; i < 10; i++)
udelay(1000);
((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12);
#endif
reset_phys();
return 0;
}

138
board/netta2/u-boot.lds Normal file
View File

@ -0,0 +1,138 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

135
board/netta2/u-boot.lds.debug Normal file
View File

@ -0,0 +1,135 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
cpu/mpc8xx/fec.c
View File

@ -383,7 +383,7 @@ static void fec_pin_init(int fecidx)
*/
fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE)
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* our PHYs are the limit at 2.5 MHz */
fecp->fec_mii_speed <<= 1;
#endif

21
include/configs/NETPHONE.h
View File

@ -49,8 +49,8 @@
/* #define CONFIG_XIN 10000000 */
#define CONFIG_XIN 50000000
#define MPC8XX_HZ 120000000
/* #define MPC8XX_HZ 66666666 */
/* #define MPC8XX_HZ 120000000 */
#define MPC8XX_HZ 66666666
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
@ -67,8 +67,8 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_AUTOSCRIPT
@ -336,16 +336,18 @@
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*
* Note: When TBS == 0 the timebase is independent of current cpu clock.
*/
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
#define CFG_SCCR (SCCR_TBS | \
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
#define CFG_SCCR (SCCR_TBS | \
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
@ -491,6 +493,8 @@
/* NAND */
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CFG_MAX_NAND_DEVICE 1
@ -571,6 +575,11 @@
/*****************************************************************************/
#define CFG_DIRECT_FLASH_TFTP
#define CFG_DIRECT_NAND_TFTP
/*****************************************************************************/
#if CONFIG_NETPHONE_VERSION == 1
#define STATUS_LED_BIT 0x00000008 /* bit 28 */
#elif CONFIG_NETPHONE_VERSION == 2

46
include/configs/NETTA.h
View File

@ -65,8 +65,8 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
@ -108,18 +108,22 @@
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CODEC | \
CFG_POST_DSP )
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_NAND | \
CFG_CMD_CDP | \
CFG_CMD_DHCP | \
CFG_CMD_PING | \
CFG_CMD_MII | \
CFG_CMD_PCMCIA | CFG_CMD_IDE | CFG_CMD_FAT | \
CFG_CMD_DIAG | \
CFG_CMD_FAT | \
CFG_CMD_IDE | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_NFS | \
CFG_CMD_CDP \
)
CFG_CMD_PCMCIA | \
CFG_CMD_PING | \
0)
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
@ -339,18 +343,20 @@
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*
* Note: When TBS == 0 the timebase is independent of current cpu clock.
*/
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
#define CFG_SCCR (SCCR_TBS | \
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL001 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
#define CFG_SCCR (SCCR_TBS | \
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
#endif
@ -604,10 +610,11 @@
/* NAND */
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CFG_MAX_NAND_DEVICE 1
#define NAND_NO_RB
/* #define NAND_NO_RB */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
@ -677,6 +684,17 @@
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
#define CONFIG_JFFS2_NAND_OFF (2 * 1024 * 1024) /* start of jffs2 partition */
#define CONFIG_JFFS2_NAND_SIZE (1*1024*1024) /* size of jffs2 partition */
#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
/*****************************************************************************/
#define CFG_DIRECT_FLASH_TFTP
#define CFG_DIRECT_NAND_TFTP
/*****************************************************************************/
#if 1

762
include/configs/NETTA2.h Normal file
View File

@ -0,0 +1,762 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetTA4 board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
#error Unsupported CONFIG_NETTA2 version
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
/* #define CONFIG_XIN 10000000 */
#define CONFIG_XIN 50000000
/* #define MPC8XX_HZ 120000000 */
#define MPC8XX_HZ 66666666
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
#define CONFIG_PREBOOT "echo;"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_AUTOSCRIPT
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY
#define CONFIG_MII 1
#define CONFIG_RMII 1 /* use RMII interface */
#define CONFIG_ETHER_ON_FEC1 1
#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
#define CONFIG_FEC1_PHY_NORXERR 1
#define CONFIG_ETHER_ON_FEC2 1
#define CONFIG_FEC2_PHY 4
#define CONFIG_FEC2_PHY_NORXERR 1
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_NAND | \
CFG_CMD_DHCP | \
CFG_CMD_PING | \
CFG_CMD_MII | \
CFG_CMD_CDP \
)
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#if defined(DEBUG)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#if CONFIG_NETTA2_VERSION == 2
#define CFG_FLASH_BASE4 0x40080000
#endif
#define CFG_RESET_ADDRESS 0x80000000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#if CONFIG_NETTA2_VERSION == 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#elif CONFIG_NETTA2_VERSION == 2
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#endif
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
#define CFG_ENV_OFFSET 0
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
#define CFG_ENV_OFFSET_REDUND 0
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else /* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
*/
#if CONFIG_XIN == 10000000
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 25000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 40000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 75000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
#elif CONFIG_XIN == 50000000
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 50MHz
#endif
#else
#error unsupported XIN freq
#endif
/*
*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*
* Note: When TBS == 0 the timebase is independent of current cpu clock.
*/
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
#endif
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CFG_DER 0x2002000F*/
#define CFG_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
#if CONFIG_NETTA2_VERSION == 2
#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
#endif
/*
* BR3 and OR3 (SDRAM)
*
*/
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
/*
* Memory Periodic Timer Prescaler
*/
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
#define CFG_MAMR_PTA 234
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CONFIG_ARTOS /* include ARTOS support */
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/****************************************************************/
#define DSP_SIZE 0x00010000 /* 64K */
#define NAND_SIZE 0x00010000 /* 64K */
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
/****************************************************************/
/* NAND */
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
#define CFG_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
#define NAND_DISABLE_CE(nand) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
} while(0)
#define NAND_ENABLE_CE(nand) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
} while(0)
#define NAND_CTL_CLRALE(nandptr) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
} while(0)
#define NAND_CTL_SETALE(nandptr) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
} while(0)
#define NAND_CTL_SETCLE(nandptr) \
do { \
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
} while(0)
#if CONFIG_NETTA2_VERSION == 1
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#elif CONFIG_NETTA2_VERSION == 2
#define NAND_WAIT_READY(nand) \
do { \
int _tries = 0; \
while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
if (++_tries > 100000) \
break; \
} while (0)
#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND_ADDRESS(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define WRITE_NAND(d, adr) \
do { \
*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
} while(0)
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
/*****************************************************************************/
#define CFG_DIRECT_FLASH_TFTP
#define CFG_DIRECT_NAND_TFTP
/*****************************************************************************/
#if CONFIG_NETTA2_VERSION == 1
#define STATUS_LED_BIT 0x00000008 /* bit 28 */
#elif CONFIG_NETTA2_VERSION == 2
#define STATUS_LED_BIT 0x00000080 /* bit 24 */
#endif
#define STATUS_LED_PERIOD (CFG_HZ / 2)
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#ifndef __ASSEMBLY__
/* LEDs */
/* led_id_t is unsigned int mask */
typedef unsigned int led_id_t;
#define __led_toggle(_msk) \
do { \
((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
} while(0)
#define __led_set(_msk, _st) \
do { \
if ((_st)) \
((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
else \
((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
} while(0)
#define __led_init(msk, st) __led_set(msk, st)
#endif
/***********************************************************************************************************
----------------------------------------------------------------------------------------------
(V1) version 1 of the board
(V2) version 2 of the board
----------------------------------------------------------------------------------------------
Pin definitions:
+------+----------------+--------+------------------------------------------------------------
| # | Name | Type | Comment
+------+----------------+--------+------------------------------------------------------------
| PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
| PA7 | DSP_INT | Output | DSP interrupt
| PA10 | DSP_RESET | Output | DSP reset
| PA14 | USBOE | Output | USB (1)
| PA15 | USBRXD | Output | USB (1)
| PB19 | BT_RTS | Output | Bluetooth (0)
| PB23 | BT_CTS | Output | Bluetooth (0)
| PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
| PB27 | SPICS_DISP | Output | Display chip select
| PB28 | SPI_RXD_3V | Input | SPI Data Rx
| PB29 | SPI_TXD | Output | SPI Data Tx
| PB30 | SPI_CLK | Output | SPI Clock
| PC10 | DISPA0 | Output | Display A0
| PC11 | BACKLIGHT | Output | Display backlit
| PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
| | IO_RESET | Output | (V2) General I/O reset
| PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
| | HOOK | Input | (V2) Hook input interrupt
| PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
| | F_RY_BY | Input | (V2) NAND F_RY_BY
| PE17 | F_ALE | Output | NAND F_ALE
| PE18 | F_CLE | Output | NAND F_CLE
| PE20 | F_CE | Output | NAND F_CE
| PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
| | LED | Output | (V2) LED
| PE27 | SPICS_ER | Output | External serial register CS
| PE28 | LEDIO1 | Output | (V1) LED
| | BKBR1 | Input | (V2) Keyboard input scan
| PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
| | BKBR2 | Input | (V2) Keyboard input scan
| PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
| | BKBR3 | Input | (V2) Keyboard input scan
| PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
| | BKBR4 | Input | (V2) Keyboard input scan
+------+----------------+--------+---------------------------------------------------
----------------------------------------------------------------------------------------------
Serial register input:
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
| 4 | HOOK | Hook switch
| 5 | BT_LINK | Bluetooth link status
| 6 | HOST_WAKE | Bluetooth host wake up
| 7 | OK_ETH | Cisco inline power OK status
+------+----------------+------------------------------------------------------------
----------------------------------------------------------------------------------------------
Chip selects:
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
| CS0 | CS0 | Boot flash
| CS1 | CS_FLASH | NAND flash
| CS2 | CS_DSP | DSP
| CS3 | DCS_DRAM | DRAM
| CS4 | CS_FLASH2 | (V2) 2nd flash
+------+----------------+------------------------------------------------------------
----------------------------------------------------------------------------------------------
Interrupts:
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
| IRQ1 | IRQ_DSP | DSP interrupt
| IRQ3 | S_INTER | DUSLIC ???
| IRQ4 | F_RY_BY | NAND
| IRQ7 | IRQ_MAX | MAX 3100 interrupt
+------+----------------+------------------------------------------------------------
----------------------------------------------------------------------------------------------
Interrupts on PCMCIA pins:
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
| IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
| IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
| IP_A2| RMII1_MDINT | PHY interrupt for #1
| IP_A3| RMII2_MDINT | PHY interrupt for #2
| IP_A5| HOST_WAKE | (V2) Bluetooth host wake
| IP_A6| OK_ETH | (V2) Cisco inline power OK
+------+----------------+------------------------------------------------------------
**************************************************************************************************/
#define CFG_CONSOLE_IS_IN_ENV 1
#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
#define CFG_CONSOLE_ENV_OVERWRITE 1
/*************************************************************************************************/
/* use board specific hardware */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_HW_WATCHDOG
#define CONFIG_SHOW_ACTIVITY
/*************************************************************************************************/
#define CONFIG_CDP_DEVICE_ID 20
#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */
#define CONFIG_CDP_PORT_ID "eth%d"
#define CONFIG_CDP_CAPABILITIES 0x00000010
#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__
#define CONFIG_CDP_PLATFORM "Intracom NetTA2"
#define CONFIG_CDP_TRIGGER 0x20020001
#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */
/*************************************************************************************************/
#define CONFIG_AUTO_COMPLETE 1
/*************************************************************************************************/
#define CONFIG_CRC32_VERIFY 1
/*************************************************************************************************/
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
/*************************************************************************************************/
#endif /* __CONFIG_H */

1
include/post.h
View File

@ -90,6 +90,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SPR 0x00000400
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#endif /* CONFIG_POST */

2
include/status_led.h
View File

@ -334,7 +334,7 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE)
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */
/************************************************************************/
#else

2
post/Makefile
View File

@ -27,7 +27,7 @@ SUBDIRS = cpu
LIB = libpost.a
AOBJS = cache_8xx.o
COBJS = cache.o cpu.o dsp.o ether.o
COBJS = cache.o codec.o cpu.o dsp.o ether.o
COBJS += i2c.o memory.o post.o rtc.o
COBJS += spr.o sysmon.o tests.o uart.o
COBJS += usb.o watchdog.o

48
post/codec.c Normal file
View File

@ -0,0 +1,48 @@
/*
* (C) Copyright 2004
* Pantelis Antoniou, Intracom S.A. , panto@intracom.gr
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* CODEC test
*
* This test verifies the connection and performs a memory test
* on any connected codec(s). The meat of the work is done
* in the board specific function.
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_CODEC
extern int board_post_codec(int flags);
int codec_post_test (int flags)
{
return board_post_codec(flags);
}
#endif /* CONFIG_POST & CFG_POST_CODEC */
#endif /* CONFIG_POST */

13
post/tests.c
View File

@ -44,6 +44,7 @@ extern int usb_post_test (int flags);
extern int spr_post_test (int flags);
extern int sysmon_post_test (int flags);
extern int dsp_post_test (int flags);
extern int codec_post_test (int flags);
extern int sysmon_init_f (void);
@ -209,6 +210,18 @@ struct post_test post_list[] =
CFG_POST_DSP
},
#endif
#if CONFIG_POST & CFG_POST_DSP
{
"CODEC test",
"codec",
"This test checks any connected codec(s).",
POST_RAM | POST_MANUAL,
&codec_post_test,
NULL,
NULL,
CFG_POST_CODEC
},
#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);