NAND: DaVinci: V2 Adding 4 BIT ECC support
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Sandeep Paulraj
Scott Wood
parent
f83b7f9e8a
commit
77b351cd0f
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@ -47,6 +47,16 @@
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/emif_defs.h>
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/* Definitions for 4-bit hardware ECC */
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#define NAND_TIMEOUT 10240
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#define NAND_ECC_BUSY 0xC
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#define NAND_4BITECC_MASK 0x03FF03FF
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#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
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#define ECC_STATE_NO_ERR 0x0
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#define ECC_STATE_TOO_MANY_ERRS 0x1
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#define ECC_STATE_ERR_CORR_COMP_P 0x2
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#define ECC_STATE_ERR_CORR_COMP_N 0x3
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static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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@ -170,6 +180,268 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
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}
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
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/*
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* TI uses a different layout for 4K page deviecs. Since the
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* eccpos filed can hold only a limited number of entries, adding
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* support for 4K page will result in compilation warnings
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* 4K Support will be added later
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*/
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#ifdef CONFIG_SYS_NAND_PAGE_2K
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.eccbytes = 40,
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.eccpos = {
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24, 25, 26, 27, 28,
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
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59, 60, 61, 62, 63,
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},
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.oobfree = {
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{.offset = 2, .length = 22, },
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},
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#endif
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};
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#endif
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static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u32 val;
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switch (mode) {
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case NAND_ECC_WRITE:
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case NAND_ECC_READ:
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/*
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* Start a new ECC calculation for reading or writing 512 bytes
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* of data.
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*/
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val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
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emif_regs->NANDFCR = val;
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break;
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case NAND_ECC_READSYN:
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val = emif_regs->NAND4BITECC1;
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break;
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default:
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break;
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}
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}
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static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
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{
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ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
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ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
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ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
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ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
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return 0;
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}
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static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code)
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{
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
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unsigned int const1 = 0, const2 = 0;
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unsigned char count1 = 0;
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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/*Convert 10 bit ecc value to 8 bit */
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for (count1 = 0; count1 < 2; count1++) {
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const2 = count1 * 5;
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const1 = count1 * 2;
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/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
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ecc_code[const2] = hw_4ecc[const1] & 0xFF;
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/*
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* Take 2 bits as LSB bits from val1 (count1=0) or val5
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* (count1=1) and 6 bits from val2 (count1=0) or
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* val5 (count1=1)
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*/
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ecc_code[const2 + 1] =
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((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
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0xFC);
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/*
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* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
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* 4 bits from val3 (count1=0) or val6 (count1=1)
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*/
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ecc_code[const2 + 2] =
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((hw_4ecc[const1] >> 22) & 0xF) |
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((hw_4ecc[const1 + 1] << 4) & 0xF0);
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/*
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* Take 6 bits from val3(count1=0) or val6 (count1=1) and
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* 2 bits from val4 (count1=0) or val7 (count1=1)
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*/
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ecc_code[const2 + 3] =
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((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
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((hw_4ecc[const1 + 1] >> 10) & 0xC0);
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/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
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ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
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}
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return 0;
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}
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static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct nand_chip *this = mtd->priv;
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unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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int i;
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
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unsigned short *pspare = NULL, *pspare1 = NULL;
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unsigned int numerrors, erroraddress, errorvalue;
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u32 val;
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/*
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* Check for an ECC where all bytes are 0xFF. If this is the case, we
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* will assume we are looking at an erased page and we should ignore
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* the ECC.
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*/
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for (i = 0; i < 10; i++) {
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if (read_ecc[i] != 0xFF)
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break;
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}
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if (i == 10)
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return 0;
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/* Convert 8 bit in to 10 bit */
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pspare = (unsigned short *)&read_ecc[2];
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pspare1 = (unsigned short *)&read_ecc[0];
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/* Take 10 bits from 0th and 1st bytes */
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ecc_10bit[0] = (*pspare1) & 0x3FF;
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/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
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ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
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| (((pspare[0]) << 6) & 0x3C0);
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/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
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ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
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/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
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ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
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| ((((pspare[1])) << 2) & 0x3FC);
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/* Take 8 bits from 5th byte and 2 bits from 6th byte */
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ecc_10bit[4] = ((pspare[1]) >> 8)
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| ((((pspare[2])) << 8) & 0x300);
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/* Take 6 bits from 6th byte and 4 bits from 7th byte */
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ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
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/* Take 4 bits from 7th byte and 6 bits from 8th byte */
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ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
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| ((((pspare[3])) << 4) & 0x3F0);
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/*Take 2 bits from 8th byte and 8 bits from 9th byte */
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ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
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/*
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* Write the parity values in the NAND Flash 4-bit ECC Load register.
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* Write each parity value one at a time starting from 4bit_ecc_val8
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* to 4bit_ecc_val1.
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*/
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for (i = 7; i >= 0; i--)
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emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
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/*
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* Perform a dummy read to the EMIF Revision Code and Status register.
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* This is required to ensure time for syndrome calculation after
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* writing the ECC values in previous step.
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*/
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val = emif_regs->NANDFSR;
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/*
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* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
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* A syndrome value of 0 means no bit errors. If the syndrome is
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* non-zero then go further otherwise return.
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*/
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
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hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
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return 0;
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/*
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* Clear any previous address calculation by doing a dummy read of an
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* error address register.
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*/
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val = emif_regs->NANDERRADD1;
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/*
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* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
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* register to 1.
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*/
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emif_regs->NANDFCR |= 1 << 13;
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/*
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* Wait for the corr_state field (bits 8 to 11)in the
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* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
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*/
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i = NAND_TIMEOUT;
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do {
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val = emif_regs->NANDFSR;
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val &= 0xc00;
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i--;
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} while ((i > 0) && val);
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iserror = emif_regs->NANDFSR;
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iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
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iserror = iserror >> 8;
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/*
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* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
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* corrected (five or more errors). The number of errors
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* calculated (err_num field) differs from the number of errors
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* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
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* correction complete (errors on bit 8 or 9).
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* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
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* complete (error exists).
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*/
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if (iserror == ECC_STATE_NO_ERR) {
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val = emif_regs->NANDERRVAL1;
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return 0;
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} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
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val = emif_regs->NANDERRVAL1;
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return -1;
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}
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numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
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/* Read the error address, error value and correct */
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for (i = 0; i < numerrors; i++) {
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if (i > 1) {
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erroraddress =
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((emif_regs->NANDERRADD2 >>
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(16 * (i & 1))) & 0x3FF);
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erroraddress = ((512 + 7) - erroraddress);
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errorvalue =
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((emif_regs->NANDERRVAL2 >>
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(16 * (i & 1))) & 0xFF);
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} else {
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erroraddress =
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((emif_regs->NANDERRADD1 >>
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(16 * (i & 1))) & 0x3FF);
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erroraddress = ((512 + 7) - erroraddress);
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errorvalue =
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((emif_regs->NANDERRVAL1 >>
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(16 * (i & 1))) & 0xFF);
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}
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/* xor the corrupt data with error value */
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if (erroraddress < 512)
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dat[erroraddress] ^= errorvalue;
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}
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return numerrors;
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}
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static int nand_davinci_dev_ready(struct mtd_info *mtd)
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{
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return emif_regs->NANDFSR & 0x1;
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@ -215,7 +487,7 @@ void davinci_nand_init(struct nand_chip *nand)
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{
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nand->chip_delay = 0;
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#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
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nand->options = NAND_USE_FLASH_BBT;
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nand->options |= NAND_USE_FLASH_BBT;
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#endif
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#ifdef CONFIG_SYS_NAND_HW_ECC
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nand->ecc.mode = NAND_ECC_HW;
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@ -227,7 +499,15 @@ void davinci_nand_init(struct nand_chip *nand)
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
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nand->ecc.size = 512;
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nand->ecc.bytes = 10;
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nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
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nand->ecc.correct = nand_davinci_4bit_correct_data;
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nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
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nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
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#endif
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/* Set address of hardware control function */
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nand->cmd_ctrl = nand_davinci_hwcontrol;
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@ -55,6 +55,16 @@ typedef struct {
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dv_reg NANDF2ECC;
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dv_reg NANDF3ECC;
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dv_reg NANDF4ECC;
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u_int8_t RSVD2[60];
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dv_reg NAND4BITECCLOAD;
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dv_reg NAND4BITECC1;
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dv_reg NAND4BITECC2;
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dv_reg NAND4BITECC3;
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dv_reg NAND4BITECC4;
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dv_reg NANDERRADD1;
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dv_reg NANDERRADD2;
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dv_reg NANDERRVAL1;
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dv_reg NANDERRVAL2;
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} emif_registers;
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typedef emif_registers *emifregs;
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