ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
c5a172a5fd
commit
779e975117
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@ -293,6 +293,7 @@ Stefan Roese <sr@denx.de>
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walnut PPC405GP
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yellowstone PPC440GR
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yosemite PPC440EP
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zeus PPC405EP
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P3M750 PPC750FX/GX/GL
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2
MAKEALL
2
MAKEALL
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@ -91,7 +91,7 @@ LIST_4xx=" \
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sc3 sequoia sequoia_nand taihu \
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taishan VOH405 VOM405 W7OLMC \
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W7OLMG walnut WUH405 XPEDITE1K \
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yellowstone yosemite yucca \
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yellowstone yosemite yucca zeus \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -1294,6 +1294,9 @@ yellowstone_config: unconfig
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yucca_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
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zeus_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
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#########################################################################
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## MPC8220 Systems
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#########################################################################
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@ -20,10 +20,12 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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long int spd_sdram(void);
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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long int spd_sdram(void);
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int board_early_init_f(void)
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{
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@ -34,6 +36,15 @@ int board_early_init_f(void)
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mtdcr(uictr, 0x00000010); /* set int trigger levels */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* Configure CPC0_PCI to enable PerWE as output
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* and enable the internal PCI arbiter if selected
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*/
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if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
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mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
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else
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mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
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return 0;
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}
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@ -50,6 +50,12 @@ int board_early_init_f(void)
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mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
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mtebc(pb3cr, CFG_EBC_PB3CR);
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/*
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* Configure CPC0_PCI to enable PerWE as output
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* and enable the internal PCI arbiter
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*/
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mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
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return 0;
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}
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o update.o
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SOBJS =
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,24 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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@ -0,0 +1,133 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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.resetvec 0xFFFFFFFC :
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{
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*(.resetvec)
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} = 0xffff
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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cpu/ppc4xx/start.o (.text)
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*(.text)
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*(.fixup)
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*(.got1)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rodata)
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*(.rodata1)
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*(.rodata.str1.4)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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*(.got)
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss :
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{
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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}
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_end = . ;
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PROVIDE (end = .);
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}
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@ -0,0 +1,105 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#if defined(CONFIG_ZEUS)
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u8 buf_zeus_ce[] = {
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/*00 01 02 03 04 05 06 07 */
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0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*08 09 0a 0b 0c 0d 0e 0f */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*10 11 12 13 14 15 16 17 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*18 19 1a 1b 1c 1d 1e 1f */
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0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
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u8 buf_zeus_pe[] = {
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/* CPU_CLOCK_DIV 1 = 00
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CPU_PLB_FREQ_DIV 3 = 10
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OPB_PLB_FREQ_DIV 2 = 01
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EBC_PLB_FREQ_DIV 2 = 00
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MAL_PLB_FREQ_DIV 1 = 00
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PCI_PLB_FRQ_DIV 3 = 10
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PLL_PLLOUTA = IS SET
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PLL_OPERATING = IS NOT SET
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PLL_FDB_MUL 10 = 1010
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PLL_FWD_DIV_A 3 = 101
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PLL_FWD_DIV_B 3 = 101
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TUNE = 0x2be */
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/*00 01 02 03 04 05 06 07 */
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0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*08 09 0a 0b 0c 0d 0e 0f */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*10 11 12 13 14 15 16 17 */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/*18 19 1a 1b 1c 1d 1e 1f */
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0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
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static int update_boot_eeprom(void)
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{
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u32 len = 0x20;
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u8 chip = CFG_I2C_EEPROM_ADDR;
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u8 *pbuf;
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u8 base;
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int i;
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if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
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pbuf = buf_zeus_pe;
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base = 0x40;
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} else {
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pbuf = buf_zeus_ce;
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base = 0x00;
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||||
}
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||||
|
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for (i = 0; i < len; i++, base++) {
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||||
if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
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||||
printf("i2c_write fail\n");
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||||
return 1;
|
||||
}
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||||
udelay(11000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
|
||||
{
|
||||
return update_boot_eeprom();
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
update_boot_eeprom, 1, 1, do_update_boot_eeprom,
|
||||
"update_boot_eeprom - update boot eeprom content\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,511 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <environment.h>
|
||||
#include <logbuff.h>
|
||||
#include <post.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define REBOOT_MAGIC 0x07081967
|
||||
#define REBOOT_NOP 0x00000000
|
||||
#define REBOOT_DO_POST 0x00000001
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
extern env_t *env_ptr;
|
||||
extern uchar default_environment[];
|
||||
|
||||
ulong flash_get_size(ulong base, int banknum);
|
||||
void env_crc_update(void);
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
static u32 start_time;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicer, 0x00000000); /* disable all ints */
|
||||
mtdcr(uiccr, 0x00000000);
|
||||
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
|
||||
mtdcr(uictr, 0x00000000); /* set int trigger levels */
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
|
||||
/*
|
||||
* Configure CPC0_PCI to enable PerWE as output
|
||||
*/
|
||||
mtdcr(cpc0_pci, CPC0_PCI_SPE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u32 pbcr;
|
||||
int size_val = 0;
|
||||
u32 post_magic;
|
||||
u32 post_val;
|
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC);
|
||||
post_val = in_be32((void *)CFG_POST_VAL);
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
|
||||
/*
|
||||
* Set special bootline bootparameter to pass this POST boot
|
||||
* mode to Linux to reset the username/password
|
||||
*/
|
||||
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
|
||||
|
||||
/*
|
||||
* Normally don't run POST tests, only when enabled
|
||||
* via the sw-reset button. So disable further tests
|
||||
* upon next bootup here.
|
||||
*/
|
||||
out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
|
||||
} else {
|
||||
/*
|
||||
* Only run POST when initiated via the sw-reset button mechanism
|
||||
*/
|
||||
post_word_store(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get current time
|
||||
*/
|
||||
start_time = get_timer(0);
|
||||
|
||||
/*
|
||||
* FLASH stuff...
|
||||
*/
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
/* adjust flash start and offset */
|
||||
mfebc(pb0cr, pbcr);
|
||||
switch (gd->bd->bi_flashsize) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
case 32 << 20:
|
||||
size_val = 5;
|
||||
break;
|
||||
case 64 << 20:
|
||||
size_val = 6;
|
||||
break;
|
||||
case 128 << 20:
|
||||
size_val = 7;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||
mtebc(pb0cr, pbcr);
|
||||
|
||||
/*
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
puts("Board: Zeus-");
|
||||
|
||||
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
|
||||
puts("PE");
|
||||
else
|
||||
puts("CE");
|
||||
|
||||
puts(" of BulletEndPoint");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
/* both LED's off */
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0);
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
|
||||
udelay(10000);
|
||||
/* and on again */
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 1);
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static u32 detect_sdram_size(void)
|
||||
{
|
||||
u32 val;
|
||||
u32 size;
|
||||
|
||||
mfsdram(mem_mb0cf, val);
|
||||
size = (4 << 20) << ((val & 0x000e0000) >> 17);
|
||||
|
||||
/*
|
||||
* Check if 2nd bank is enabled too
|
||||
*/
|
||||
mfsdram(mem_mb1cf, val);
|
||||
if (val & 1)
|
||||
size += (4 << 20) << ((val & 0x000e0000) >> 17);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
return detect_sdram_size();
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
unsigned long msr;
|
||||
unsigned long total_kbytes;
|
||||
|
||||
total_kbytes = detect_sdram_size();
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_EE));
|
||||
|
||||
for (k = 0; k < total_kbytes ;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0) {
|
||||
printf("%3d MB\r", k / 1024);
|
||||
}
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
mtmsr(msr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int default_env_var(char *buf, char *var)
|
||||
{
|
||||
char *ptr;
|
||||
char *val;
|
||||
|
||||
/*
|
||||
* Find env variable
|
||||
*/
|
||||
ptr = strstr(buf + 4, var);
|
||||
if (ptr == NULL) {
|
||||
printf("ERROR: %s not found!\n", var);
|
||||
return -1;
|
||||
}
|
||||
ptr += strlen(var) + 1;
|
||||
|
||||
/*
|
||||
* Now the ethaddr needs to be updated in the "normal"
|
||||
* environment storage -> redundant flash.
|
||||
*/
|
||||
val = ptr;
|
||||
setenv(var, val);
|
||||
printf("Updated %s from eeprom to %s!\n", var, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int restore_default(void)
|
||||
{
|
||||
char *buf;
|
||||
char *buf_save;
|
||||
u32 crc;
|
||||
|
||||
/*
|
||||
* Unprotect and erase environment area
|
||||
*/
|
||||
flash_protect(FLAG_PROTECT_CLEAR,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_sect_erase(CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
|
||||
|
||||
/*
|
||||
* Now restore default environment from U-Boot image
|
||||
* -> ipaddr, serverip...
|
||||
*/
|
||||
memset(env_ptr, 0, sizeof(env_t));
|
||||
memcpy(env_ptr->data, default_environment, ENV_SIZE);
|
||||
#ifdef CFG_REDUNDAND_ENVIRONMENT
|
||||
env_ptr->flags = 0xFF;
|
||||
#endif
|
||||
env_crc_update();
|
||||
gd->env_valid = 1;
|
||||
|
||||
/*
|
||||
* Read board specific values from I2C EEPROM
|
||||
* and set env variables accordingly
|
||||
* -> ethaddr, eth1addr, serial#
|
||||
*/
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
|
||||
if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
|
||||
(u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
|
||||
puts("\nError reading EEPROM!\n");
|
||||
} else {
|
||||
crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
|
||||
if (crc != *(u32 *)buf) {
|
||||
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
|
||||
return -1;
|
||||
}
|
||||
|
||||
default_env_var(buf, "ethaddr");
|
||||
buf += 8 + 18;
|
||||
default_env_var(buf, "eth1addr");
|
||||
buf += 9 + 18;
|
||||
default_env_var(buf, "serial#");
|
||||
}
|
||||
|
||||
/*
|
||||
* Finally save updated env variables back to flash
|
||||
*/
|
||||
saveenv();
|
||||
|
||||
free(buf_save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char *buf;
|
||||
char *buf_save;
|
||||
char str[32];
|
||||
u32 crc;
|
||||
char var[32];
|
||||
|
||||
if (argc < 4) {
|
||||
puts("ERROR!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
|
||||
memset(buf, 0, FACTORY_RESET_ENV_SIZE);
|
||||
|
||||
strcpy(var, "ethaddr");
|
||||
printf("Setting %s to %s\n", var, argv[1]);
|
||||
sprintf(str, "%s=%s", var, argv[1]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "eth1addr");
|
||||
printf("Setting %s to %s\n", var, argv[2]);
|
||||
sprintf(str, "%s=%s", var, argv[2]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "serial#");
|
||||
printf("Setting %s to %s\n", var, argv[3]);
|
||||
sprintf(str, "%s=%s", var, argv[3]);
|
||||
strcpy(buf + 4, str);
|
||||
|
||||
crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
|
||||
*(u32 *)buf_save = crc;
|
||||
|
||||
if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
|
||||
(u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
|
||||
puts("\nError writing EEPROM!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
free(buf_save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
setdef, 4, 1, do_set_default,
|
||||
"setdef - write board-specific values to EEPROM (ethaddr...)\n",
|
||||
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
|
||||
);
|
||||
|
||||
static inline int sw_reset_pressed(void)
|
||||
{
|
||||
return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
|
||||
}
|
||||
|
||||
int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
|
||||
{
|
||||
int delta;
|
||||
int count = 0;
|
||||
int post = 0;
|
||||
int factory_reset = 0;
|
||||
|
||||
if (!sw_reset_pressed()) {
|
||||
printf("SW-Reset already high (Button released)\n");
|
||||
printf("-> No action taken!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("Waiting for SW-Reset button to be released.");
|
||||
|
||||
while (1) {
|
||||
delta = get_timer(start_time);
|
||||
if (!sw_reset_pressed())
|
||||
break;
|
||||
|
||||
if ((delta > CFG_TIME_POST) && !post) {
|
||||
printf("\nWhen released now, POST tests will be started.");
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
|
||||
post = 1;
|
||||
}
|
||||
|
||||
if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
|
||||
printf("\nWhen released now, factory default values"
|
||||
" will be restored.");
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0);
|
||||
factory_reset = 1;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
if (!(count++ % 1000))
|
||||
printf(".");
|
||||
}
|
||||
|
||||
|
||||
printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
|
||||
|
||||
if (delta > CFG_TIME_FACTORY_RESET) {
|
||||
printf("Starting factory reset value restoration...\n");
|
||||
|
||||
/*
|
||||
* Restore default setting
|
||||
*/
|
||||
restore_default();
|
||||
|
||||
/*
|
||||
* Reset the board for default to become valid
|
||||
*/
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (delta > CFG_TIME_POST) {
|
||||
printf("Starting POST configuration...\n");
|
||||
|
||||
/*
|
||||
* Enable POST upon next bootup
|
||||
*/
|
||||
out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
|
||||
out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
|
||||
post_bootmode_init();
|
||||
|
||||
/*
|
||||
* Reset the logbuffer for a clean start
|
||||
*/
|
||||
logbuff_reset();
|
||||
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
chkreset, 1, 1, do_chkreset,
|
||||
"chkreset- Check for status of SW-reset button and act accordingly\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
u32 post_magic;
|
||||
u32 post_val;
|
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC);
|
||||
post_val = in_be32((void *)CFG_POST_VAL);
|
||||
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
|
@ -187,14 +187,14 @@ void sdram_init(void)
|
|||
/*
|
||||
* Disable memory controller.
|
||||
*/
|
||||
mtsdram0(mem_mcopt1, 0x00000000);
|
||||
mtsdram(mem_mcopt1, 0x00000000);
|
||||
|
||||
/*
|
||||
* Set MB0CF for bank 0.
|
||||
*/
|
||||
mtsdram0(mem_mb0cf, mb0cf[i].reg);
|
||||
mtsdram0(mem_sdtr1, sdtr1);
|
||||
mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
|
||||
mtsdram(mem_mb0cf, mb0cf[i].reg);
|
||||
mtsdram(mem_sdtr1, sdtr1);
|
||||
mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
|
||||
|
||||
udelay(200);
|
||||
|
||||
|
|
@ -203,7 +203,7 @@ void sdram_init(void)
|
|||
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
|
||||
* read/prefetch.
|
||||
*/
|
||||
mtsdram0(mem_mcopt1, 0x80800000);
|
||||
mtsdram(mem_mcopt1, 0x80800000);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
|
|
@ -215,10 +215,21 @@ void sdram_init(void)
|
|||
#ifdef CONFIG_SDRAM_BANK1
|
||||
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
|
||||
|
||||
mtsdram0(mem_mcopt1, 0x00000000);
|
||||
mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
|
||||
mtsdram0(mem_mcopt1, 0x80800000);
|
||||
mtsdram(mem_mcopt1, 0x00000000);
|
||||
mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
|
||||
mtsdram(mem_mcopt1, 0x80800000);
|
||||
udelay(10000);
|
||||
|
||||
/*
|
||||
* Check if 2nd bank is really available.
|
||||
* If the size not equal to the size of the first
|
||||
* bank, then disable the 2nd bank completely.
|
||||
*/
|
||||
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
|
||||
mb0cf[i].size) {
|
||||
mtsdram(mem_mb1cf, 0);
|
||||
mtsdram(mem_mcopt1, 0);
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,8 +29,6 @@
|
|||
|
||||
#include <config.h>
|
||||
|
||||
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
|
||||
|
||||
#define ONE_BILLION 1000000000
|
||||
|
||||
struct sdram_conf_s {
|
||||
|
|
|
|||
|
|
@ -1869,38 +1869,7 @@ ppc405ep_init:
|
|||
ori r3,r3,CFG_EBC_PB4CR@l
|
||||
mtdcr ebccfgd,r3
|
||||
#endif
|
||||
#ifdef CONFIG_TAIHU
|
||||
mfdcr r4, CPC0_BOOT
|
||||
andi. r5, r4, CPC0_BOOT_SEP@l
|
||||
bne strap_0 /* serial eeprom present */
|
||||
#endif
|
||||
|
||||
#ifndef CFG_CPC0_PCI
|
||||
li r3,CPC0_PCI_HOST_CFG_EN
|
||||
#ifdef CONFIG_BUBINGA
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Check FPGA for PCI internal/external arbitration
|
||||
! If board is set to internal arbitration, update cpc0_pci
|
||||
!-----------------------------------------------------------------------
|
||||
*/
|
||||
addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
|
||||
ori r5,r5,FPGA_REG1@l
|
||||
lbz r5,0x0(r5) /* read to get PCI arb selection */
|
||||
andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
|
||||
beq ..pci_cfg_set /* if not set, then bypass reg write*/
|
||||
#endif
|
||||
ori r3,r3,CPC0_PCI_ARBIT_EN
|
||||
#ifdef CONFIG_TAIHU
|
||||
ori r3,r3,CPC0_PCI_SPE
|
||||
#endif
|
||||
#else /* CFG_CPC0_PCI */
|
||||
li r3,CFG_CPC0_PCI
|
||||
#endif /* CFG_CPC0_PCI */
|
||||
..pci_cfg_set:
|
||||
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
|
||||
|
||||
strap_0:
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Check to see if chip is in bypass mode.
|
||||
|
|
@ -1966,6 +1935,21 @@ strap_0:
|
|||
bne _pci_66mhz
|
||||
#endif /* CONFIG_TAIHU */
|
||||
|
||||
#if defined(CONFIG_ZEUS)
|
||||
mfdcr r4, CPC0_BOOT
|
||||
andi. r5, r4, CPC0_BOOT_SEP@l
|
||||
bne strap_1 /* serial eeprom present */
|
||||
lis r3,0x0000
|
||||
addi r3,r3,0x3030
|
||||
lis r4,0x8042
|
||||
addi r4,r4,0x223e
|
||||
b 1f
|
||||
strap_1:
|
||||
mfdcr r3, CPC0_PLLMR0
|
||||
mfdcr r4, CPC0_PLLMR1
|
||||
b 1f
|
||||
#endif
|
||||
|
||||
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
|
||||
ori r3,r3,PLLMR0_DEFAULT@l /* */
|
||||
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
|
||||
|
|
@ -1982,9 +1966,9 @@ _pci_66mhz:
|
|||
strap_1:
|
||||
mfdcr r3, CPC0_PLLMR0
|
||||
mfdcr r4, CPC0_PLLMR1
|
||||
1:
|
||||
#endif /* CONFIG_TAIHU */
|
||||
|
||||
1:
|
||||
b pll_write /* Write the CPC0_PLLMR with new value */
|
||||
|
||||
pll_done:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
|
||||
Storage of the board specific values (ethaddr...)
|
||||
-------------------------------------------------
|
||||
|
||||
The board specific environment variables that should be unique
|
||||
for each individual board, can be stored in the I2C EEPROM. This
|
||||
will be done from offset 0x80 with the length of 0x80 bytes. The
|
||||
following command can be used to store the values here:
|
||||
|
||||
=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
|
||||
|
||||
ethaddr eth1addr serial#
|
||||
|
||||
Now those 3 values are stored into the I2C EEPROM. A CRC is added
|
||||
to make sure that the values get not corrupted.
|
||||
|
||||
|
||||
SW-Reset Pushbutton handling:
|
||||
-----------------------------
|
||||
|
||||
The SW-reset push button is connected to a GPIO input too. This
|
||||
way U-Boot can "see" how long the SW-reset was pressed, and a
|
||||
specific action can be taken. Two different actions are supported:
|
||||
|
||||
a) Release after more than 5 seconds and less then 10 seconds:
|
||||
-> Run POST
|
||||
|
||||
Please note, that the POST test will take a while (approx. 1 min
|
||||
on the 128MByte board). This is mainly due to the system memory
|
||||
test.
|
||||
|
||||
b) Release after more than 10 seconds:
|
||||
-> Restore factory default settings
|
||||
|
||||
The factory default values are restored. The default environment
|
||||
variables are restored (ipaddr, serverip...) and the board
|
||||
specific values (ethaddr, eth1addr and serial#) are restored
|
||||
to the environment from the I2C EEPROM. Also a bootline parameter
|
||||
is added to the Linux bootline to signal the Linux kernel upon
|
||||
the next startup, that the factory defaults should be restored.
|
||||
|
||||
The command to check this sw-reset status and act accordingly is
|
||||
|
||||
=> chkreset
|
||||
|
||||
This command is added to the default "bootcmd", so that it is called
|
||||
automatically upon startup.
|
||||
|
||||
Also, the 2 LED's are used to indicate the current status of this
|
||||
command (time passed since pushing the button). When the POST test
|
||||
will be run, the green LED will be switched off, and when the
|
||||
factory restore will be initiated, the reg LED will be switched off.
|
||||
|
||||
|
||||
Loggin of POST results:
|
||||
-----------------------
|
||||
|
||||
The results of the POST tests are logged in a logbuffer located at the end
|
||||
of the onboard memory. It can be accessed with the U-Boot command "log":
|
||||
|
||||
=> log show
|
||||
<4>POST memory PASSED
|
||||
<4>POST cache PASSED
|
||||
<4>POST cpu PASSED
|
||||
<4>POST uart PASSED
|
||||
<4>POST ethernet PASSED
|
||||
|
||||
The DENX Linux kernel tree has support for this log buffer included. Exactly
|
||||
this buffer is used for logging of all kernel messages too. By enabling the
|
||||
compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
|
||||
can access the U-Boot log messages from Linux too.
|
||||
|
||||
2007-08-10, Stefan Roese <sr@denx.de>
|
||||
|
|
@ -0,0 +1,375 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* zeus.h - configuration for Zeus board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ZEUS 1 /* Board is Zeus */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_405EP 1 /* Specifc 405EP support*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
|
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
|
||||
#define CONFIG_HAS_ETH1 1
|
||||
#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
#define CONFIG_PHY_RESET 1
|
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_LOG | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO)
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CFG_POST_MEMORY | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_CACHE | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_ETHER)
|
||||
|
||||
#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
|
||||
|
||||
/* Define here the base-addresses of the UARTs to test in POST */
|
||||
#define CFG_POST_UART_TABLE {UART0_BASE}
|
||||
|
||||
#define CONFIG_LOGBUFFER
|
||||
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
|
||||
|
||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
|
||||
*/
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
|
||||
|
||||
/* SDRAM timings used in datasheet */
|
||||
#define CFG_SDRAM_CL 3 /* CAS latency */
|
||||
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
|
||||
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
|
||||
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
|
||||
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#define CFG_BASE_BAUD 691200
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/* these are for the ST M24C02 2kbit serial i2c eeprom */
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*
|
||||
* The layout of the I2C EEPROM, used for bootstrap setup and for board-
|
||||
* specific values, like ethaddr... that can be restored via the sw-reset
|
||||
* button
|
||||
*/
|
||||
#define FACTORY_RESET_I2C_EEPROM 0x50
|
||||
#define FACTORY_RESET_ENV_OFFS 0x80
|
||||
#define FACTORY_RESET_ENV_SIZE 0x80
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFF000000
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CFG_OCM_DATA_ADDR 0xF8000000
|
||||
#define CFG_OCM_DATA_SIZE 0x1000
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */
|
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
/* reserve some memory for POST and BOOT limit info */
|
||||
#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
|
||||
|
||||
/* extra data in OCM */
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
|
||||
#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8)
|
||||
#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash 16M) initialization */
|
||||
#define CFG_EBC_PB0AP 0x05815600
|
||||
#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific)
|
||||
*
|
||||
* GPIO0[0] - External Bus Controller BLAST output
|
||||
* GPIO0[1-9] - Instruction trace outputs
|
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
|
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
||||
* GPIO0[28-29] - UART1 data signal input/output
|
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
|
||||
*/
|
||||
#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */
|
||||
#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
|
||||
#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
|
||||
#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
|
||||
#define CFG_GPIO0_TSRH 0x00000000
|
||||
#define CFG_GPIO0_TSRL 0x00000000
|
||||
#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
|
||||
#define CFG_GPIO0_ODR 0x00000000
|
||||
|
||||
#define CFG_GPIO_SW_RESET 1
|
||||
#define CFG_GPIO_ZEUS_PE 12
|
||||
#define CFG_GPIO_LED_RED 22
|
||||
#define CFG_GPIO_LED_GREEN 23
|
||||
|
||||
/* Time in milli-seconds */
|
||||
#define CFG_TIME_POST 5000
|
||||
#define CFG_TIME_FACTORY_RESET 10000
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/* ENVIRONMENT VARS */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
|
||||
#define CONFIG_IPADDR 192.168.1.10
|
||||
#define CONFIG_SERVERIP 192.168.1.100
|
||||
#define CONFIG_GATEWAYIP 192.168.1.100
|
||||
#define CONFIG_ETHADDR 50:00:00:00:06:00
|
||||
#define CONFIG_ETH1ADDR 50:00:00:00:06:01
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"logversion=2\0" \
|
||||
"hostname=zeus\0" \
|
||||
"netdev=eth0\0" \
|
||||
"ethact=ppc_4xx_eth0\0" \
|
||||
"netmask=255.255.255.0\0" \
|
||||
"ramdisk_size=50000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw" \
|
||||
" nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw" \
|
||||
" ramdisk=${ramdisk_size}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0," \
|
||||
"${baudrate}\0" \
|
||||
"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"run nfsargs addip addtty;bootm\0" \
|
||||
"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"tftp ${ramdisk_mem_addr} ${file_fs};" \
|
||||
"run ramargs addip addtty;" \
|
||||
"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
|
||||
"rootpath=/target_fs/zeus\0" \
|
||||
"kernel_fl_addr=ff000000\0" \
|
||||
"kernel_mem_addr=200000\0" \
|
||||
"ramdisk_fl_addr=ff300000\0" \
|
||||
"ramdisk_mem_addr=4000000\0" \
|
||||
"uboot_fl_addr=fffc0000\0" \
|
||||
"uboot_mem_addr=100000\0" \
|
||||
"file_uboot=/zeus/u-boot.bin\0" \
|
||||
"tftp_uboot=tftp 100000 ${file_uboot}\0" \
|
||||
"update_uboot=protect off fffc0000 ffffffff;" \
|
||||
"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
|
||||
"protect on fffc0000 ffffffff\0" \
|
||||
"upd_uboot=run tftp_uboot;run update_uboot\0" \
|
||||
"file_kernel=/zeus/uImage_ba\0" \
|
||||
"tftp_kernel=tftp 100000 ${file_kernel}\0" \
|
||||
"update_kernel=protect off ff000000 ff17ffff;" \
|
||||
"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
|
||||
"upd_kernel=run tftp_kernel;run update_kernel\0" \
|
||||
"file_fs=/zeus/rootfs_ba.img\0" \
|
||||
"tftp_fs=tftp 100000 ${file_fs}\0" \
|
||||
"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
|
||||
"cp.b 100000 ff300000 580000\0" \
|
||||
"upd_fs=run tftp_fs;run update_fs\0" \
|
||||
"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
|
||||
""
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -541,6 +541,18 @@
|
|||
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
|
|
@ -1226,6 +1238,8 @@
|
|||
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
|
||||
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
|
||||
|
||||
#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
|
||||
#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue