MPC512x: factor out common code
Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
This commit is contained in:
Wolfgang Denk
parent
0549353a6b
commit
7629f1c06b
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@ -27,6 +27,7 @@
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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@ -34,9 +35,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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extern int mpc5121_diu_init(void);
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extern void ide_set_reset(int idereset);
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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@ -53,14 +51,9 @@ extern void ide_set_reset(int idereset);
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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long int fixed_sdram(void);
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr;
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/*
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@ -71,14 +64,7 @@ int board_early_init_f(void)
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CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.lpcs2aw);
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__asm__ __volatile__ ("isync");
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sync_law(&im->sysconf.lpcs2aw);
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/*
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* Initialize Local Window for the On Board SRAM access
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@ -88,14 +74,7 @@ int board_early_init_f(void)
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CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.lpcs6aw);
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__asm__ __volatile__ ("isync");
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sync_law(&im->sysconf.lpcs6aw);
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/*
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* Configure Flash Speed
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@ -124,100 +103,6 @@ phys_size_t initdram (int board_type)
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return fixed_sdram();
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}
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/*
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* fixed sdram init:
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* The board doesn't use memory modules that have serial presence
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* detect or similar mechanism for discovery of the DRAM settings
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*/
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long int fixed_sdram (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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u32 i;
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/* Initialize IO Control */
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out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
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/* Initialize DDR Local Window */
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out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
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out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.ddrlaw.ar);
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__asm__ __volatile__ ("isync");
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/* Enable DDR */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
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/* Initialize DDR Priority Manager */
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out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
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out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
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out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
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out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
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out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
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out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
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out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
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out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
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out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
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out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
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out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
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out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
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out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
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out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
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out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
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out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
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out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
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out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
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out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
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out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
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out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
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out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
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out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
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/* Initialize MDDRC */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
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out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
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out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
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/* Initialize DDR */
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for (i = 0; i < 10; i++)
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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/* Start MDDRC */
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
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return msize;
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}
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int misc_init_r(void)
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{
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u32 tmp;
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@ -295,7 +180,6 @@ static iopin_t ioregs_init[] = {
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},
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};
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int checkboard (void)
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{
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puts("Board: ARIA\n");
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@ -28,6 +28,7 @@
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -46,9 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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int eeprom_write_enable(unsigned dev_addr, int state)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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@ -61,18 +59,7 @@ int eeprom_write_enable(unsigned dev_addr, int state)
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else
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clrbits_be32(&im->gpio.gpdat, 0x00100000);
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return 0;
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}
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync.
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*/
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static inline void sync_law(volatile void *addr)
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{
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in_be32(addr);
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__asm__ __volatile__ ("isync");
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return 0;
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}
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int board_early_init_f(void)
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@ -146,93 +133,6 @@ int board_early_init_f(void)
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return 0;
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}
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/*
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* fixed sdram init:
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* The board doesn't use memory modules that have serial presence
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* detect or similar mechanism for discovery of the DRAM settings
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*/
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long int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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u32 i;
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/* Initialize IO Control */
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out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
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/* Initialize DDR Local Window */
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out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
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out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
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sync_law(&im->sysconf.ddrlaw.ar);
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/* Enable DDR */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
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/* Initialize DDR Priority Manager */
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out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
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out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
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out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
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out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
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out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
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out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
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out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
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out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
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out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
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out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
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out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
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out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
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out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
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out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
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out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
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out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
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out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
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out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
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out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
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out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
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out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
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out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
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out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
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/* Initialize MDDRC */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
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out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
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out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
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/* Initialize DDR */
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for (i = 0; i < 10; i++)
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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/* Start MDDRC */
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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return get_ram_size(0, fixed_sdram());
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@ -26,6 +26,7 @@
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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@ -36,9 +37,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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extern int mpc5121_diu_init(void);
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extern void ide_set_reset(int idereset);
|
||||
|
||||
/* Clocks in use */
|
||||
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
|
||||
CLOCK_SCCR1_DDR_EN | \
|
||||
|
|
@ -56,10 +54,6 @@ extern void ide_set_reset(int idereset);
|
|||
CLOCK_SCCR2_MEM_EN | \
|
||||
CLOCK_SCCR2_SPDIF_EN)
|
||||
|
||||
#define CSAW_START(start) ((start) & 0xFFFF0000)
|
||||
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
|
||||
|
||||
long int fixed_sdram(void);
|
||||
void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
|
||||
|
||||
/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
|
||||
|
|
@ -84,10 +78,10 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
|
|||
out_8(csreg, v);
|
||||
}
|
||||
|
||||
int board_early_init_f (void)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
u32 lpcaw, spridr;
|
||||
u32 spridr;
|
||||
|
||||
/*
|
||||
* Initialize Local Window for the CPLD registers access (CS2 selects
|
||||
|
|
@ -98,14 +92,7 @@ int board_early_init_f (void)
|
|||
CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
|
||||
);
|
||||
out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
|
||||
|
||||
/*
|
||||
* According to MPC5121e RM, configuring local access windows should
|
||||
* be followed by a dummy read of the config register that was
|
||||
* modified last and an isync
|
||||
*/
|
||||
lpcaw = in_be32(&im->sysconf.lpcs6aw);
|
||||
__asm__ __volatile__ ("isync");
|
||||
sync_law(&im->sysconf.lpcs2aw);
|
||||
|
||||
/*
|
||||
* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
|
||||
|
|
@ -146,104 +133,11 @@ int board_early_init_f (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
u32 msize = 0;
|
||||
|
||||
msize = fixed_sdram ();
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
/*
|
||||
* fixed sdram init -- the board doesn't use memory modules that have serial presence
|
||||
* detect or similar mechanism for discovery of the DRAM settings
|
||||
*/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2 (msize);
|
||||
u32 i;
|
||||
|
||||
/* Initialize IO Control */
|
||||
out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
|
||||
|
||||
/* Initialize DDR Local Window */
|
||||
out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
|
||||
out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
|
||||
|
||||
/*
|
||||
* According to MPC5121e RM, configuring local access windows should
|
||||
* be followed by a dummy read of the config register that was
|
||||
* modified last and an isync
|
||||
*/
|
||||
in_be32(&im->sysconf.ddrlaw.ar);
|
||||
__asm__ __volatile__ ("isync");
|
||||
|
||||
/* Enable DDR */
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
|
||||
|
||||
/* Initialize DDR Priority Manager */
|
||||
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
|
||||
out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
|
||||
out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
|
||||
out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
|
||||
out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
|
||||
out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
|
||||
out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
|
||||
out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
|
||||
out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
|
||||
out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
|
||||
out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
|
||||
out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
|
||||
out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
|
||||
out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
|
||||
out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
|
||||
out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
|
||||
out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
|
||||
out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
|
||||
out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
|
||||
out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
|
||||
out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
|
||||
out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
|
||||
out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
|
||||
|
||||
/* Initialize MDDRC */
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
|
||||
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
|
||||
out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
|
||||
out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
|
||||
|
||||
/* Initialize DDR */
|
||||
for (i = 0; i < 10; i++)
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
|
||||
/* Start MDDRC */
|
||||
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
|
||||
msize = fixed_sdram();
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,15 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common)
|
|||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
|
||||
COBJS-y := cpu.o
|
||||
COBJS-y += traps.o
|
||||
COBJS-y += cpu_init.o
|
||||
COBJS-y += fixed_sdram.o
|
||||
COBJS-y += i2c.o
|
||||
COBJS-y += interrupts.o
|
||||
COBJS-y += iopin.o
|
||||
COBJS-y += serial.o
|
||||
COBJS-y += speed.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += diu.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2009 DENX Software Engineering
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mpc512x.h>
|
||||
|
||||
/*
|
||||
* fixed sdram init:
|
||||
* The board doesn't use memory modules that have serial presence
|
||||
* detect or similar mechanism for discovery of the DRAM settings
|
||||
*/
|
||||
long int fixed_sdram(void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
u32 i;
|
||||
|
||||
/* Initialize IO Control */
|
||||
out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
|
||||
|
||||
/* Initialize DDR Local Window */
|
||||
out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
|
||||
out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
|
||||
sync_law(&im->sysconf.ddrlaw.ar);
|
||||
|
||||
/* Enable DDR */
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
|
||||
|
||||
/* Initialize DDR Priority Manager */
|
||||
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
|
||||
out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
|
||||
out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
|
||||
out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
|
||||
out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
|
||||
out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
|
||||
out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
|
||||
out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
|
||||
out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
|
||||
out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
|
||||
out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
|
||||
out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
|
||||
out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
|
||||
out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
|
||||
out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
|
||||
out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
|
||||
out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
|
||||
out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
|
||||
out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
|
||||
out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
|
||||
out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
|
||||
out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
|
||||
out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
|
||||
|
||||
/* Initialize MDDRC */
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
|
||||
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
|
||||
out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
|
||||
out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
|
||||
|
||||
/* Initialize DDR */
|
||||
for (i = 0; i < 10; i++)
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
|
||||
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
|
||||
|
||||
/* Start MDDRC */
|
||||
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
|
||||
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* include/asm-ppc/mpc512x.h
|
||||
*
|
||||
* Prototypes, etc. for the Freescale MPC512x embedded cpu chips
|
||||
*
|
||||
* 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASMPPC_MPC512X_H
|
||||
#define __ASMPPC_MPC512X_H
|
||||
|
||||
/*
|
||||
* macros for manipulating CSx_START/STOP
|
||||
*/
|
||||
#define CSAW_START(start) ((start) & 0xFFFF0000)
|
||||
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
|
||||
|
||||
/*
|
||||
* Inlines
|
||||
*/
|
||||
|
||||
/*
|
||||
* According to MPC5121e RM, configuring local access windows should
|
||||
* be followed by a dummy read of the config register that was
|
||||
* modified last and an isync.
|
||||
*/
|
||||
static inline void sync_law(volatile void *addr)
|
||||
{
|
||||
in_be32(addr);
|
||||
__asm__ __volatile__ ("isync");
|
||||
}
|
||||
|
||||
/*
|
||||
* Prototypes
|
||||
*/
|
||||
extern long int fixed_sdram(void);
|
||||
extern int mpc5121_diu_init(void);
|
||||
extern void ide_set_reset(int idereset);
|
||||
|
||||
#endif /* __ASMPPC_MPC512X_H */
|
||||
Loading…
Reference in New Issue