Fix variable CPU clock for MPC859/866 systems for low CPU clocks
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wdenk
parent
6876609446
commit
75d1ea7f6a
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@ -2,6 +2,8 @@
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Changes since U-Boot 1.0.1:
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======================================================================
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* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
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* Implement adaptive SDRAM timing configuration based on actual CPU
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clock frequency for INCA-IP; fix problem with board hanging when
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switching from 150MHz to 100MHz
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18
README
18
README
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@ -415,12 +415,28 @@ The following options need to be configured:
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Define exactly one of
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CONFIG_MPC8240, CONFIG_MPC8245
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- 8xx CPU Options: (if using an 8xx cpu)
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- 8xx CPU Options: (if using an MPC8xx cpu)
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Define one or more of
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CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() cannot work
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e.g. if there is no 32KHz
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reference PIT/RTC clock
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- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
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CFG_866_OSCCLK
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CFG_866_CPUCLK_MIN
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CFG_866_CPUCLK_MAX
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CFG_866_CPUCLK_DEFAULT
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See doc/README.MPC866
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CFG_MEASURE_CPUCLK
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Define this to measure the actual CPU clock instead
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of relying on the correctness of the configured
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values. Mostly useful for board bringup to make sure
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the PLL is locked at the intended frequency. Note
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that this requires a (stable) reference clock (32 kHz
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RTC clock),
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- Linux Kernel Interface:
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CONFIG_CLOCKS_IN_MHZ
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@ -128,14 +128,6 @@ int checkboard (void)
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break;
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putc (*s);
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}
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#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
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printf (" [%d.%d...%d.%d MHz]",
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CFG_866_CPUCLK_MIN / 1000000,
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((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CFG_866_CPUCLK_MAX / 1000000,
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((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
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);
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#endif
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putc ('\n');
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return (0);
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@ -123,10 +123,22 @@ static int check_CPU (long clock, uint pvr, uint immr)
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else
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printf ("unknown M%s (0x%08x)", id_str, k);
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printf (" at %s MHz:", strmhz (buf, clock));
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printf (" %u kB I-Cache", checkicache () >> 10);
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printf (" %u kB D-Cache", checkdcache () >> 10);
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#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
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printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
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strmhz (buf, clock),
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CFG_866_CPUCLK_MIN / 1000000,
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((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CFG_866_CPUCLK_MAX / 1000000,
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((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
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);
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#else
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printf (" at %s MHz: ", strmhz (buf, clock));
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#endif
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printf ("%u kB I-Cache %u kB D-Cache",
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checkicache () >> 10,
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checkdcache () >> 10
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);
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/* do we have a FEC (860T/P or 852/859/866)? */
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@ -71,11 +71,11 @@
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static void serial_setdivisor(volatile cpm8xx_t *cp)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int divisor=gd->cpu_clk/16/gd->baudrate;
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int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
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if(divisor/16>0x1000) {
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/* bad divisor, assume 50Mhz clock and 9600 baud */
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divisor=(50*1000*1000)/16/9600;
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divisor=(50*1000*1000 + 8*9600)/16/9600;
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}
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#ifdef CFG_BRGCLK_PRESCALE
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@ -25,7 +25,7 @@
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#include <mpc8xx.h>
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#include <asm/processor.h>
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#ifndef CONFIG_TQM866M
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#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK)
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#define PITC_SHIFT 16
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#define PITR_SHIFT 16
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@ -170,6 +170,10 @@ unsigned long measure_gclk(void)
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#endif
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}
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#endif
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#if !defined(CONFIG_TQM866M)
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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* or (if it is not defined) measure_gclk() (which uses the ref clock)
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@ -230,6 +234,9 @@ int get_clocks_866 (void)
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cpuclk = CFG_866_CPUCLK_DEFAULT;
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gd->cpu_clk = init_pll_866 (cpuclk);
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#if defined(CFG_MEASURE_CPUCLK)
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gd->cpu_clk = measure_gclk ();
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#endif
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0)
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gd->bus_clk = gd->cpu_clk;
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@ -269,8 +276,19 @@ static long init_pll_866 (long clk)
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char mfi, mfn, mfd, s, pdf;
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long step_mfi, step_mfn;
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pdf = 0;
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if (clk < 80000000) {
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if (clk < 20000000) {
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clk *= 2;
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pdf = 1;
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} else {
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pdf = 0;
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}
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if (clk < 40000000) {
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s = 2;
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step_mfi = CFG_866_OSCCLK / 4;
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mfd = 7;
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step_mfn = CFG_866_OSCCLK / 30;
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} else if (clk < 80000000) {
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s = 1;
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step_mfi = CFG_866_OSCCLK / 2;
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mfd = 14;
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@ -294,13 +312,14 @@ static long init_pll_866 (long clk)
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/* Calculate effective clk
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*/
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n = (mfi * step_mfi) + (mfn * step_mfn);
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n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
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| PLPRCR_MFD_MSK | PLPRCR_S_MSK
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| PLPRCR_MFI_MSK | PLPRCR_DBRMO))
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| PLPRCR_MFI_MSK | PLPRCR_DBRMO
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| PLPRCR_PDF_MSK))
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| (mfn << PLPRCR_MFN_SHIFT)
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| (mfd << PLPRCR_MFD_SHIFT)
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| (s << PLPRCR_S_SHIFT)
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@ -12,6 +12,10 @@ If the "cpuclk" environment variable value is within the CPUCLK_MIN /
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CPUCLK_MAX limits, the specified value is used. Otherwise, the
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default CPU clock value is set.
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Please make sure you understand what you are doing, and understand
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the restrictions of your hardware (board, processor). For example,
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ethernet will stop working for CPU clock frequencies below 25 MHz.
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Please note that for now the new clock-handling code has been enabled
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for the TQM866M board only, even though it should be pretty much
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common for other MPC859 / MPC866 based boards also. Our intention
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@ -37,12 +37,19 @@
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#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
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#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
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#define CFG_866_CPUCLK_MIN 10000000 /* 10 MHz - CPU minimum clock */
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#define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
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#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
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#define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
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/* (it will be used if there is no */
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/* 'cpuclk' variable with valid value) */
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#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
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/* (function measure_gclk() */
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/* will be called) */
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#ifdef CFG_MEASURE_CPUCLK
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#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
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#endif
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
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