arm: A320: driver for FTMAC100 ethernet controller
This patch adds an FTMAC100 ethernet driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Po-Yu Chuang
Ben Warren
parent
eb1a4d0a47
commit
750326e5d5
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@ -39,6 +39,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o
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COBJS-$(CONFIG_ENC28J60) += enc28j60.o
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COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
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COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
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COBJS-$(CONFIG_FTMAC100) += ftmac100.o
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COBJS-$(CONFIG_GRETH) += greth.o
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COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
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COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
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@ -0,0 +1,278 @@
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/*
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* Faraday FTMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include "ftmac100.h"
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#define ETH_ZLEN 60
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struct ftmac100_data {
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volatile struct ftmac100_txdes txdes[1];
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volatile struct ftmac100_rxdes rxdes[PKTBUFSRX];
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int rx_index;
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};
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/*
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* Reset MAC
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*/
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static void ftmac100_reset (struct eth_device *dev)
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{
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struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
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debug ("%s()\n", __func__);
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writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
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while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
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;
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}
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/*
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* Set MAC address
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*/
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static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac)
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{
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struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
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unsigned int maddr = mac[0] << 8 | mac[1];
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
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debug ("%s(%x %x)\n", __func__, maddr, laddr);
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writel (maddr, &ftmac100->mac_madr);
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writel (laddr, &ftmac100->mac_ladr);
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}
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static void ftmac100_set_mac_from_env (struct eth_device *dev)
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{
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eth_getenv_enetaddr ("ethaddr", dev->enetaddr);
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ftmac100_set_mac (dev, dev->enetaddr);
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}
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/*
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* disable transmitter, receiver
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*/
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static void ftmac100_halt (struct eth_device *dev)
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{
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struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
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debug ("%s()\n", __func__);
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writel (0, &ftmac100->maccr);
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}
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static int ftmac100_init (struct eth_device *dev, bd_t *bd)
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{
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struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
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struct ftmac100_data *priv = dev->priv;
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volatile struct ftmac100_txdes *txdes = priv->txdes;
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volatile struct ftmac100_rxdes *rxdes = priv->rxdes;
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unsigned int maccr;
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int i;
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debug ("%s()\n", __func__);
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ftmac100_reset (dev);
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/* set the ethernet address */
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ftmac100_set_mac_from_env (dev);
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/* disable all interrupts */
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writel (0, &ftmac100->imr);
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/* initialize descriptors */
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priv->rx_index = 0;
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txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR;
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rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR;
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for (i = 0; i < PKTBUFSRX; i++) {
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/* RXBUF_BADR */
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rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i];
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rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
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rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
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}
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/* transmit ring */
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writel ((unsigned int)txdes, &ftmac100->txr_badr);
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/* receive ring */
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writel ((unsigned int)rxdes, &ftmac100->rxr_badr);
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/* poll receive descriptor automatically */
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writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc);
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/* enable transmitter, receiver */
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maccr = FTMAC100_MACCR_XMT_EN |
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FTMAC100_MACCR_RCV_EN |
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FTMAC100_MACCR_XDMA_EN |
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FTMAC100_MACCR_RDMA_EN |
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FTMAC100_MACCR_CRC_APD |
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FTMAC100_MACCR_ENRX_IN_HALFTX |
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FTMAC100_MACCR_RX_RUNT |
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FTMAC100_MACCR_RX_BROADPKT;
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writel (maccr, &ftmac100->maccr);
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return 0;
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}
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/*
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* Get a data block via Ethernet
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*/
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static int ftmac100_recv (struct eth_device *dev)
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{
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struct ftmac100_data *priv = dev->priv;
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volatile struct ftmac100_rxdes *curr_des;
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unsigned short rxlen;
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curr_des = &priv->rxdes[priv->rx_index];
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if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
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return -1;
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if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR |
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FTMAC100_RXDES0_CRC_ERR |
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FTMAC100_RXDES0_FTL |
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FTMAC100_RXDES0_RUNT |
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FTMAC100_RXDES0_RX_ODD_NB)) {
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return -1;
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}
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rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
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debug ("%s(): RX buffer %d, %x received\n",
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__func__, priv->rx_index, rxlen);
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/* pass the packet up to the protocol layers. */
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NetReceive ((void *)curr_des->rxdes2, rxlen);
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/* release buffer to DMA */
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curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN;
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priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
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return 0;
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}
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/*
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* Send a data block via Ethernet
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*/
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static int
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ftmac100_send (struct eth_device *dev, volatile void *packet, int length)
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{
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struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
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struct ftmac100_data *priv = dev->priv;
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volatile struct ftmac100_txdes *curr_des = priv->txdes;
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int tmo;
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if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
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debug ("%s(): no TX descriptor available\n", __func__);
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return -1;
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}
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debug ("%s(%x, %x)\n", __func__, (int)packet, length);
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length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
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/* initiate a transmit sequence */
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curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
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curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
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curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
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FTMAC100_TXDES1_LTS |
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FTMAC100_TXDES1_TXBUF_SIZE (length);
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curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN;
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/* start transmit */
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writel (1, &ftmac100->txpd);
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/* wait for transfer to succeed */
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tmo = get_timer (0) + 5 * CONFIG_SYS_HZ;
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while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
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if (get_timer (0) >= tmo) {
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debug ("%s(): timed out\n", __func__);
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return -1;
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}
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}
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debug ("%s(): packet sent\n", __func__);
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return 0;
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}
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int ftmac100_initialize (bd_t *bd)
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{
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struct eth_device *dev;
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struct ftmac100_data *priv;
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dev = malloc (sizeof *dev);
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if (!dev) {
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printf ("%s(): failed to allocate dev\n", __func__);
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goto out;
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}
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/* Transmit and receive descriptors should align to 16 bytes */
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priv = memalign (16, sizeof (struct ftmac100_data));
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if (!priv) {
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printf ("%s(): failed to allocate priv\n", __func__);
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goto free_dev;
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}
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memset (dev, 0, sizeof (*dev));
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memset (priv, 0, sizeof (*priv));
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sprintf (dev->name, "FTMAC100");
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dev->iobase = CONFIG_FTMAC100_BASE;
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dev->init = ftmac100_init;
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dev->halt = ftmac100_halt;
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dev->send = ftmac100_send;
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dev->recv = ftmac100_recv;
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dev->priv = priv;
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eth_register (dev);
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return 1;
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free_dev:
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free (dev);
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out:
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return 0;
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}
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@ -0,0 +1,154 @@
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/*
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* Faraday FTMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FTMAC100_H
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#define __FTMAC100_H
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struct ftmac100 {
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unsigned int isr; /* 0x00 */
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unsigned int imr; /* 0x04 */
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unsigned int mac_madr; /* 0x08 */
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unsigned int mac_ladr; /* 0x0c */
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unsigned int maht0; /* 0x10 */
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unsigned int maht1; /* 0x14 */
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unsigned int txpd; /* 0x18 */
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unsigned int rxpd; /* 0x1c */
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unsigned int txr_badr; /* 0x20 */
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unsigned int rxr_badr; /* 0x24 */
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unsigned int itc; /* 0x28 */
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unsigned int aptc; /* 0x2c */
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unsigned int dblac; /* 0x30 */
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unsigned int pad1[3]; /* 0x34 - 0x3c */
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unsigned int pad2[16]; /* 0x40 - 0x7c */
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unsigned int pad3[2]; /* 0x80 - 0x84 */
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unsigned int maccr; /* 0x88 */
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unsigned int macsr; /* 0x8c */
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unsigned int phycr; /* 0x90 */
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unsigned int phywdata; /* 0x94 */
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unsigned int fcr; /* 0x98 */
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unsigned int bpr; /* 0x9c */
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unsigned int pad4[8]; /* 0xa0 - 0xbc */
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unsigned int pad5; /* 0xc0 */
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unsigned int ts; /* 0xc4 */
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unsigned int dmafifos; /* 0xc8 */
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unsigned int tm; /* 0xcc */
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unsigned int pad6; /* 0xd0 */
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unsigned int tx_mcol_scol; /* 0xd4 */
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unsigned int rpf_aep; /* 0xd8 */
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unsigned int xm_pg; /* 0xdc */
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unsigned int runt_tlcc; /* 0xe0 */
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unsigned int crcer_ftl; /* 0xe4 */
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unsigned int rlc_rcc; /* 0xe8 */
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unsigned int broc; /* 0xec */
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unsigned int mulca; /* 0xf0 */
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unsigned int rp; /* 0xf4 */
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unsigned int xp; /* 0xf8 */
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};
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/*
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* Interrupt status register & interrupt mask register
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*/
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#define FTMAC100_INT_RPKT_FINISH (1 << 0)
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#define FTMAC100_INT_NORXBUF (1 << 1)
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#define FTMAC100_INT_XPKT_FINISH (1 << 2)
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#define FTMAC100_INT_NOTXBUF (1 << 3)
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#define FTMAC100_INT_XPKT_OK (1 << 4)
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#define FTMAC100_INT_XPKT_LOST (1 << 5)
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#define FTMAC100_INT_RPKT_SAV (1 << 6)
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#define FTMAC100_INT_RPKT_LOST (1 << 7)
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#define FTMAC100_INT_AHB_ERR (1 << 8)
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#define FTMAC100_INT_PHYSTS_CHG (1 << 9)
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/*
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* Automatic polling timer control register
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*/
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#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
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#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
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#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
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#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
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/*
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* MAC control register
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*/
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#define FTMAC100_MACCR_XDMA_EN (1 << 0)
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#define FTMAC100_MACCR_RDMA_EN (1 << 1)
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#define FTMAC100_MACCR_SW_RST (1 << 2)
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#define FTMAC100_MACCR_LOOP_EN (1 << 3)
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#define FTMAC100_MACCR_CRC_DIS (1 << 4)
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#define FTMAC100_MACCR_XMT_EN (1 << 5)
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#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6)
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#define FTMAC100_MACCR_RCV_EN (1 << 8)
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#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9)
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#define FTMAC100_MACCR_RX_RUNT (1 << 10)
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#define FTMAC100_MACCR_RX_FTL (1 << 11)
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#define FTMAC100_MACCR_RCV_ALL (1 << 12)
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#define FTMAC100_MACCR_CRC_APD (1 << 14)
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#define FTMAC100_MACCR_FULLDUP (1 << 15)
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#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16)
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#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
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/*
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* Transmit descriptor, aligned to 16 bytes
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*/
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struct ftmac100_txdes {
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unsigned int txdes0;
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unsigned int txdes1;
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unsigned int txdes2; /* TXBUF_BADR */
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unsigned int txdes3; /* not used by HW */
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} __attribute__ ((aligned(16)));
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#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0)
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#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1)
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#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31)
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#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff)
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#define FTMAC100_TXDES1_LTS (1 << 27)
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#define FTMAC100_TXDES1_FTS (1 << 28)
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#define FTMAC100_TXDES1_TX2FIC (1 << 29)
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#define FTMAC100_TXDES1_TXIC (1 << 30)
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#define FTMAC100_TXDES1_EDOTR (1 << 31)
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/*
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* Receive descriptor, aligned to 16 bytes
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*/
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struct ftmac100_rxdes {
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unsigned int rxdes0;
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unsigned int rxdes1;
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unsigned int rxdes2; /* RXBUF_BADR */
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unsigned int rxdes3; /* not used by HW */
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} __attribute__ ((aligned(16)));
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#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff)
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#define FTMAC100_RXDES0_MULTICAST (1 << 16)
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#define FTMAC100_RXDES0_BROADCAST (1 << 17)
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#define FTMAC100_RXDES0_RX_ERR (1 << 18)
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#define FTMAC100_RXDES0_CRC_ERR (1 << 19)
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#define FTMAC100_RXDES0_FTL (1 << 20)
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#define FTMAC100_RXDES0_RUNT (1 << 21)
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#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22)
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#define FTMAC100_RXDES0_LRS (1 << 28)
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#define FTMAC100_RXDES0_FRS (1 << 29)
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#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31)
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#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff)
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#define FTMAC100_RXDES1_EDORR (1 << 31)
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#endif /* __FTMAC100_H */
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@ -51,6 +51,7 @@ int eepro100_initialize(bd_t *bis);
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int eth_3com_initialize (bd_t * bis);
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||||
int fec_initialize (bd_t *bis);
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||||
int fecmxc_initialize (bd_t *bis);
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||||
int ftmac100_initialize(bd_t *bits);
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||||
int greth_initialize(bd_t *bis);
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||||
void gt6426x_eth_initialize(bd_t *bis);
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int inca_switch_initialize(bd_t *bis);
|
||||
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Loading…
Reference in New Issue