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Convert SMC911X Ethernet driver to CONFIG_NET_MULTI API

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All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
 - changed CONFIG_DRIVER_SMC911X* to CONFIG_SMC911X*
 - cleaned up line lengths
 - modified all boards that override weak function in this driver
 - added

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
master
Ben Warren 14 years ago
parent 3bd0a877b7
commit 736fead8fd
23 changed files with 335 additions and 195 deletions
Show Stats Download Patch File Download Diff File

8
board/bf548-ezkit/bf548-ezkit.c
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@ -7,6 +7,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
@ -77,3 +78,10 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif

10
board/cm-bf548/cm-bf548.c
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@ -9,6 +9,7 @@
#include <common.h>
#include <config.h>
#include <command.h>
#include <netdev.h>
#include <asm/blackfin.h>
DECLARE_GLOBAL_DATA_PTR;
@ -77,3 +78,12 @@ int board_early_init_f(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

10
board/freescale/mx31pdk/mx31pdk.c
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@ -25,6 +25,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
@ -61,3 +62,12 @@ int checkboard(void)
printf("Board: i.MX31 MAX PDK (3DS)\n");
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

10
board/imx31_litekit/imx31_litekit.c
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@ -23,6 +23,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
@ -75,3 +76,12 @@ int checkboard (void)
printf("Board: i.MX31 Litekit\n");
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

10
board/imx31_phycore/imx31_phycore.c
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@ -24,6 +24,7 @@
#include <common.h>
#include <s6e63d6.h>
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
@ -128,3 +129,12 @@ int checkboard (void)
printf("Board: Phytec phyCore i.MX31\n");
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

22
board/micronas/vct/ebi_smc911x.c
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@ -18,6 +18,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include "vct.h"
@ -45,10 +46,11 @@ int ebi_init_smc911x(void)
* Accessor functions replacing the "weak" functions in
* drivers/net/smc911x.c
*/
u32 smc911x_reg_read(u32 addr)
u32 smc911x_reg_read(struct eth_device *dev, u32 addr)
{
volatile u32 data;
addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
ebi_wait();
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
@ -58,8 +60,9 @@ u32 smc911x_reg_read(u32 addr)
return (data);
}
void smc911x_reg_write(u32 addr, u32 data)
void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data)
{
addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
ebi_wait();
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
@ -68,8 +71,9 @@ void smc911x_reg_write(u32 addr, u32 data)
ebi_wait();
}
void pkt_data_push(u32 addr, u32 data)
void pkt_data_push(struct eth_device *dev, u32 addr, u32 data)
{
addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
ebi_wait();
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
@ -80,10 +84,11 @@ void pkt_data_push(u32 addr, u32 data)
return;
}
u32 pkt_data_pull(u32 addr)
u32 pkt_data_pull(struct eth_device *dev, u32 addr)
{
volatile u32 data;
addr += dev->iobase;
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
ebi_wait();
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
@ -92,3 +97,12 @@ u32 pkt_data_pull(u32 addr)
return data;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE);
#endif
return rc;
}

10
board/micronas/vct/vct.c
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@ -21,6 +21,7 @@
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include "vct.h"
@ -115,3 +116,12 @@ int checkboard(void)
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

10
board/omap3/evm/evm.c
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@ -28,6 +28,7 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
@ -122,3 +123,12 @@ static void setup_net_chip(void)
udelay(1);
writel(GPIO0, &gpio3_base->setdataout);
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

10
board/renesas/ap325rxa/ap325rxa.c
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@ -19,6 +19,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@ -160,3 +161,12 @@ void ide_set_reset(int idereset)
udelay(FPGA_NAND_RST_WAIT);
outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

17
board/renesas/rsk7203/rsk7203.c
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@ -21,6 +21,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@ -57,15 +58,25 @@ void led_set_state(unsigned short value)
* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
* functions necessary to solve this problem.
*/
u32 pkt_data_pull(u32 addr)
u32 pkt_data_pull(struct eth_device *dev, u32 addr)
{
volatile u16 *addr_16 = (u16 *)addr;
volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
| swab16(*(addr_16 + 1));
}
void pkt_data_push(u32 addr, u32 val)
void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
{
addr += dev->iobase;
*(volatile u16 *)(addr + 2) = swab16((u16)val);
*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

2
drivers/net/Makefile
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@ -63,7 +63,7 @@ COBJS-$(CONFIG_RTL8169) += rtl8169.o
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o
COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o

177
drivers/net/smc911x.c
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@ -24,110 +24,90 @@
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "smc911x.h"
u32 pkt_data_pull(u32 addr) \
u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
__attribute__ ((weak, alias ("smc911x_reg_read")));
void pkt_data_push(u32 addr, u32 val) \
void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
__attribute__ ((weak, alias ("smc911x_reg_write")));
#define mdelay(n) udelay((n)*1000)
static int smx911x_handle_mac_address(bd_t *bd)
static void smx911x_handle_mac_address(struct eth_device *dev)
{
unsigned long addrh, addrl;
uchar m[6];
if (eth_getenv_enetaddr("ethaddr", m)) {
/* if the environment has a valid mac address then use it */
addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
addrh = m[4] | (m[5] << 8);
smc911x_set_mac_csr(ADDRL, addrl);
smc911x_set_mac_csr(ADDRH, addrh);
} else {
/* if not, try to get one from the eeprom */
addrh = smc911x_get_mac_csr(ADDRH);
addrl = smc911x_get_mac_csr(ADDRL);
m[0] = (addrl ) & 0xff;
m[1] = (addrl >> 8 ) & 0xff;
m[2] = (addrl >> 16 ) & 0xff;
m[3] = (addrl >> 24 ) & 0xff;
m[4] = (addrh ) & 0xff;
m[5] = (addrh >> 8 ) & 0xff;
/* we get 0xff when there is no eeprom connected */
if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
printf(DRIVERNAME ": no valid mac address in environment "
"and no eeprom found\n");
return -1;
}
eth_setenv_enetaddr("ethaddr", m);
}
uchar *m = dev->enetaddr;
printf(DRIVERNAME ": MAC %pM\n", m);
addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
addrh = m[4] | (m[5] << 8);
smc911x_set_mac_csr(dev, ADDRL, addrl);
smc911x_set_mac_csr(dev, ADDRH, addrh);
return 0;
printf(DRIVERNAME ": MAC %pM\n", m);
}
static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
static int smc911x_miiphy_read(struct eth_device *dev,
u8 phy, u8 reg, u16 *val)
{
while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 |
MII_ACC_MII_BUSY);
while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
*val = smc911x_get_mac_csr(MII_DATA);
*val = smc911x_get_mac_csr(dev, MII_DATA);
return 0;
}
static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val)
static int smc911x_miiphy_write(struct eth_device *dev,
u8 phy, u8 reg, u16 val)
{
while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
smc911x_set_mac_csr(MII_DATA, val);
smc911x_set_mac_csr(MII_ACC,
smc911x_set_mac_csr(dev, MII_DATA, val);
smc911x_set_mac_csr(dev, MII_ACC,
phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
return 0;
}
static int smc911x_phy_reset(void)
static int smc911x_phy_reset(struct eth_device *dev)
{
u32 reg;
reg = smc911x_reg_read(PMT_CTRL);
reg = smc911x_reg_read(dev, PMT_CTRL);
reg &= ~0xfffff030;
reg |= PMT_CTRL_PHY_RST;
smc911x_reg_write(PMT_CTRL, reg);
smc911x_reg_write(dev, PMT_CTRL, reg);
mdelay(100);
return 0;
}
static void smc911x_phy_configure(void)
static void smc911x_phy_configure(struct eth_device *dev)
{
int timeout;
u16 status;
smc911x_phy_reset();
smc911x_phy_reset(dev);
smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_RESET);
mdelay(1);
smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
smc911x_miiphy_write(dev, 1, PHY_ANAR, 0x01e1);
smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_AUTON |
PHY_BMCR_RST_NEG);
timeout = 5000;
do {
@ -135,7 +115,7 @@ static void smc911x_phy_configure(void)
if ((timeout--) == 0)
goto err_out;
if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
if (smc911x_miiphy_read(dev, 1, PHY_BMSR, &status) != 0)
goto err_out;
} while (!(status & PHY_BMSR_LS));
@ -147,39 +127,39 @@ err_out:
printf(DRIVERNAME ": autonegotiation timed out\n");
}
static void smc911x_enable(void)
static void smc911x_enable(struct eth_device *dev)
{
/* Enable TX */
smc911x_reg_write(HW_CFG, 8 << 16 | HW_CFG_SF);
smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
smc911x_reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000);
smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
smc911x_reg_write(TX_CFG, TX_CFG_TX_ON);
smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
/* no padding to start of packets */
smc911x_reg_write(RX_CFG, 0);
smc911x_reg_write(dev, RX_CFG, 0);
smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
MAC_CR_HBDIS);
}
int eth_init(bd_t *bd)
static int smc911x_init(struct eth_device *dev, bd_t * bd)
{
printf(DRIVERNAME ": initializing\n");
if (smc911x_detect_chip())
if (smc911x_detect_chip(dev))
goto err_out;
smc911x_reset();
smc911x_reset(dev);
/* Configure the PHY, initialize the link state */
smc911x_phy_configure();
smc911x_phy_configure(dev);
if (smx911x_handle_mac_address(bd))
goto err_out;
smx911x_handle_mac_address(dev);
/* Turn on Tx + Rx */
smc911x_enable();
smc911x_enable(dev);
return 0;
@ -187,28 +167,32 @@ err_out:
return -1;
}
int eth_send(volatile void *packet, int length)
static int smc911x_send(struct eth_device *dev,
volatile void *packet, int length)
{
u32 *data = (u32*)packet;
u32 tmplen;
u32 status;
smc911x_reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
smc911x_reg_write(TX_DATA_FIFO, length);
smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
TX_CMD_A_INT_LAST_SEG | length);
smc911x_reg_write(dev, TX_DATA_FIFO, length);
tmplen = (length + 3) / 4;
while (tmplen--)
pkt_data_push(TX_DATA_FIFO, *data++);
pkt_data_push(dev, TX_DATA_FIFO, *data++);
/* wait for transmission */
while (!((smc911x_reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
TX_FIFO_INF_TSUSED) >> 16));
/* get status. Ignore 'no carrier' error, it has no meaning for
* full duplex operation
*/
status = smc911x_reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL |
TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
status = smc911x_reg_read(dev, TX_STATUS_FIFO) &
(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
if (!status)
return 0;
@ -223,26 +207,26 @@ int eth_send(volatile void *packet, int length)
return -1;
}
void eth_halt(void)
static void smc911x_halt(struct eth_device *dev)
{
smc911x_reset();
smc911x_reset(dev);
}
int eth_rx(void)
static int smc911x_rx(struct eth_device *dev)
{
u32 *data = (u32 *)NetRxPackets[0];
u32 pktlen, tmplen;
u32 status;
if ((smc911x_reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
status = smc911x_reg_read(RX_STATUS_FIFO);
if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
status = smc911x_reg_read(dev, RX_STATUS_FIFO);
pktlen = (status & RX_STS_PKT_LEN) >> 16;
smc911x_reg_write(RX_CFG, 0);
smc911x_reg_write(dev, RX_CFG, 0);
tmplen = (pktlen + 2+ 3) / 4;
while (tmplen--)
*data++ = pkt_data_pull(RX_DATA_FIFO);
*data++ = pkt_data_pull(dev, RX_DATA_FIFO);
if (status & RX_STS_ES)
printf(DRIVERNAME
@ -254,3 +238,36 @@ int eth_rx(void)
return 0;
}
int smc911x_initialize(u8 dev_num, int base_addr)
{
unsigned long addrl, addrh;
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (!dev) {
free(dev);
return 0;
}
memset(dev, 0, sizeof(*dev));
dev->iobase = base_addr;
addrh = smc911x_get_mac_csr(dev, ADDRH);
addrl = smc911x_get_mac_csr(dev, ADDRL);
dev->enetaddr[0] = addrl;
dev->enetaddr[1] = addrl >> 8;
dev->enetaddr[2] = addrl >> 16;
dev->enetaddr[3] = addrl >> 24;
dev->enetaddr[4] = addrh;
dev->enetaddr[5] = addrh >> 8;
dev->init = smc911x_init;
dev->halt = smc911x_halt;
dev->send = smc911x_send;
dev->recv = smc911x_rx;
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
eth_register(dev);
return 0;
}

168
drivers/net/smc911x.h
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@ -27,45 +27,51 @@
#include <linux/types.h>
#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
defined (CONFIG_DRIVER_SMC911X_16_BIT)
#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
CONFIG_DRIVER_SMC911X_16_BIT shall be set"
#define DRIVERNAME "smc911x"
#if defined (CONFIG_SMC911X_32_BIT) && \
defined (CONFIG_SMC911X_16_BIT)
#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
CONFIG_SMC911X_16_BIT shall be set"
#endif
#if defined (CONFIG_DRIVER_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(u32 addr)
#if defined (CONFIG_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
return *(volatile u32*)addr;
return *(volatile u32*)(dev->iobase + offset);
}
u32 smc911x_reg_read(u32 addr) __attribute__((weak, alias("__smc911x_reg_read")));
u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
__attribute__((weak, alias("__smc911x_reg_read")));
static inline void __smc911x_reg_write(u32 addr, u32 val)
static inline void __smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
*(volatile u32*)addr = val;
*(volatile u32*)(dev->iobase + offset) = val;
}
void smc911x_reg_write(u32 addr, u32 val) __attribute__((weak, alias("__smc911x_reg_write")));
#elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(u32 addr)
void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
__attribute__((weak, alias("__smc911x_reg_write")));
#elif defined (CONFIG_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
volatile u16 *addr_16 = (u16 *)addr;
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
}
static inline void smc911x_reg_write(u32 addr, u32 val)
static inline void smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
*(volatile u16*)addr = (u16)val;
*(volatile u16*)(addr + 2) = (u16)(val >> 16);
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
}
#else
#error "SMC911X: undefined bus width"
#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
#endif /* CONFIG_SMC911X_16_BIT */
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00)
#define RX_DATA_FIFO 0x00
#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20)
#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
@ -80,7 +86,7 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define TX_CMD_B_DISABLE_PADDING 0x00001000
#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40)
#define RX_STATUS_FIFO 0x40
#define RX_STS_PKT_LEN 0x3FFF0000
#define RX_STS_ES 0x00008000
#define RX_STS_BCST 0x00002000
@ -94,8 +100,8 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define RX_STS_MII_ERR 0x00000008
#define RX_STS_DRIBBLING 0x00000004
#define RX_STS_CRC_ERR 0x00000002
#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44)
#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48)
#define RX_STATUS_FIFO_PEEK 0x44
#define TX_STATUS_FIFO 0x48
#define TX_STS_TAG 0xFFFF0000
#define TX_STS_ES 0x00008000
#define TX_STS_LOC 0x00000800
@ -106,21 +112,23 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define TX_STS_MANY_DEFER 0x00000004
#define TX_STS_UNDERRUN 0x00000002
#define TX_STS_DEFERRED 0x00000001
#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C)
#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50)
#define TX_STATUS_FIFO_PEEK 0x4C
#define ID_REV 0x50
#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
#define ID_REV_REV_ID 0x0000FFFF /* RO */
#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54)
#define INT_CFG 0x54
#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
#define INT_CFG_INT_DEAS_CLR 0x00004000
#define INT_CFG_INT_DEAS_STS 0x00002000
#define INT_CFG_IRQ_INT 0x00001000 /* RO */
#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_POL 0x00000010
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_TYPE 0x00000001
#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58)
#define INT_STS 0x58
#define INT_STS_SW_INT 0x80000000 /* R/WC */
#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
@ -149,7 +157,7 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C)
#define INT_EN 0x5C
#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
@ -179,14 +187,14 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64)
#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68)
#define BYTE_TEST 0x64
#define FIFO_INT 0x68
#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C)
#define RX_CFG 0x6C
#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
@ -196,16 +204,17 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70)
#define TX_CFG 0x70
/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */
/* R/W Self Clearing */
/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
#define TX_CFG_TXSAO 0x00000004 /* R/W */
#define TX_CFG_TX_ON 0x00000002 /* R/W */
#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74)
#define HW_CFG 0x74
#define HW_CFG_TTM 0x00200000 /* R/W */
#define HW_CFG_SF 0x00100000 /* R/W */
#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
@ -221,24 +230,25 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define HW_CFG_SRST_TO 0x00000002 /* RO */
#define HW_CFG_SRST 0x00000001 /* Self Clearing */
#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78)
#define RX_DP_CTRL 0x78
#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C)
#define RX_FIFO_INF 0x7C
#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80)
#define TX_FIFO_INF 0x80
#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84)
#define PMT_CTRL 0x84
#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_TYPE 0x00000040
#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
@ -246,10 +256,11 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_EN 0x00000002
#define PMT_CTRL_READY 0x00000001 /* RO */
#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88)
#define GPIO_CFG 0x88
#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
@ -269,23 +280,23 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C)
#define GPT_CFG 0x8C
#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90)
#define GPT_CNT 0x90
#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98)
#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C)
#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0)
#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4)
#define ENDIAN 0x98
#define FREE_RUN 0x9C
#define RX_DROP 0xA0
#define MAC_CSR_CMD 0xA4
#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8)
#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC)
#define MAC_CSR_DATA 0xA8
#define AFC_CFG 0xAC
#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
@ -294,7 +305,7 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define AFC_CFG_FCADD 0x00000002 /* R/W */
#define AFC_CFG_FCANY 0x00000001 /* R/W */
#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0)
#define E2P_CMD 0xB0
#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
@ -309,7 +320,7 @@ static inline void smc911x_reg_write(u32 addr, u32 val)
#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4)
#define E2P_DATA 0xB4
#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
/* end of LAN register offsets and bit definitions */
@ -403,41 +414,39 @@ static const struct chip_id chip_ids[] = {
{ 0, NULL },
};
#define DRIVERNAME "smc911x"
static u32 smc911x_get_mac_csr(u8 reg)
static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
{
while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
smc911x_reg_write(dev, MAC_CSR_CMD,
MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
return smc911x_reg_read(MAC_CSR_DATA);
return smc911x_reg_read(dev, MAC_CSR_DATA);
}
static void smc911x_set_mac_csr(u8 reg, u32 data)
static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
{
while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
smc911x_reg_write(MAC_CSR_DATA, data);
smc911x_reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
while (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
smc911x_reg_write(dev, MAC_CSR_DATA, data);
smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
}
static int smc911x_detect_chip(void)
static int smc911x_detect_chip(struct eth_device *dev)
{
unsigned long val, i;
val = smc911x_reg_read(BYTE_TEST);
val = smc911x_reg_read(dev, BYTE_TEST);
if (val != 0x87654321) {
printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
return -1;
}
val = smc911x_reg_read(ID_REV) >> 16;
val = smc911x_reg_read(dev, ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == val) break;
}
@ -451,18 +460,19 @@ static int smc911x_detect_chip(void)
return 0;
}
static void smc911x_reset(void)
static void smc911x_reset(struct eth_device *dev)
{
int timeout;
/* Take out of PM setting first */
if (smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY) {
if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(BYTE_TEST, 0x0);
smc911x_reg_write(dev, BYTE_TEST, 0x0);
timeout = 10;
while (timeout-- && !(smc911x_reg_read(PMT_CTRL) & PMT_CTRL_READY))
while (timeout-- &&
!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
udelay(10);
if (!timeout) {
printf(DRIVERNAME
@ -472,12 +482,12 @@ static void smc911x_reset(void)
}
/* Disable interrupts */
smc911x_reg_write(INT_EN, 0);
smc911x_reg_write(dev, INT_EN, 0);
smc911x_reg_write(HW_CFG, HW_CFG_SRST);
smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
timeout = 1000;
while (timeout-- && smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
udelay(10);
if (!timeout) {
@ -486,11 +496,11 @@ static void smc911x_reset(void)
}
/* Reset the FIFO level and flow control settings */
smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
smc911x_reg_write(AFC_CFG, 0x0050287F);
smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
/* Set to LED outputs */
smc911x_reg_write(GPIO_CFG, 0x70070000);
smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
}
#endif

7
include/configs/ap325rxa.h
Unescape View File

@ -53,9 +53,10 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_32_BIT 1
#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT 1
#define CONFIG_SMC911X_BASE 0xB6080000
/* MEMORY */
#define AP325RXA_SDRAM_BASE (0x88000000)

7
include/configs/bf548-ezkit.h
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@ -69,9 +69,10 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
#define CONFIG_DRIVER_SMC911X_16_BIT
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME bf548-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */

7
include/configs/cm-bf548.h
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@ -69,9 +69,10 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_BASE 0x24000000
#define CONFIG_DRIVER_SMC911X_16_BIT
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf548
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */

7
include/configs/imx31_litekit.h
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@ -104,9 +104,10 @@
"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_BASE (CS4_BASE + 0x00020000)
#define CONFIG_DRIVER_SMC911X_32_BIT 1
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options

7
include/configs/imx31_phycore.h
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@ -106,9 +106,10 @@
"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
#define CONFIG_DRIVER_SMC911X_32_BIT 1
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0xa8000000
#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options

7
include/configs/mx31pdk.h
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@ -106,9 +106,10 @@
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0"
#define CONFIG_DRIVER_SMC911X 1
#define CONFIG_DRIVER_SMC911X_BASE 0xB6000000
#define CONFIG_DRIVER_SMC911X_32_BIT 1
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0xB6000000
#define CONFIG_SMC911X_32_BIT 1
/*
* Miscellaneous configurable options

7
include/configs/omap3_evm.h
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@ -302,9 +302,10 @@ extern unsigned int boot_flash_type;
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_SMC911X
#define CONFIG_DRIVER_SMC911X_32_BIT
#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */

7
include/configs/rsk7203.h
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@ -105,8 +105,9 @@
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Network interface */
#define CONFIG_DRIVER_SMC911X
#define CONFIG_DRIVER_SMC911X_16_BIT
#define CONFIG_DRIVER_SMC911X_BASE (0x24000000)
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE (0x24000000)
#endif /* __RSK7203_H */

9
include/configs/vct.h
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@ -89,10 +89,11 @@
/*
* SMSC91C11x Network Card
*/
#define CONFIG_DRIVER_SMC911X
#define CONFIG_DRIVER_SMC911X_BASE 0x00000000
#define CONFIG_DRIVER_SMC911X_32_BIT
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0x00000000
#define CONFIG_SMC911X_32_BIT
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_NET_MULTI
#endif
/*
@ -342,7 +343,7 @@ int vct_gpio_get(int pin);
#undef CONFIG_CMD_TERMINAL
#undef CONFIG_CMD_USB
#undef CONFIG_DRIVER_SMC911X
#undef CONFIG_SMC911X
#undef CONFIG_SOFT_I2C
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP

1
include/netdev.h
Unescape View File

@ -71,6 +71,7 @@ int rtl8139_initialize(bd_t *bis);
int rtl8169_initialize(bd_t *bis);
int scc_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc911x_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
int uec_standard_init(bd_t *bis);

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