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CPCI4052 update (support for revision 3).

This commit is contained in:
stroese 2003-03-20 15:31:19 +00:00
parent 97a43d641d
commit 6f4474e87b
4 changed files with 895 additions and 823 deletions
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115
board/esd/cpci405/cpci405.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2001
* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -50,7 +50,7 @@ const unsigned char fpgadata[] =
/* Prototypes */
int version2(void);
int cpci405_version(void);
int gunzip(void *, int, unsigned char *, int *);
@ -83,7 +83,7 @@ int board_pre_init (void)
* Boot onboard FPGA
*/
#ifndef CONFIG_CPCI405_VER2
if (!version2()) {
if (cpci405_version() == 1) {
status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
if (status != 0) {
/* booting FPGA failed */
@ -144,7 +144,11 @@ int board_pre_init (void)
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
@ -178,29 +182,43 @@ int cpci405_host(void)
}
int version2(void)
int cpci405_version(void)
{
unsigned long cntrl0Reg;
unsigned long value;
/*
* Setup GPIO pins (CS2/GPIO11 as GPIO)
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x02000000);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out32(IBM405GP_GPIO0_ODR, in32(IBM405GP_GPIO0_ODR) & ~0x00180000);
out32(IBM405GP_GPIO0_TCR, in32(IBM405GP_GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in32(IBM405GP_GPIO0_IR) & 0x00100000; /* test GPIO11 */
value = in32(IBM405GP_GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Setup GPIO pins (CS2/GPIO11 as CS again)
* Restore GPIO settings
*/
mtdcr(cntrl0, cntrl0Reg);
if (value)
return 0; /* no, board is version 1.x */
else
return -1; /* yes, board is version 2.x */
switch (value) {
case 0x00180000:
/* CS2==1 && CS3==1 -> version 1 */
return 1;
case 0x00080000:
/* CS2==0 && CS3==1 -> version 2 */
return 2;
case 0x00100000:
/* CS2==1 && CS3==0 -> version 3 */
return 3;
case 0x00000000:
/* CS2==0 && CS3==0 -> version 4 */
return 4;
default:
/* should not be reached! */
return 2;
}
}
@ -230,7 +248,7 @@ int misc_init_r (void)
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (version2()) {
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
@ -291,11 +309,41 @@ int misc_init_r (void)
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
/*
* Enable outputs in fpga on version 3 board
*/
*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
/*
* Set outputs to 0
*/
*leds = 0x00;
/*
* Reset external DUART
*/
*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
}
else {
printf("\n*** U-Boot Version does not match Board Version!\n");
printf("*** CPCI-405 Version 2.x detected!\n");
printf("*** Please use correct U-Boot version (CPCI4052)!\n\n");
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
}
#else /* CONFIG_CPCI405_VER2 */
@ -321,10 +369,10 @@ int misc_init_r (void)
}
}
if (version2()) {
printf("\n*** U-Boot Version does not match Board Version!\n");
printf("*** CPCI-405 Board Version 1.x detected!\n");
printf("*** Please use correct U-Boot version (CPCI405)!\n\n");
if (cpci405_version() >= 2) {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Board Version 2.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
}
#endif /* CONFIG_CPCI405_VER2 */
@ -350,6 +398,7 @@ int checkboard (void)
#endif
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned short ver;
puts ("Board: ");
@ -359,17 +408,19 @@ int checkboard (void)
puts(str);
}
if (version2())
puts (" (Ver 2.x, ");
else
puts (" (Ver 1.x, ");
ver = cpci405_version();
printf(" (Ver %d.x, ", ver);
#if 0
if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS)
& CFG_FPGA_STATUS_FLASH)
puts ("FLASH Bank A, ");
else
puts ("FLASH Bank B, ");
#if 0 /* test-only */
if (ver >= 2) {
volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
puts ("FLASH Bank B, ");
} else {
puts ("FLASH Bank A, ");
}
}
#endif
if (ctermm2()) {

86
board/esd/cpci405/flash.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2001
* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -39,13 +39,31 @@ static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long calc_size(unsigned long size)
{
switch (size) {
case 1 << 20:
return 0;
case 2 << 20:
return 1;
case 4 << 20:
return 2;
case 8 << 20:
return 3;
case 16 << 20:
return 4;
default:
return 0;
}
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
int size_val = 0;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
@ -68,61 +86,37 @@ unsigned long flash_init (void)
/* Re-do sizing to get full correct info */
if (size_b1) {
base_b1 = -size_b1;
if (size_b1 < (1 << 20)) {
/* minimum CS size on PPC405GP is 1MB !!! */
size_b1 = 1 << 20;
}
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
base_b1 = -size_b1;
switch (size_b1) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
default:
size_val = 0;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
#if 0 /* test-only */
printf("size_b1=%x base_b1=%x pb1cr = %x\n",
size_b1, base_b1, pbcr); /* test-only */
#endif
}
if (size_b0) {
base_b0 = base_b1 - size_b0;
if (size_b0 < (1 << 20)) {
/* minimum CS size on PPC405GP is 1MB !!! */
size_b0 = 1 << 20;
}
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
switch (size_b1) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
#if 0 /* test-only */
printf("size_b0=%x base_b0=%x pb0cr = %x\n",
size_b0, base_b0, pbcr); /* test-only */
#endif
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

1503
board/esd/cpci405/fpgadata_cpci4052.c
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File diff suppressed because it is too large Load Diff

14
include/configs/CPCI4052.h
View File

@ -296,13 +296,15 @@
/* Memory Bank 2 (CAN0, 1) initialization */
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CFG_LED_ADDR 0xF0000380
/* Memory Bank 3 (CompactFlash IDE) initialization */
#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (NVRAM/RTC) initialization */
#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
//#define CFG_EBC_PB4AP 0x01805280 /* TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 5 (optional Quart) initialization */
@ -332,10 +334,12 @@
#define CFG_FPGA_TS_CAP3_LOW 0x1e
/* FPGA Mode Reg */
#define CFG_FPGA_MODE_CF_RESET 0x0001
#define CFG_FPGA_MODE_CF_RESET 0x0001
#define CFG_FPGA_MODE_DUART_RESET 0x0002
#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
#define CFG_FPGA_MODE_TS_CLEAR 0x2000
#define CFG_FPGA_MODE_TS_CLEAR 0x2000
/* FPGA Status Reg */
#define CFG_FPGA_STATUS_DIP0 0x0001
@ -357,13 +361,9 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
#if 1 /* test-only */
#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
#else
#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
#endif
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)