Merge branch 'master' of /home/wd/git/u-boot/custodians

2007-12-27 01:13:05 +01:00 · 2007-12-27 01:13:05 +01:00 · 6e1bbe6e3e
parent 58bbc77eb0 81b38be863
commit 6e1bbe6e3e
55 changed files with 5766 additions and 6 deletions
--- a/11
+++ b/11
@ -117,7 +117,7 @@ N: Arun Dharankar
 E: ADharankar@ATTBI.Com
 D: threads / scheduler example code

-N: Kári Davíðsson
+N: K?ri Dav??sson
 E: kd@flaga.is
 D: FLAGA DM Support

@ -143,7 +143,7 @@ E: info@elste.org
 D: Port for the ModNET50 Board, NET+50 CPU Port
 W: http://www.imms.de

-N: Daniel Engström
+N: Daniel Engstr?m
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board

@ -334,7 +334,7 @@ N: Frank Morauf
 E: frank.morauf@salzbrenner.com
 D: Support for Embedded Planet RPX Super Board

-N: David Müller
+N: David M?ller
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board

@ -499,3 +499,8 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
+
+N: Nobuhiro Iwamatsu
+E: iwamatsu@nigauri.org
+D: Support for SuperH, MS7750SE01 and  MS7722SE01 boards.
+W: http://www.nigauri.org/~iwamatsu/
--- a/12
+++ b/12
@ -634,6 +634,18 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
 	ATSTK1002		AT32AP7000
 	ATSTK1003		AT32AP7001
 	ATSTK1004		AT32AP7002
+ 
+#########################################################################
+# SuperH Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
+
+	MS7750SE		SH7750
+	MS7722SE		SH7722

 #########################################################################
 # End of MAINTAINERS list						#
--- a/21
+++ b/21
@ -657,6 +657,23 @@ LIST_blackfin="		\
 	bf561-ezkit	\
 "

+#########################################################################
+## SH Systems
+#########################################################################
+
+LIST_sh4="		\
+	ms7750se	\
+	ms7722se	\
+"
+
+LIST_sh3=""
+
+
+LIST_sh="		\
+	${LIST_sh3}	\
+	${LIST_sh4}	\
+"
+
 #-----------------------------------------------------------------------

 #----- for now, just run PPC by default -----
@ -691,7 +708,9 @@ do
 	mips|mips_el| \
 	nios|nios2| \
 	ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
-	x86|I486|TSEC)
+	x86|I486|TSEC| \
+	sh|sh4|sh3 \
+	)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
--- a/20
+++ b/20
@ -152,6 +152,9 @@ endif
 ifeq ($(ARCH),avr32)
 CROSS_COMPILE = avr32-linux-
 endif
+ifeq ($(ARCH),sh)
+CROSS_COMPILE = sh4-linux-
+endif
 endif
 endif

@ -2668,6 +2671,23 @@ atstk1004_config	:	unconfig
 #########################################################################
 #########################################################################

+#########################################################################
+## sh4 (Renesas SuperH)
+#########################################################################
+ms7750se_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MS7750SE 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 ms7750se
+
+ms7722se_config :       unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MS7722SE 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 ms7722se
+
+#########################################################################
+#########################################################################
+#########################################################################
+
 clean:
 	find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
--- a/board/ms7722se/Makefile
+++ b/board/ms7722se/Makefile
@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#     
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7722se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/ms7722se/config.mk
+++ b/board/ms7722se/config.mk
@ -0,0 +1,32 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/config.mk
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000
+
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@ -0,0 +1,296 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *    
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+/*
+ *  Board specific low level init code, called _very_ early in the
+ *  startup sequence. Relocation to SDRAM has not happened yet, no
+ *  stack is available, bss section has not been initialised, etc.
+ *
+ *  (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	mov.l	CCR_A, r1	! Address of Cache Control Register
+	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+	mov.l	r0, @r1
+
+	mov.l	MMUCR_A, r1	! Address of MMU Control Register
+	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
+	mov.l	MSTPCR0_D, r0	! 
+	mov.l	r0, @r1
+
+	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
+	mov.l	MSTPCR2_D, r0	! 
+	mov.l	r0, @r1
+
+	mov.l	SBSCR_A, r1	! 
+	mov.w	SBSCR_D, r0	! 
+	mov.w	r0, @r1
+
+	mov.l	PSCR_A, r1	! 
+	mov.w	PSCR_D, r0	! 
+	mov.w	r0, @r1
+
+!	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+!	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+!	mov.w	r0, @r1
+
+	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
+	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+	mov.w	r0, @r1
+
+	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	mov.l	FRQCR_D, r0	! 
+	mov.l	r0, @r1
+
+	mov.l	CCR_A, r1		! Address of Cache Control Register
+	mov.l	CCR_D_2, r0	! ??
+	mov.l	r0, @r1
+
+bsc_init:
+
+	mov.l	PSELA_A, r1
+	mov.w	PSELA_D, r0
+	mov.w	r0, @r1
+
+	mov.l	DRVCR_A, r1
+	mov.w	DRVCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PCCR_A, r1
+	mov.w	PCCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PECR_A, r1
+	mov.w	PECR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PJCR_A, r1
+	mov.w	PJCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	PXCR_A, r1
+	mov.w	PXCR_D, r0
+	mov.w	r0, @r1
+
+	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	r0, @r1		! CMNCR set
+
+	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	r0, @r1		! CS0BCR set
+
+	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
+	mov.l	CS2BCR_D, r0	! CS2BCR data    -> R0
+	mov.l	r0, @r1		! CS2BCR set
+
+	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
+	mov.l	r0, @r1		! CS4BCR set
+
+	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	r0, @r1		! CS5ABCR set
+
+	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	r0, @r1		! CS5BBCR set
+
+	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	r0, @r1		! CS6ABCR set
+
+	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	r0, @r1		! CS0WCR set
+
+	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
+	mov.l 	CS2WCR_D, r0	! CS2WCR data    -> R0
+	mov.l	r0, @r1		! CS2WCR set
+
+	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	r0, @r1		! CS4WCR set
+
+	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	r0, @r1		! CS5AWCR set
+
+	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	r0, @r1		! CS5BWCR set
+
+	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	r0, @r1		! CS6AWCR set
+
+	! SDRAM initialization
+	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
+	mov.l	r0, @r1		! SB_SDCR set
+
+	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
+	mov.l	r0, @r1		! SB_SDWCR set
+
+	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
+	mov.l	r0, @r1		! SB_SDPCR set
+
+	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
+	mov.l	r0, @r1		! SB_RTCOR set
+
+	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
+	mov.l	r0, @r1		! SB_RTCSR set
+
+	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov.b	r0, @r1		! SDMR3 set
+
+	! BL bit off (init = ON)  (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	mov	#0, r0
+
+
+
+	.align	2
+
+CCR_A:		.long	CCR			
+MMUCR_A:	.long	MMUCR
+MSTPCR0_A:	.long	MSTPCR0
+MSTPCR2_A:	.long	MSTPCR2
+SBSCR_A:	.long	SBSCR
+PSCR_A:		.long	PSCR
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+
+CCR_D:		.long	0x00000800
+CCR_D_2:	.long	0x00000103
+MMUCR_D:	.long	0x00000004
+MSTPCR0_D:	.long	0x00001001
+MSTPCR2_D:	.long	0xffffffff
+FRQCR_D:	.long	0x07022538
+
+PSELA_A:	.long   0xa405014E
+PSELA_D:	.word   0x0A10
+        .align 2
+
+DRVCR_A:	.long   0xa405018A
+DRVCR_D:	.word   0x0554
+	.align 2
+
+PCCR_A:		.long   0xa4050104
+PCCR_D:		.word   0x8800
+	.align 2
+
+PECR_A:		.long   0xa4050108
+PECR_D:		.word   0x0000
+	.align 2
+
+PJCR_A:		.long   0xa4050110
+PJCR_D:		.word   0x1000
+	.align 2
+
+PXCR_A:		.long   0xa4050148
+PXCR_D:		.word   0x0AAA
+	.align 2
+
+CMNCR_A:	.long	CMNCR
+CMNCR_D:	.long	0x00000013
+CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_D:	.long	0x24920400
+CS2BCR_A:	.long	CS2BCR		! SRAM
+CS2BCR_D:	.long	0x24920400
+CS4BCR_A:	.long	CS4BCR		! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_A:	.long	CS5ABCR		! Ext slot
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_A:	.long	CS5BBCR		! USB controller
+CS5BBCR_D:	.long	0x24920400
+CS6ABCR_A:	.long	CS6ABCR		! Ethernet
+CS6ABCR_D:	.long	0x24920400
+
+CS0WCR_A:	.long	CS0WCR
+CS0WCR_D:	.long	0x00000300
+CS2WCR_A:	.long	CS2WCR
+CS2WCR_D:	.long	0x00000300
+CS4WCR_A:	.long	CS4WCR
+CS4WCR_D:	.long	0x00000300
+CS5AWCR_A:	.long	CS5AWCR
+CS5AWCR_D:	.long	0x00000300
+CS5BWCR_A:	.long	CS5BWCR
+CS5BWCR_D:	.long	0x00000300
+CS6AWCR_A:	.long	CS6AWCR
+CS6AWCR_D:	.long	0x00000300
+
+SDCR_A:		.long	SBSC_SDCR
+SDCR_D:		.long	0x00020809
+SDWCR_A:	.long	SBSC_SDWCR
+SDWCR_D:	.long	0x00164d0d
+SDPCR_A:	.long	SBSC_SDPCR
+SDPCR_D:	.long	0x00000087
+RTCOR_A:	.long	SBSC_RTCOR
+RTCOR_D:	.long	0xA55A0034
+RTCSR_A:	.long	SBSC_RTCSR
+RTCSR_D:	.long	0xA55A0010
+SDMR3_A:	.long	0xFE500180
+
+	.align	1
+
+SBSCR_D:	.word	0x0040
+PSCR_D:		.word	0x0000
+RWTCSR_D_1:	.word	0xA507
+RWTCSR_D_2:	.word	0xA507
+RWTCNT_D:	.word	0x5A00
+
+SR_MASK_D:	.long	0xEFFFFF0F
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ * 
+ * board/ms7722se/ms7722se.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define LED_BASE	0xB0800000
+
+int checkboard(void)
+{
+	puts("BOARD: Hitachi UL MS7722SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Setup PTXMD[1:0] for /CS6A */
+	outw(inw(PXCR) & ~0xf000, PXCR);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+	*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
+}
+
--- a/board/ms7722se/u-boot.lds
+++ b/board/ms7722se/u-boot.lds
@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+	   
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+	   
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+	
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+	
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .); 
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
+
--- a/board/ms7750se/Makefile
+++ b/board/ms7750se/Makefile
@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7750se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
--- a/board/ms7750se/config.mk
+++ b/board/ms7750se/config.mk
@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x8FFC0000
--- a/board/ms7750se/lowlevel_init.S
+++ b/board/ms7750se/lowlevel_init.S
@ -0,0 +1,180 @@
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 
+ 
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+	.global lowlevel_init
+	.text
+	.align  2
+
+lowlevel_init:
+
+	mov.l   CCR_A, r1               ! CCR Address
+	mov.l   CCR_D_DISABLE, r0       ! CCR Data
+	mov.l   r0, @r1
+
+init_bsc:
+	mov.l	FRQCR_A,r1	/* FRQCR Address */
+	mov.l	FRQCR_D,r0	/* FRQCR Data */
+	mov.w	r0,@r1
+
+	mov.l	BCR1_A,r1	/* BCR1 Address */
+	mov.l	BCR1_D,r0	/* BCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	BCR2_A,r1	/* BCR2 Address */
+	mov.l	BCR2_D,r0	/* BCR2 Data */
+	mov.w	r0,@r1
+
+	mov.l	WCR1_A,r1	/* WCR1 Address */
+	mov.l	WCR1_D,r0	/* WCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR2_A,r1	/* WCR2 Address */
+	mov.l	WCR2_D,r0	/* WCR2 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR3_A,r1	/* WCR3 Address */
+	mov.l	WCR3_D,r0	/* WCR3 Data */
+	mov.l	r0,@r1
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D1,r0	/* MCR Data1 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	! Do you need PCMCIA setting?	
+	! If so, please add the lines here...
+
+	mov.l	RTCNT_A,r1	/* RTCNT Address */
+	mov.l	RTCNT_D,r0	/* RTCNT Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCOR_A,r1	/* RTCOR Address */
+	mov.l	RTCOR_D,r0	/* RTCOR Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCSR_A,r1	/* RTCSR Address */
+	mov.l	RTCSR_D,r0	/* RTCSR Data */
+	mov.w	r0,@r1
+
+	mov.l	RFCR_A,r1	/* RFCR Address */
+	mov.l	RFCR_D,r0	/* RFCR Data */
+	mov.w	r0,@r1		/* Clear reflesh counter */
+	/* Wait DRAM refresh 30 times */
+	mov	#30,r3
+1:
+	mov.w	@r1,r0
+	extu.w	r0,r2
+	cmp/hi	r3,r2
+	bf	1b
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D2,r0	/* MCR Data2 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	rts
+	 nop
+
+	.align	2
+
+CCR_A:          .long   CCR
+CCR_D_DISABLE:  .long   0x0808
+FRQCR_A:	.long	FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+		.long	0x00000e1a	/* 12:3:3 */
+#else	/* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+		.long	0x00000e13	/* 6:2:1 */
+#else
+		.long	0x00000e23	/* 6:1:1 */
+#endif
+#endif	/* CONFIG_CPU_TYPE_R */
+
+BCR1_A:		.long	BCR1
+BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
+BCR2_A:		.long	BCR2
+BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
+WCR1_A:		.long	WCR1
+WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
+WCR2_A:		.long	WCR2
+WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
+WCR3_A:		.long	WCR3
+WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
+RTCSR_A:	.long	RTCSR	
+RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCNT_A:	.long	RTCNT
+RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCOR_A:	.long	RTCOR
+RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+SDMR3_A:	.long	SDMR3_ADDRESS
+MCR_A:		.long	MCR
+MCR_D1:		.long	MCR_D1_VALUE
+MCR_D2:		.long	MCR_D2_VALUE
+RFCR_A:		.long	RFCR
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+
--- a/board/ms7750se/ms7750se.c
+++ b/board/ms7750se/ms7750se.c
@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2007 
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
--- a/board/ms7750se/u-boot.lds
+++ b/board/ms7750se/u-boot.lds
@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+	   
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+	   
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+	
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+	
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .); 
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
+
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (hdr->ih_arch != IH_CPU_NIOS2)
 #elif defined(__PPC__)
 	if (hdr->ih_arch != IH_CPU_PPC)
+#elif defined(__sh__)
+	if (hdr->ih_arch != IH_CPU_SH)
 #else
 # error Unknown CPU type
 #endif
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@ -886,7 +886,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 #endif	/* __LITTLE_ENDIAN || CONFIG_AU1X00 */


-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
@ -938,7 +938,7 @@ output_data(int dev, ulong *sect_buf, int words)
 }
 #endif	/* __PPC__ */

-#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
+#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {
--- a/cpu/sh4/Makefile
+++ b/cpu/sh4/Makefile
@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+START	= start.o
+OBJS	= cpu.o interrupts.o watchdog.o time.o cache.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/cpu/sh4/cache.c
+++ b/cpu/sh4/cache.c
@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2()                    \
+  do {                                    \
+    unsigned long __dummy;		\
+    __asm__ __volatile__(			\
+                "mov.l  1f, %0\n\t"     \
+                "or     %1, %0\n\t"     \
+                "jmp    @%0\n\t"        \
+                " nop\n\t"              \
+                ".balign 4\n"           \
+                "1:     .long 2f\n"     \
+                "2:"                    \
+                : "=&r" (__dummy)       \
+                : "r" (0x20000000));    \
+  } while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1()                                    \
+  do {                                                    \
+    unsigned long __dummy;                          \
+    __asm__ __volatile__(                           \
+                "nop;nop;nop;nop;nop;nop;nop\n\t"       \
+                "mov.l  1f, %0\n\t"                     \
+                "jmp    @%0\n\t"                        \
+                " nop\n\t"                              \
+                ".balign 4\n"                           \
+                "1:     .long 2f\n"                     \
+                "2:"                                    \
+                : "=&r" (__dummy));                     \
+  } while (0)
+
+#define CACHE_VALID       1
+#define CACHE_UPDATED     2
+
+static inline void cache_wback_all(void)
+{
+	unsigned long addr, data, i, j;
+
+	jump_to_P2();
+	for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+		for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+      			addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+				| (i << CACHE_OC_ENTRY_SHIFT);
+      			data = inl(addr);
+			if (data & CACHE_UPDATED) {
+				data &= ~CACHE_UPDATED;
+				outl(data, addr);
+			}
+		}
+	}
+	back_to_P1();
+}
+
+
+#define CACHE_ENABLE      0
+#define CACHE_DISABLE     1
+
+int cache_control(unsigned int cmd)
+{
+	unsigned long ccr;
+
+	jump_to_P2();
+	ccr = inl(CCR);
+
+	if (ccr & CCR_CACHE_ENABLE)
+		cache_wback_all();
+
+	if (cmd == CACHE_DISABLE)
+		outl(CCR_CACHE_STOP, CCR);
+	else
+		outl(CCR_CACHE_INIT, CCR);
+	back_to_P1();
+
+	return 0;
+}
--- a/cpu/sh4/config.mk
+++ b/cpu/sh4/config.mk
@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#   
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+PLATFORM_CPPFLAGS += -m4-nofpu
+PLATFORM_RELFLAGS += -ffixed-r13
--- a/cpu/sh4/cpu.c
+++ b/cpu/sh4/cpu.c
@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+int checkcpu(void)
+{
+	puts("CPU: SH4\n");
+	return 0;
+}
+
+int cpu_init (void)
+{
+	return 0;
+}
+
+int cleanup_before_linux (void)
+{
+	disable_interrupts();
+	return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	disable_interrupts();
+	reset_cpu (0);
+	return 0;
+}
+
+void flush_cache (unsigned long addr, unsigned long size)
+{
+
+}
+
+void icache_enable (void)
+{
+	cache_control(0);
+}
+
+void icache_disable (void)
+{
+	cache_control(1);
+}
+
+int icache_status (void)
+{
+	return 0; 
+}
+
+void dcache_enable (void)
+{
+}
+
+void dcache_disable (void)
+{
+}
+
+int dcache_status (void)
+{
+	return 0;
+}
--- a/cpu/sh4/interrupts.c
+++ b/cpu/sh4/interrupts.c
@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int interrupt_init (void)
+{
+	return 0; 
+}
+
+void enable_interrupts (void)
+{
+
+}
+
+int disable_interrupts (void){ 
+	return 0; 
+}
+
--- a/cpu/sh4/start.S
+++ b/cpu/sh4/start.S
@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+	.text
+	.align	2
+
+	.global	_start
+_start:
+	mov.l	._lowlevel_init, r0
+100:	bsrf	r0
+	nop
+
+	bsr	1f
+	nop
+1:	sts	pr, r5
+	mov.l	._reloc_dst, r4	
+	add	#(_start-1b), r5	
+	mov.l	._reloc_dst_end, r6	
+
+2:	mov.l	@r5+, r1
+	mov.l	r1, @r4
+	add	#4, r4
+	cmp/hs	r6, r4
+	bf	2b
+	
+	mov.l	._bss_start, r4	
+	mov.l	._bss_end, r5		
+	mov	#0, r1
+
+3:	mov.l	r1, @r4			/* bss clear */	
+	add	#4, r4
+	cmp/hs	r5, r4
+	bf	3b
+
+	mov.l	._gd_init, r13		/* global data */
+	mov.l	._stack_init, r15	/* stack */
+
+	mov.l	._sh_generic_init, r0
+	jsr	@r0			
+	nop				
+
+loop:
+	bra	loop
+
+	.align	2
+
+._lowlevel_init:	.long	(lowlevel_init - (100b + 4))
+._reloc_dst:		.long	reloc_dst
+._reloc_dst_end:	.long	reloc_dst_end
+._bss_start:		.long	bss_start
+._bss_end:		.long	bss_end
+._gd_init:		.long	(_start - CFG_GBL_DATA_SIZE)
+._stack_init:		.long	(_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._sh_generic_init:	.long	sh_generic_init
+
--- a/cpu/sh4/time.c
+++ b/cpu/sh4/time.c
@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2007
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define TMU_MAX_COUNTER (~0UL)
+
+static void tmu_timer_start (unsigned int timer)
+{
+	if (timer > 2)
+		return;
+
+	*((volatile unsigned char *) TSTR) |= (1 << timer);
+}
+
+static void tmu_timer_stop (unsigned int timer)
+{
+	u8 val = *((volatile u8 *)TSTR);
+	if (timer > 2)
+		return;
+	*((volatile unsigned char *)TSTR) = val &~(1 << timer);
+}
+
+int timer_init (void)
+{
+	/* Divide clock by 4 */
+	*(volatile u16 *)TCR0 = 0;
+
+	tmu_timer_stop(0);
+	tmu_timer_start(0);
+	return 0;
+}
+
+/*
+   In theory we should return a true 64bit value (ie something that doesn't
+   overflow). However, we don't. Therefore if TMU runs at fastest rate of
+   6.75 MHz this value will wrap after u-boot has been running for approx
+   10 minutes.
+*/
+unsigned long long get_ticks (void)
+{
+	return (0 - *((volatile u32 *) TCNT0));
+}
+
+unsigned long get_timer (unsigned long base)
+{
+	return ((0 - *((volatile u32 *) TCNT0)) - base);
+}
+
+void set_timer (unsigned long t)
+{
+	*((volatile unsigned int *) TCNT0) = (0 - t);
+}
+
+void reset_timer (void)
+{
+	tmu_timer_stop(0);
+	set_timer (0);
+	tmu_timer_start(0);
+}
+
+void udelay (unsigned long usec)
+{
+	unsigned int start = get_timer (0);
+	unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+	while (get_timer (0) < end)
+		continue;
+}
+
+unsigned long get_tbclk (void)
+{
+	return CFG_HZ;
+}
--- a/cpu/sh4/watchdog.c
+++ b/cpu/sh4/watchdog.c
@ -0,0 +1,52 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define WDT_BASE	WTCNT
+
+static unsigned char cnt_read (void){
+	return *((volatile unsigned char *)(WDT_BASE + 0x00));
+}
+
+static unsigned char csr_read (void){
+	return *((volatile unsigned char *)(WDT_BASE + 0x04));
+}
+
+static void cnt_write (unsigned char value){
+	while (csr_read() & (1 << 5)) {
+		/* delay */
+	}
+	*((volatile unsigned short *)(WDT_BASE + 0x00)) 
+		= ((unsigned short) value) | 0x5A00;
+}
+
+static void csr_write (unsigned char value){
+	*((volatile unsigned short *)(WDT_BASE + 0x04)) 
+		= ((unsigned short) value) | 0xA500;
+}
+
+
+int watchdog_init (void){ return 0; }
+
+void reset_cpu (unsigned long ignored)
+{
+	while(1);
+}
+
+
--- a/doc/README.marubun-pcmcia
+++ b/doc/README.marubun-pcmcia
@ -0,0 +1,65 @@
+
+U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
+	Last update 21/11/2007 by Nobuhiro Iwamatsu
+	
+========================================================================================
+
+0. What's this? 
+    This driver supports MARUBUN MR-SHPC-01.
+	url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html
+	(Sorry Japanese only.)
+
+    This chip is used with SuperH well, and adopted by the 
+    reference board. 
+	ex. * MS7750SE01
+		* MS7722SE01
+		* other 
+		
+    This chip doesn't support CardBus.
+
+1. base source code 
+    The code is based on sources from the Linux kernel
+    	( arch/sh/kernel/cf-enabler.c ). 
+
+2. How to use 
+    The options you have to specify in the config file are (with the
+    value for my board as an example):
+
+    * CONFIG_MARUBUN_PCCARD
+	If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
+	ex. 	#define CONFIG_MARUBUN_PCCARD
+		
+    * CONFIG_PCMCIA_SLOT_A
+    	Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
+	ex.	#define CONFIG_PCMCIA_SLOT_A    1
+
+    * CFG_MARUBUN_MRSHPC
+    	This is MR-SHPC-01 PCMCIA controler base address.
+	You should do the setting matched to your environment. 
+	ex.  #define CFG_MARUBUN_MRSHPC 0xb03fffe0 
+	     ( for MS7722SE01 environment )
+
+    * CFG_MARUBUN_MW1
+	This is MR-SHPC-01 memory window base address.
+	You should do the setting matched to your environment. 
+	ex. #define CFG_MARUBUN_MW1 0xb0400000
+	     ( for MS7722SE01 environment )
+	
+    * CFG_MARUBUN_MW1
+	This is MR-SHPC-01 attribute window base address.
+	You should do the setting matched to your environment. 
+	ex. #define CFG_MARUBUN_MW2 0xb0500000
+	     ( for MS7722SE01 environment )
+	     
+    * CFG_MARUBUN_MW1
+	This is MR-SHPC-01 I/O window base address.
+	You should do the setting matched to your environment. 
+	ex. #define CFG_MARUBUN_IO  0xb0600000
+	     ( for MS7722SE01 environment )
+
+3. Other
+    * Check Compact Flash only.
+    * Maybe, NE2000 compatible NIC is sure to move.
+
+Copyright (c) 2007
+	Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
--- a/doc/README.sh
+++ b/doc/README.sh
@ -0,0 +1,62 @@
+
+U-Boot for Renesas SuperH 
+	Last update 08/10/2007 by Nobuhiro Iwamatsu
+
+================================================================================
+0. What's this?
+	This file contains status information for the port of U-Boot to the
+	Renesas SuperH series of CPUs.
+
+================================================================================
+1. Overview
+	SuperH has an original boot loader. However, source code is dirty, and 
+	maintenance is not done.
+	To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu 
+	started the porting to u-boot in 2007. 
+
+================================================================================
+2. Supported CPUs
+
+	2.1. Renesas SH7750/SH7750R
+	2.2. Renesas SH7722
+
+================================================================================
+3. Supported Boards
+
+	3.1. Hitachi UL MS7750SE01/MS7750RSE01
+		Board specific code is in board/ms7750se
+		To use this board, type "make ms7750se_config".
+
+	3.2. Hitachi UL MS7722SE01
+		Board specific code is in board/ms7722se
+		To use this board, type "make ms7722se_config".
+
+	** README **
+		In SuperH, S-record and binary of made u-boot work on the memory.
+		When u-boot is written in the flash, it is necessary to change the 
+		address by using 'objcopy'.  
+		ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
+	
+================================================================================
+4. Compiler
+	You can use the following of u-boot to compile. 
+		- SuperH Linux Open site
+			http://www.superh-linux.org/
+		- KPIT GNU tools
+			http://www.kpitgnutools.com/
+
+================================================================================
+5. Future
+	I plan to support the following CPUs and boards.
+		5.1. CPUs
+			- SH7710/SH7712 (SH3)
+			- SH7780(SH4)
+			- SH7785(SH4)
+		
+		5.2. Boards
+			- Many boards ;-)
+
+================================================================================
+Copyright (c) 2007
+    Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
+
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@ -30,6 +30,7 @@ COBJS-y += pxa_pcmcia.o
 COBJS-y += rpx_pcmcia.o
 COBJS-y += ti_pci1410a.o
 COBJS-y += tqm8xx_pcmcia.o
+COBJS-y += marubun_pcmcia.o

 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
--- a/drivers/pcmcia/marubun_pcmcia.c
+++ b/drivers/pcmcia/marubun_pcmcia.c
@ -0,0 +1,113 @@
+/*
+ * Marubun MR-SHPC-01 PCMCIA controller device driver
+ *
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *              
+ */ 
+
+#include <common.h>
+#include <config.h>
+#include <pcmcia.h>
+#include <asm/io.h>
+
+#if	(CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if	(CONFIG_COMMANDS & CFG_CMD_IDE)
+#define	CONFIG_PCMCIA
+#endif
+
+#if	defined(CONFIG_PCMCIA)  \
+	        && (defined(CONFIG_MARUBUN_PCCARD)) 
+
+/* MR-SHPC-01 register */
+#define MRSHPC_MODE   	(CFG_MARUBUN_MRSHPC + 4)
+#define MRSHPC_OPTION   (CFG_MARUBUN_MRSHPC + 6)
+#define MRSHPC_CSR      (CFG_MARUBUN_MRSHPC + 8)
+#define MRSHPC_ISR      (CFG_MARUBUN_MRSHPC + 10)
+#define MRSHPC_ICR      (CFG_MARUBUN_MRSHPC + 12)
+#define MRSHPC_CPWCR    (CFG_MARUBUN_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (CFG_MARUBUN_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (CFG_MARUBUN_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (CFG_MARUBUN_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (CFG_MARUBUN_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (CFG_MARUBUN_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (CFG_MARUBUN_MRSHPC + 26)
+#define MRSHPC_CDCR     (CFG_MARUBUN_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (CFG_MARUBUN_MRSHPC + 30)
+
+int pcmcia_on (void)
+{
+	printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	/* Init */
+	outw( 0x0000 , MRSHPC_MODE );
+
+	if ((inw(MRSHPC_CSR) & 0x000c) == 0){	/* if card detect is true */
+		if ((inw(MRSHPC_CSR) & 0x0080) == 0){
+			outw(0x0674 ,MRSHPC_CPWCR);  /* Card Vcc is 3.3v? */
+		}else{
+			outw(0x0678 ,MRSHPC_CPWCR);  /* Card Vcc is 5V */
+		}
+		udelay( 100000 );   /* wait for power on */
+	}else{
+		return 1;
+	}
+	/*
+	 *	PC-Card window open
+	 *	flag == COMMON/ATTRIBUTE/IO
+	 */
+	/* common window open */
+	outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
+	else
+		outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
+	
+	/* attribute window open */
+	outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
+	else
+		outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
+	
+	/* I/O window open */
+	outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
+	outw(0x0008,MRSHPC_CDCR);   /* I/O card mode */
+	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
+		outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
+	else
+		outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
+	
+	outw(0x0000,MRSHPC_ISR);
+	outw(0x2000,MRSHPC_ICR);
+	outb(0x00,(CFG_MARUBUN_MW2 + 0x206));
+	outb(0x42,(CFG_MARUBUN_MW2 + 0x200));
+
+	return 0;
+}
+
+int pcmcia_off (void)
+{
+	printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	return 0;
+}
+
+#endif /* CONFIG_MARUBUN_PCCARD */
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@ -35,6 +35,7 @@ COBJS-y += serial_max3100.o
 COBJS-y += serial_pl010.o
 COBJS-y += serial_pl011.o
 COBJS-y += serial_xuartlite.o
+COBJS-y += serial_sh.o
 COBJS-y += usbtty.o

 COBJS	:= $(COBJS-y)
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@ -0,0 +1,177 @@
+/*
+ * SuperH SCIF device driver.
+ * Copyright (c) 2007 Nobuhiro Iwamatsu
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifdef CFG_SCIF_CONSOLE
+
+#if defined (CONFIG_CONS_SCIF0)
+#define SCIF_BASE	SCIF0_BASE
+#elif defined (CONFIG_CONS_SCIF1)
+#define SCIF_BASE	SCIF1_BASE
+#else
+#error "Default SCIF doesn't set....."
+#endif
+
+#define SCSMR 	(vu_short *)(SCIF_BASE + 0x0)
+#define SCBRR 	(vu_char  *)(SCIF_BASE + 0x4) 
+#define SCSCR 	(vu_short *)(SCIF_BASE + 0x8)
+#define SCFTDR 	(vu_char  *)(SCIF_BASE + 0xC)
+#define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
+#define SCFRDR 	(vu_char  *)(SCIF_BASE + 0x14)
+#define SCFCR 	(vu_short *)(SCIF_BASE + 0x18)
+#define SCFDR 	(vu_short *)(SCIF_BASE + 0x1C)
+#if defined(CONFIG_SH4A)
+#define SCRFDR	(vu_short *)(SCIF_BASE + 0x20)
+#define SCSPTR	(vu_short *)(SCIF_BASE + 0x24)
+#define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
+#define SCRER	(vu_short *)(SCIF_BASE + 0x2C)
+#elif defined (CONFIG_SH4)
+#define SCSPTR 	(vu_short *)(SCIF_BASE + 0x20)
+#define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+#elif defined (CONFIG_SH3)
+#define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+#endif
+
+#define SCR_RE 		(1 << 4)
+#define SCR_TE 		(1 << 5) 
+#define FCR_RFRST	(1 << 1) /* RFCL */
+#define FCR_TFRST	(1 << 2) /* TFCL */
+#define FSR_DR   	(1 << 0)
+#define FSR_RDF  	(1 << 1)
+#define FSR_FER  	(1 << 3)
+#define FSR_BRK  	(1 << 4)
+#define FSR_FER  	(1 << 3)
+#define FSR_TEND 	(1 << 6)
+#define FSR_ER   	(1 << 7)
+
+/*----------------------------------------------------------------------*/
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int divisor = gd->baudrate * 32;
+
+	*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / 
+						(gd->baudrate * 32) - 1;
+}
+
+int serial_init (void)
+{
+	*SCSCR = (SCR_RE | SCR_TE);
+	*SCSMR = 0 ;
+	*SCSMR = 0;
+	*SCFCR = (FCR_RFRST | FCR_TFRST);
+	*SCFCR;
+	*SCFCR = 0;
+
+	serial_setbrg();
+	return 0;
+}
+
+static int serial_tx_fifo_level (void)
+{
+	return (*SCFDR >> 8) & 0x1F;
+}
+
+static int serial_rx_fifo_level (void)
+{
+	return (*SCFDR >> 0) & 0x1F;
+}
+
+void serial_raw_putc (const char c)
+{
+	unsigned int fsr_bits_to_clear;
+
+	while (1) {
+		if (*SCFSR & FSR_TEND) {		/* Tx fifo is empty */
+			fsr_bits_to_clear = FSR_TEND;
+			break;
+		}
+	}
+
+	*SCFTDR = c;
+	if (fsr_bits_to_clear != 0)
+		*SCFSR &= ~fsr_bits_to_clear;
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		serial_raw_putc ('\r');
+	serial_raw_putc (c);
+}
+
+void serial_puts (const char *s)
+{
+	char c;
+	while ((c = *s++) != 0)
+		serial_putc (c);
+}
+
+int serial_tstc (void)
+{
+	return serial_rx_fifo_level() ? 1 : 0;
+}
+
+#define FSR_ERR_CLEAR   0x0063
+#define RDRF_CLEAR      0x00fc
+#define LSR_ORER        1
+void handle_error( void ){
+
+	(void)*SCFSR ;
+	*SCFSR = FSR_ERR_CLEAR ;
+	(void)*SCLSR ;
+	*SCLSR = 0x00 ;
+}
+
+int serial_getc_check( void ){
+	unsigned short status;
+
+	status = *SCFSR ;
+
+	if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
+		handle_error();
+	if( *SCLSR & LSR_ORER )
+		handle_error();
+	return (status & ( FSR_DR | FSR_RDF ));
+}
+
+int serial_getc (void)
+{
+	unsigned short status ;
+	char ch;
+	while(!serial_getc_check());
+
+	ch = *SCFRDR;
+	status =  *SCFSR ;
+
+	*SCFSR = RDRF_CLEAR ;
+
+	if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
+		handle_error();
+
+	if( *SCLSR & LSR_ORER )
+		handle_error();
+
+	return ch ;
+}
+
+#endif	/* CFG_SCIF_CONSOLE */
--- a/examples/Makefile
+++ b/examples/Makefile
@ -61,6 +61,11 @@ ifeq ($(ARCH),avr32)
 LOAD_ADDR = 0x00000000
 endif

+ifeq ($(ARCH),sh)
+LOAD_ADDR = 0x8C000000
+endif
+
+
 include $(TOPDIR)/config.mk

 ELF	= hello_world
--- a/examples/stubs.c
+++ b/examples/stubs.c
@ -151,6 +151,22 @@ gd_t *global_data;
 		:					\
 		: "i"(offsetof(gd_t, jt)), "i"(XF_ ##x)	\
 		: "r8");
+#elif defined(CONFIG_SH)
+/*
+ * r13 holds the pointer to the global_data. r1 is a call clobbered.
+ */
+#define EXPORT_FUNC(x)                  \
+        asm volatile (                  \
+		"       .align  2\n"                    \
+		"       .globl " #x "\n"                \
+		#x ":\n"                                \
+		"       mov     r13, r1\n"              \
+		"       add     %0, r1\n"               \
+		"       add     %1, r1\n"               \
+		"       jmp     @r1\n"                  \
+		"       nop\n"                          \
+		"       nop\n"                          \
+		: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1");
 #else
 #error stubs definition missing for this architecture
 #endif
--- a/include/asm-sh/bitops.h
+++ b/include/asm-sh/bitops.h
@ -0,0 +1,166 @@
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
+
+#ifdef __KERNEL__
+//#include <asm/system.h>
+#include <asm/irqflags.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a |= mask;
+	local_irq_restore(flags);
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+static inline void clear_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a ^= mask;
+	local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+//#include <asm-generic/bitops/non-atomic.h>
+
+static inline unsigned long ffz(unsigned long word)
+{
+	unsigned long result;
+
+	__asm__("1:\n\t"
+		"shlr	%1\n\t"
+		"bt/s	1b\n\t"
+		" add	#1, %0"
+		: "=r" (result), "=r" (word)
+		: "0" (~0L), "1" (word)
+		: "t");
+	return result;
+}
+
+/**
+ * ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline int ffs(int x)
+{
+  int r = 1;
+
+  if (!x)
+    return 0;
+  if (!(x & 0xffff)) {
+    x >>= 16;
+    r += 16;
+  }
+  if (!(x & 0xff)) {
+    x >>= 8;
+    r += 8;
+  }
+  if (!(x & 0xf)) {
+    x >>= 4;
+    r += 4;
+  }
+  if (!(x & 3)) {
+    x >>= 2;
+    r += 2;
+  }
+  if (!(x & 1)) {
+    x >>= 1;
+    r += 1;
+  }
+  return r;
+}
+
+#if 0
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+#endif
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
--- a/include/asm-sh/byteorder.h
+++ b/include/asm-sh/byteorder.h
@ -0,0 +1,31 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SH_BYTEORDER_H_
+#define __ASM_SH_BYTEORDER_H_
+
+#include <config.h>
+#include <asm/types.h>
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif
+
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH4_H_
+#define _ASM_CPU_SH4_H_
+
+/* cache control */
+#define CCR_CACHE_STOP   0x00000808
+#define CCR_CACHE_ENABLE 0x00000101
+#define CCR_CACHE_ICI    0x00000800
+
+#define CACHE_OC_ADDRESS_ARRAY	0xf4000000
+#define CACHE_OC_WAY_SHIFT	14
+#define CACHE_OC_NUM_ENTRIES	512
+#define CACHE_OC_ENTRY_SHIFT	5
+
+#if defined (CONFIG_CPU_SH7750)
+#include <asm/cpu_sh7750.h>
+#elif defined (CONFIG_CPU_SH7722)
+#include <asm/cpu_sh7722.h>
+#else
+#error "Unknown SH4 variant"
+#endif
+
+#endif	/* _ASM_CPU_SH4_H_ */
--- a/include/asm-sh/cpu_sh7722.h
+++ b/include/asm-sh/cpu_sh7722.h
--- a/include/asm-sh/cpu_sh7750.h
+++ b/include/asm-sh/cpu_sh7750.h
@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7750/SH7750S/SH7750R/SH7751/SH7751R 
+ *  Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7750_H_
+#define _ASM_CPU_SH7750_H_
+
+#ifdef CONFIG_CPU_TYPE_R
+#define CACHE_OC_NUM_WAYS     2
+#define CCR_CACHE_INIT   0x8000090d     /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#else
+#define CACHE_OC_NUM_WAYS     1
+#define CCR_CACHE_INIT   0x0000090b
+#endif
+
+/*      OCN     */
+#define PTEH 	0xFF000000
+#define PTEL 	0xFF000004
+#define TTB 	0xFF000008
+#define TEA 	0xFF00000C
+#define MMUCR 	0xFF000010
+#define BASRA 	0xFF000014
+#define BASRB	0xFF000018
+#define CCR	0xFF00001C
+#define TRA 	0xFF000020
+#define EXPEVT 	0xFF000024
+#define INTEVT 	0xFF000028
+#define PTEA 	0xFF000034
+#define QACR0 	0xFF000038
+#define QACR1 	0xFF00003C
+
+/*      UBC     */
+#define BARA 	0xFF200000
+#define BAMRA 	0xFF200004
+#define BBRA 	0xFF200008
+#define BARB 	0xFF20000C
+#define BAMRB 	0xFF200010
+#define BBRB 	0xFF200014
+#define BDRB 	0xFF200018
+#define BDMRB 	0xFF20001C
+#define BRCR 	0xFF200020
+
+/*      BSC     */
+#define BCR1	0xFF800000
+#define BCR2	0xFF800004
+#define BCR3 	0xFF800050
+#define BCR4	0xFE0A00F0
+#define WCR1 	0xFF800008
+#define WCR2 	0xFF80000C
+#define WCR3 	0xFF800010
+#define MCR 	0xFF800014
+#define PCR 	0xFF800018
+#define RTCSR 	0xFF80001C
+#define RTCNT 	0xFF800020
+#define RTCOR 	0xFF800024
+#define RFCR 	0xFF800028
+#define PCTRA 	0xFF80002C
+#define PDTRA 	0xFF800030
+#define PCTRB 	0xFF800040
+#define PDTRB 	0xFF800044
+#define GPIOIC 	0xFF800048
+
+/*      DMAC    */
+#define SAR0 	0xFFA00000
+#define DAR0 	0xFFA00004
+#define DMATCR0 0xFFA00008
+#define CHCR0	0xFFA0000C
+#define SAR1 	0xFFA00010
+#define DAR1 	0xFFA00014
+#define DMATCR1 0xFFA00018
+#define CHCR1 	0xFFA0001C
+#define SAR2 	0xFFA00020
+#define DAR2 	0xFFA00024
+#define DMATCR2 0xFFA00028
+#define CHCR2 	0xFFA0002C
+#define SAR3 	0xFFA00030
+#define DAR3 	0xFFA00034
+#define DMATCR3 0xFFA00038
+#define CHCR3 	0xFFA0003C
+#define DMAOR 	0xFFA00040
+#define SAR4	0xFFA00050
+#define DAR4 	0xFFA00054
+#define DMATCR4 0xFFA00058
+
+/*      CPG     */
+#define FRQCR 	0xFFC00000
+#define STBCR 	0xFFC00004
+#define WTCNT 	0xFFC00008
+#define WTCSR 	0xFFC0000C
+#define STBCR2 	0xFFC00010
+
+/*      RTC     */
+#define R64CNT	0xFFC80000
+#define RSECCNT 0xFFC80004
+#define RMINCNT 0xFFC80008
+#define RHRCNT 	0xFFC8000C
+#define RWKCNT 	0xFFC80010
+#define RDAYCNT 0xFFC80014
+#define RMONCNT 0xFFC80018
+#define RYRCNT 	0xFFC8001C
+#define RSECAR 	0xFFC80020
+#define RMINAR 	0xFFC80024
+#define RHRAR 	0xFFC80028
+#define RWKAR 	0xFFC8002C
+#define RDAYAR 	0xFFC80030
+#define RMONAR 	0xFFC80034
+#define RCR1 	0xFFC80038
+#define RCR2 	0xFFC8003C
+#define RCR3 	0xFFC80050
+#define RYRAR 	0xFFC80054
+
+/*      ICR     */
+#define ICR 	0xFFD00000
+#define IPRA 	0xFFD00004
+#define IPRB 	0xFFD00008
+#define IPRC	0xFFD0000C
+#define IPRD 	0xFFD00010
+#define INTPRI 	0xFE080000
+#define INTREQ	0xFE080020
+#define INTMSK	0xFE080040
+#define INTMSKCL	0xFE080060
+
+/*      CPG     */
+#define CLKSTP		0xFE0A0000
+#define CLKSTPCLR	0xFE0A0008
+
+/*      TMU     */
+#define TSTR2 	0xFE100004
+#define TCOR3 	0xFE100008
+#define TCNT3 	0xFE10000C
+#define TCR3 	0xFE100010
+#define TCOR4 	0xFE100014
+#define TCNT4 	0xFE100018
+#define TCR4 	0xFE10001C
+#define TOCR 	0xFFD80000
+#define TSTR0 	0xFFD80004
+#define TCOR0	0xFFD80008
+#define TCNT0 	0xFFD8000C
+#define TCR0 	0xFFD80010
+#define TCOR1 	0xFFD80014
+#define TCNT1 	0xFFD80018
+#define TCR1 	0xFFD8001C
+#define TCOR2 	0xFFD80020
+#define TCNT2 	0xFFD80024
+#define TCR2 	0xFFD80028
+#define TCPR2 	0xFFD8002C
+#define TSTR	TSTR0
+
+/*      SCI     */
+#define SCSMR1 	0xFFE00000
+#define SCBRR1 	0xFFE00004
+#define SCSCR1 	0xFFE00008
+#define SCTDR1 	0xFFE0000C
+#define SCSSR1 	0xFFE00010
+#define SCRDR1 	0xFFE00014
+#define SCSCMR1 0xFFE00018
+#define SCSPTR1 0xFFE0001C
+#define SCF0_BASE	SCSMR1
+
+/*      SCIF    */
+#define SCSMR2 	0xFFE80000
+#define SCBRR2 	0xFFE80004
+#define SCSCR2 	0xFFE80008
+#define SCFTDR2 0xFFE8000C
+#define SCFSR2 	0xFFE80010
+#define SCFRDR2	0xFFE80014
+#define SCFCR2 	0xFFE80018
+#define SCFDR2 	0xFFE8001C
+#define SCSPTR2	0xFFE80020
+#define SCLSR2 	0xFFE80024
+#define SCIF1_BASE	SCSMR2
+
+/*      H-UDI   */
+#define SDIR 	0xFFF00000
+#define SDDR 	0xFFF00008
+#define SDINT 	0xFFF00014
+
+#endif	/* _ASM_CPU_SH7750_H_ */
--- a/include/asm-sh/errno.h
+++ b/include/asm-sh/errno.h
@ -0,0 +1,156 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Arg list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif
--- a/include/asm-sh/global_data.h
+++ b/include/asm-sh/global_data.h
@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_SH_GLOBALDATA_H_
+#define __ASM_SH_GLOBALDATA_H_
+
+typedef	struct global_data
+{
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz! */
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid */
+	void		**jt;		/* Standalone app jump table */
+}gd_t;
+
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#define DECLARE_GLOBAL_DATA_PTR	register gd_t *gd asm ("r13")
+
+#endif /* __ASM_SH_GLOBALDATA_H_ */
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@ -0,0 +1,231 @@
+/*
+ *  linux/include/asm-sh/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)		__arch_putb(v,a)
+#define __raw_writew(v,a)		__arch_putw(v,a)
+#define __raw_writel(v,a)		__arch_putl(v,a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
+#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
+#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0	/* XXX###XXX */
+#include <asm/arch/io.h>
+#endif	/* XXX###XXX */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The SH doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#define outb(v,p)               __raw_writeb(v, p)
+#define outw(v,p)               __raw_writew(cpu_to_le16(v),p)
+#define outl(v,p)               __raw_writel(cpu_to_le32(v),p)
+
+#define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(p,d,l)
+#define outsw(p,d,l)			__raw_writesw(p,d,l)
+#define outsl(p,d,l)			__raw_writesl(p,d,l)
+
+#define insb(p,d,l)			__raw_readsb(p,d,l)
+#define insw(p,d,l)			__raw_readsw(p,d,l)
+#define insl(p,d,l)			__raw_readsl(p,d,l)
+
+#define outb_p(val,port)		outb((val),(port))
+#define outw_p(val,port)		outw((val),(port))
+#define outl_p(val,port)		outl((val),(port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port,from,len)		outsb(port,from,len)
+#define outsw_p(port,from,len)		outsw(port,from,len)
+#define outsl_p(port,from,len)		outsl(port,from,len)
+#define insb_p(port,to,len)		insb(port,to,len)
+#define insw_p(port,to,len)		insw(port,to,len)
+#define insl_p(port,to,len)		insl(port,to,len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off,sz,nocache)				\
+ ({								\
+	unsigned long _off = (off), _size = (sz);		\
+	void *_ret = (void *)0;					\
+	if (iomem_valid_addr(_off, _size))			\
+		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+	_ret;							\
+ })
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
+#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)	__raw_readb(addr)
+#define readw(addr)	__raw_readw(addr)
+#define readl(addr)	__raw_readl(addr)
+#define writeb(v,addr)	__raw_writeb(v, addr)
+#define writew(v,addr)	__raw_writew(v, addr)
+#define writel(v,addr)	__raw_writel(v, addr)
+
+#define check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_pci */
+
+static inline void sync(void)
+{
+}
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_SH_IO_H */
--- a/include/asm-sh/irqflags.h
+++ b/include/asm-sh/irqflags.h
@ -0,0 +1,126 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+static inline void raw_local_irq_enable(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+		"stc	r6_bank, %1\n\t"
+		"or	%1, %0\n\t"
+#endif
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x000000f0)
+		: "memory"
+	);
+}
+
+static inline void raw_local_irq_disable(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+}
+
+static inline void set_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	%2, %0\n\t"
+		"and	%3, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "r" (0x10000000), "r" (0xffffff0f)
+		: "memory"
+	);
+}
+
+static inline void clear_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%2, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x10000000)
+		: "memory"
+	);
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_save_flags(flags) \
+		do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+	return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+	unsigned long flags = __raw_local_save_flags();
+
+	return raw_irqs_disabled_flags(flags);
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+	unsigned long flags, __dummy;
+
+	__asm__ __volatile__ (
+		"stc	sr, %1\n\t"
+		"mov	%1, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		"mov	%1, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags), "=&r" (__dummy)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_irq_save(flags) \
+		do { (flags) = __raw_local_irq_save(); } while (0)
+
+#define local_irq_save raw_local_irq_save
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+	if ((flags & 0xf0) != 0xf0)
+		raw_local_irq_enable();
+}
+#define local_irq_restore raw_local_irq_restore
+
+#endif /* __ASM_SH_IRQFLAGS_H */
--- a/include/asm-sh/posix_types.h
+++ b/include/asm-sh/posix_types.h
@ -0,0 +1,123 @@
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short  __kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_timer_t;
+typedef int		__kernel_clockid_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+typedef unsigned short	__kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef	__FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef	__FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{ 
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef	__FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@ -0,0 +1,8 @@
+#ifndef _ASM_SH_PROCESSOR_H_
+#define _ASM_SH_PROCESSOR_H_
+#if defined CONFIG_SH3
+# include <asm/cpu_sh3.h>
+#elif defined (CONFIG_SH4)
+# include <asm/cpu_sh4.h>
+#endif
+#endif
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@ -0,0 +1,112 @@
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ * from linux kernel code.
+ */
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *	 0 - 15 are integer registers
+ *	17 - 22 are control/special registers
+ *	24 - 39 fp registers
+ *	40 - 47 xd registers
+ *	48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *	16 --- program counter (PC)
+ *	22 --- syscall #
+ *	23 --- floating point communication register
+ */
+#define REG_REG0	 0
+#define REG_REG15	15
+
+#define REG_PC		16
+
+#define REG_PR		17
+#define REG_SR		18
+#define REG_GBR      	19
+#define REG_MACH	20
+#define REG_MACL	21
+
+#define REG_SYSCALL	22
+
+#define REG_FPREG0	23
+#define REG_FPREG15	38
+#define REG_XFREG0	39
+#define REG_XFREG15	54
+
+#define REG_FPSCR	55
+#define REG_FPUL	56
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+	unsigned long regs[16];
+	unsigned long pc;
+	unsigned long pr;
+	unsigned long sr;
+	unsigned long gbr;
+	unsigned long mach;
+	unsigned long macl;
+	long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+	unsigned long	a1;
+	unsigned long	a0g;
+	unsigned long	a1g;
+	unsigned long	m0;
+	unsigned long	m1;
+	unsigned long	a0;
+	unsigned long	x0;
+	unsigned long	x1;
+	unsigned long	y0;
+	unsigned long	y1;
+	unsigned long	dsr;
+	unsigned long	rs;
+	unsigned long	re;
+	unsigned long	mod;
+};
+
+#define	PTRACE_GETDSPREGS	55
+#define	PTRACE_SETDSPREGS	56
+
+#ifdef __KERNEL__
+#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+	unsigned long pc = instruction_pointer(regs);
+
+	if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
+		pc -= 0x20000000;
+	return pc;
+}
+#endif
+
+#endif /* __ASM_SH_PTRACE_H */
--- a/include/asm-sh/string.h
+++ b/include/asm-sh/string.h
@ -0,0 +1,162 @@
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ *
+ * from linux kernel code.
+ */
+
+#ifdef __KERNEL__               /* only set these up for kernel code */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	__asm__ __volatile__("1:\n\t"
+			     "mov.b	@%1+, %2\n\t"
+			     "mov.b	%2, @%0\n\t"
+			     "cmp/eq	#0, %2\n\t"
+			     "bf/s	1b\n\t"
+			     " add	#1, %0\n\t"
+			     : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+			     : "0" (__dest), "1" (__src)
+			     : "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	if (__n == 0)
+		return __xdest;
+
+	__asm__ __volatile__(
+		"1:\n"
+		"mov.b	@%1+, %2\n\t"
+		"mov.b	%2, @%0\n\t"
+		"cmp/eq	#0, %2\n\t"
+		"bt/s	2f\n\t"
+		" cmp/eq	%5,%1\n\t"
+		"bf/s	1b\n\t"
+		" add	#1, %0\n"
+		"2:"
+		: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+		: "0" (__dest), "1" (__src), "r" (__src+__n)
+		: "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+	register int __res;
+	unsigned long __dummy;
+
+	__asm__ __volatile__(
+		"mov.b	@%1+, %3\n"
+		"1:\n\t"
+		"mov.b	@%0+, %2\n\t"
+		"cmp/eq #0, %3\n\t"
+		"bt	2f\n\t"
+		"cmp/eq %2, %3\n\t"
+		"bt/s	1b\n\t"
+		" mov.b	@%1+, %3\n\t"
+		"add	#-2, %1\n\t"
+		"mov.b	@%1, %3\n\t"
+		"sub	%3, %2\n"
+		"2:"
+		: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+		: "0" (__cs), "1" (__ct)
+		: "t");
+
+	return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+	register int __res;
+	unsigned long __dummy;
+
+	if (__n == 0)
+		return 0;
+
+	__asm__ __volatile__(
+		"mov.b	@%1+, %3\n"
+		"1:\n\t"
+		"mov.b	@%0+, %2\n\t"
+		"cmp/eq %6, %0\n\t"
+		"bt/s	2f\n\t"
+		" cmp/eq #0, %3\n\t"
+		"bt/s	3f\n\t"
+		" cmp/eq %3, %2\n\t"
+		"bt/s	1b\n\t"
+		" mov.b	@%1+, %3\n\t"
+		"add	#-2, %1\n\t"
+		"mov.b	@%1, %3\n"
+		"2:\n\t"
+		"sub	%3, %2\n"
+		"3:"
+		:"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+		: "0" (__cs), "1" (__ct), "r" (__cs+__n)
+		: "t");
+
+	return __res;
+}
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#undef __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+/* arch/sh/lib/strcasecmp.c */
+extern int strcasecmp(const char *, const char *);
+
+#else                           /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY      1
+#define __HAVE_ARCH_STRNCPY     1
+#define __HAVE_ARCH_STRCAT      1
+#define __HAVE_ARCH_STRNCAT     1
+#define __HAVE_ARCH_STRCMP      1
+#define __HAVE_ARCH_STRNCMP     1
+#define __HAVE_ARCH_STRNICMP    1
+#define __HAVE_ARCH_STRCHR      1
+#define __HAVE_ARCH_STRRCHR     1
+#define __HAVE_ARCH_STRSTR      1
+#define __HAVE_ARCH_STRLEN      1
+#define __HAVE_ARCH_STRNLEN     1
+#define __HAVE_ARCH_MEMSET      1
+#define __HAVE_ARCH_MEMCPY      1
+#define __HAVE_ARCH_MEMMOVE     1
+#define __HAVE_ARCH_MEMSCAN     1
+#define __HAVE_ARCH_MEMCMP      1
+#define __HAVE_ARCH_MEMCHR      1
+#define __HAVE_ARCH_STRTOK      1
+
+#endif /* KERNEL */
+#endif /* __ASM_SH_STRING_H */
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@ -0,0 +1,275 @@
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ *
+ * from linux kernel code.
+ */
+
+#include <linux/irqflags.h>
+#include <asm/types.h>
+
+/*
+ *	switch_to() should switch tasks to task nr n, first
+ */
+
+#define switch_to(prev, next, last) do {				\
+ struct task_struct *__last;						\
+ register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;	\
+ register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;	\
+ register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;	\
+ register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;	\
+ register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;	\
+ register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;		\
+ __asm__ __volatile__ (".balign 4\n\t" 					\
+		       "stc.l	gbr, @-r15\n\t" 			\
+		       "sts.l	pr, @-r15\n\t" 				\
+		       "mov.l	r8, @-r15\n\t" 				\
+		       "mov.l	r9, @-r15\n\t" 				\
+		       "mov.l	r10, @-r15\n\t" 			\
+		       "mov.l	r11, @-r15\n\t" 			\
+		       "mov.l	r12, @-r15\n\t" 			\
+		       "mov.l	r13, @-r15\n\t" 			\
+		       "mov.l	r14, @-r15\n\t" 			\
+		       "mov.l	r15, @r1	! save SP\n\t"		\
+		       "mov.l	@r6, r15	! change to new stack\n\t" \
+		       "mova	1f, %0\n\t" 				\
+		       "mov.l	%0, @r2		! save PC\n\t" 		\
+		       "mov.l	2f, %0\n\t" 				\
+		       "jmp	@%0		! call __switch_to\n\t" \
+		       " lds	r7, pr		!  with return to new PC\n\t" \
+		       ".balign	4\n"					\
+		       "2:\n\t"						\
+		       ".long	__switch_to\n"				\
+		       "1:\n\t"						\
+		       "mov.l	@r15+, r14\n\t"				\
+		       "mov.l	@r15+, r13\n\t"				\
+		       "mov.l	@r15+, r12\n\t"				\
+		       "mov.l	@r15+, r11\n\t"				\
+		       "mov.l	@r15+, r10\n\t"				\
+		       "mov.l	@r15+, r9\n\t"				\
+		       "mov.l	@r15+, r8\n\t"				\
+		       "lds.l	@r15+, pr\n\t"				\
+		       "ldc.l	@r15+, gbr\n\t"				\
+		       : "=z" (__last)					\
+		       : "r" (__ts1), "r" (__ts2), "r" (__ts4), 	\
+			 "r" (__ts5), "r" (__ts6), "r" (__ts7) 		\
+		       : "r3", "t");					\
+	last = __last;							\
+} while (0)
+
+/*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+
+#ifdef CONFIG_CPU_SH4A
+#define __icbi()			\
+{					\
+	unsigned long __addr;		\
+	__addr = 0xa8000000;		\
+	__asm__ __volatile__(		\
+		"icbi   %0\n\t"		\
+		: /* no output */	\
+		: "m" (__m(__addr)));	\
+}
+#endif
+
+static inline unsigned long tas(volatile int *m)
+{
+	unsigned long retval;
+
+	__asm__ __volatile__ ("tas.b	@%1\n\t"
+			      "movt	%0"
+			      : "=r" (retval): "r" (m): "t", "memory");
+	return retval;
+}
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#ifdef CONFIG_CPU_SH4A
+#define mb()		__asm__ __volatile__ ("synco": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier()	__icbi()
+#define read_barrier_depends()	do { } while(0)
+#else
+#define mb()		__asm__ __volatile__ ("": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends()	do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#define smp_read_barrier_depends()	read_barrier_depends()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#define smp_read_barrier_depends()	do { } while(0)
+#endif
+
+#define set_mb(var, value) do { xchg(&var, value); } while (0)
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2()			\
+do {					\
+	unsigned long __dummy;		\
+	__asm__ __volatile__(		\
+		"mov.l	1f, %0\n\t"	\
+		"or	%1, %0\n\t"	\
+		"jmp	@%0\n\t"	\
+		" nop\n\t" 		\
+		".balign 4\n"		\
+		"1:	.long 2f\n"	\
+		"2:"			\
+		: "=&r" (__dummy)	\
+		: "r" (0x20000000));	\
+} while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1()					\
+do {							\
+	unsigned long __dummy;				\
+	ctrl_barrier();					\
+	__asm__ __volatile__(				\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
+} while (0)
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val & 0xff;
+	local_irq_restore(flags);
+	return retval;
+}
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size)				\
+({							\
+	unsigned long __xchg__res;			\
+	volatile void *__xchg_ptr = (ptr);		\
+	switch (size) {					\
+	case 4:						\
+		__xchg__res = xchg_u32(__xchg_ptr, x);	\
+		break;					\
+	case 1:						\
+		__xchg__res = xchg_u8(__xchg_ptr, x);	\
+		break;					\
+	default:					\
+		__xchg_called_with_bad_pointer();	\
+		__xchg__res = x;			\
+		break;					\
+	}						\
+							\
+	__xchg__res;					\
+})
+
+#define xchg(ptr,x)	\
+	((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
+	unsigned long new)
+{
+	__u32 retval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	retval = *m;
+	if (retval == old)
+		*m = new;
+	local_irq_restore(flags);       /* implies memory barrier  */
+	return retval;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+		unsigned long new, int size)
+{
+	switch (size) {
+	case 4:
+		return __cmpxchg_u32(ptr, old, new);
+	}
+	__cmpxchg_called_with_bad_pointer();
+	return old;
+}
+
+#define cmpxchg(ptr,o,n)						 \
+  ({									 \
+     __typeof__(*(ptr)) _o_ = (o);					 \
+     __typeof__(*(ptr)) _n_ = (n);					 \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
+				    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+	return set_exception_table_vec(evt >> 5, handler);
+}
+
+/* XXX
+ * disable hlt during certain critical i/o operations
+ */
+#define HAVE_DISABLE_HLT
+void disable_hlt(void);
+void enable_hlt(void);
+
+#define arch_align_stack(x) (x)
+
+#endif
--- a/include/asm-sh/types.h
+++ b/include/asm-sh/types.h
@ -0,0 +1,59 @@
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
--- a/include/asm-sh/u-boot.h
+++ b/include/asm-sh/u-boot.h
@ -0,0 +1,44 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_SH_U_BOOT_H_
+#define __ASM_SH_U_BOOT_H_
+
+
+typedef struct bd_info {
+	unsigned long   bi_memstart;    /* start of DRAM memory */
+	unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
+	unsigned long   bi_flashstart;  /* start of FLASH memory */
+	unsigned long   bi_flashsize;   /* size  of FLASH memory */
+	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long   bi_sramstart;   /* start of SRAM memory */
+	unsigned long   bi_sramsize;    /* size  of SRAM memory */
+	unsigned long   bi_ip_addr;     /* IP Address */
+	unsigned char   bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long   bi_baudrate;    /* Console Baudrate */
+	unsigned long	bi_boot_params; /* where this board expects params */
+} bd_t;
+
+#endif
+
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@ -0,0 +1,137 @@
+/*
+ * Configuation settings for the Hitachi Solution Engine 7722
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MS7722SE_H
+#define __MS7722SE_H
+
+#undef DEBUG 
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7722	1
+#define CONFIG_MS7722SE		1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		192.168.0.22
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_GATEWAYIP	192.168.0.1
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE    (0xB8000000)
+
+/* MEMORY */
+#define MS7722SE_SDRAM_BASE	(0x8C000000)
+#define MS7722SE_FLASH_BASE_1	(0xA0000000)
+//#define MS7722SE_FLASH_BASE_1	(0xA1000000)
+#define MS7722SE_FLASH_BANK_SIZE	(8*1024 * 1024)
+
+#define CFG_LONGHELP				/* undef to save memory	*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Buffer size for input from the Console */
+#define CFG_PBSIZE		256		/* Buffer size for Console output */
+#define CFG_MAXARGS		16		/* max args accepted for monitor commands */
+#define CFG_BARGSIZE		512		/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+#undef  CFG_CONSOLE_INFO_QUIET			/* Suppress display of console information at boot */
+#undef  CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef  CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START	(MS7722SE_SDRAM_BASE)
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+#undef  CFG_ALT_MEMTEST		/* Enable alternate, more extensive, memory test */
+#undef  CFG_MEMTEST_SCRATCH	/* Scratch address used by the alternate memory test */
+
+#undef  CFG_LOADS_BAUD_CHANGE	/* Enable temporary baudrate change while serial download */
+
+#define CFG_SDRAM_BASE	(MS7722SE_SDRAM_BASE)
+#define CFG_SDRAM_SIZE	(64 * 1024 * 1024)	/* maybe more, but if so u-boot doesn't know about it... */
+
+#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */
+
+#define CFG_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image 
+						   	in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_LEN	(128 * 1024)		/* */
+#define CFG_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+#define CFG_GBL_DATA_SIZE	(256)		/* size in bytes reserved for initial data */
+#define CFG_BOOTMAPSZ	(8 * 1024 * 1024)	
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef  CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO			/* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */
+
+#define CFG_MAX_FLASH_SECT	150		/* Max number of sectors on each 
+				   			Flash chip */
+
+/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
+#define CFG_MAX_FLASH_BANKS	2
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
+				  CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
+				}
+
+#define CFG_FLASH_ERASE_TOUT	(3 * 1000)	/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT	(3 * 1000)	/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT	(3 * 1000)	/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)	/* Timeout for Flash clear lock bit operations (in ms) */
+
+#undef  CFG_FLASH_PROTECTION			/* Use hardware flash sectors protection instead of U-Boot software protection */
+
+#undef  CFG_DIRECT_FLASH_TFTP
+
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CFG_ENV_SECT_SIZE	(8 * 1024)
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE) 	/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */		
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif	/* __MS7722SE_H */
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@ -0,0 +1,108 @@
+/*
+ * Configuation settings for the Hitachi Solution Engine 7750
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MS7750SE_H
+#define __MS7750SE_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7750	1
+/* #define CONFIG_CPU_SH7751	1 */
+/* #define CONFIG_CPU_TYPE_R	1 */
+#define CONFIG_MS7750SE		1
+#define __LITTLE_ENDIAN__	1
+
+/*
+ * Command line configuration.
+ */
+//#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_CONS_SCIF1	1
+#define BOARD_LATE_INIT		1
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS    	"console=ttySC0,38400"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE		(0x8C000000)
+#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CFG_LONGHELP		
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+
+/* NOR Flash */
+/* #define CFG_FLASH_BASE		(0xA1000000)*/
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_MAX_FLASH_BANKS	(1)	/* Max number of 
+				 	 * Flash memory banks
+				 	 */
+#define CFG_MAX_FLASH_SECT	142
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)	/* Address of u-boot image in Flash */
+#define CFG_MONITOR_LEN		(128 * 1024)
+#define CFG_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+
+#define CFG_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER	(8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef  CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
+
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define TMU_CLK_DIVIDER		4
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __MS7750SE_H */
--- a/lib_sh/Makefile
+++ b/lib_sh/Makefile
@ -0,0 +1,42 @@
+#
+# Copyright (c) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).a
+
+SOBJS	= 
+
+COBJS	= board.o sh_linux.o # time.o
+
+SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/lib_sh/board.c
+++ b/lib_sh/board.c
@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+
+extern void malloc_bin_reloc (void);
+extern int cpu_init(void);
+extern int board_init(void);
+extern int dram_init(void);
+extern int watchdog_init(void);
+extern int timer_init(void);
+
+const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
+
+unsigned long monitor_flash_len = CFG_MONITOR_LEN;
+
+static unsigned long mem_malloc_start;
+static unsigned long mem_malloc_end;
+static unsigned long mem_malloc_brk;
+
+static void mem_malloc_init (void)
+{
+
+	mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN);
+	mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16);
+	mem_malloc_brk = mem_malloc_start;
+	memset ((void *) mem_malloc_start, 0, 
+		(mem_malloc_end - mem_malloc_start));
+}
+
+void *sbrk (ptrdiff_t increment)
+{
+	unsigned long old = mem_malloc_brk;
+	unsigned long new = old + increment;
+
+	if ((new < mem_malloc_start) ||
+	    (new > mem_malloc_end)) {
+		return NULL;
+	}
+
+	mem_malloc_brk = new;
+	return (void *) old;
+}
+
+static int sh_flash_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_flashsize = flash_init();
+	printf("FLASH: %dMB\n", gd->bd->bi_flashsize / (1024*1024));
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NAND)
+void nand_init (void);
+static int sh_nand_init(void)
+{
+	printf("NAND: ");
+	nand_init();	/* go init the NAND */
+	return 0;
+}
+#endif /* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_CMD_IDE)
+#include <ide.h>
+static int sh_marubun_init(void)
+{
+	puts ("IDE:   ");
+	ide_init();
+	return 0;
+}
+#endif /* (CONFIG_CMD_IDE) */
+
+static int sh_mem_env_init(void)
+{
+	mem_malloc_init();
+	malloc_bin_reloc();
+	env_relocate();
+	jumptable_init();
+	return 0;
+}
+
+static int sh_net_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	char *s, *e;
+	int i;
+
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+	s = getenv("ethaddr");
+	for (i = 0; i < 6; ++i) {
+		gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+		if (s) s = (*e) ? e + 1 : e;
+	}
+
+	return 0;
+}
+
+typedef int (init_fnc_t) (void);
+
+init_fnc_t *init_sequence[] =
+{
+	cpu_init,		/* basic cpu dependent setup */
+	board_init,		/* basic board dependent setup */
+	interrupt_init,		/* set up exceptions */
+	env_init,		/* event init */
+	serial_init,		/* SCIF init */
+	watchdog_init,		/* watchdog init */
+	console_init_f,
+	display_options,
+	checkcpu,
+	checkboard,		/* Check support board */
+	dram_init,		/* SDRAM init */
+	timer_init,		/* SuperH Timer (TCNT0 only) init */
+	sh_flash_init,		/* Flash memory(NOR) init*/
+	sh_mem_env_init,
+#if defined(CONFIG_CMD_NAND)
+	sh_nand_init,		/* Flash memory (NAND) init */
+#endif
+	devices_init,
+	console_init_r,
+	interrupt_init,
+#ifdef BOARD_LATE_INIT
+	board_late_init,
+#endif
+#if defined(CONFIG_CMD_NET)
+	sh_net_init,		/* SH specific eth init */
+#endif
+	NULL			/* Terminate this list */
+};
+
+void sh_generic_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	char *s;
+	int i;
+
+	memset (gd, 0, CFG_GBL_DATA_SIZE);
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	gd->bd = (bd_t *) (gd + 1);	/* At end of global data */
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+
+	bd = gd->bd;
+	bd->bi_memstart	= CFG_SDRAM_BASE;
+	bd->bi_memsize = CFG_SDRAM_SIZE;
+	bd->bi_flashstart = CFG_FLASH_BASE;
+#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE)
+	bd->bi_sramstart= CFG_SRAM_BASE;
+	bd->bi_sramsize	= CFG_SRAM_SIZE;
+#endif
+	bd->bi_baudrate	= CONFIG_BAUDRATE;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr , i++) {
+		if ((*init_fnc_ptr) () != 0) {
+			hang();
+		}
+	}
+
+#if defined(CONFIG_CMD_NET)
+	puts ("Net:   ");
+	eth_initialize(gd->bd);
+
+        if ((s = getenv ("bootfile")) != NULL) {
+		copy_filename (BootFile, s, sizeof (BootFile));
+	}
+#endif /* CONFIG_CMD_NET */
+
+	while (1) {
+		main_loop();
+	}
+}
+
+/***********************************************************************/
+
+void hang (void)
+{
+	puts ("Board ERROR\n");
+	for (;;);
+}
--- a/lib_sh/sh_linux.c
+++ b/lib_sh/sh_linux.c
@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/byteorder.h>
+
+extern image_header_t header;	/* common/cmd_bootm.c */
+
+/* The SH kernel reads arguments from the empty zero page at location
+ * 0 at the start of SDRAM. The following are copied from 
+ * arch/sh/kernel/setup.c and may require tweaking if the kernel sources
+ * change.
+ */
+#define PARAM   ((unsigned char *)CFG_SDRAM_BASE + 0x1000)
+
+#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
+#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
+#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
+#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
+#define INITRD_START (*(unsigned long *) (PARAM+0x010))
+#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
+/* ... */
+#define COMMAND_LINE ((char *) (PARAM+0x100))
+
+#define RAMDISK_IMAGE_START_MASK        0x07FF
+
+#ifdef CFG_DEBUG
+static void hexdump (unsigned char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if ((i % 16) == 0)
+			printf ("%s%08x: ", i ? "\n" : "", (unsigned int) &buf[i]);
+		printf ("%02x ", buf[i]);
+	}
+	printf ("\n");
+}
+#endif
+
+void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+		     ulong addr, ulong *len_ptr, int verify)
+{
+	image_header_t *hdr = &header;
+	char *bootargs = getenv("bootargs");
+	void (*kernel) (void) = (void (*)(void)) ntohl (hdr->ih_ep);
+
+	/* Setup parameters */
+	memset(PARAM, 0, 0x1000);	/* Clear zero page */
+	strcpy(COMMAND_LINE, bootargs);
+
+	kernel();
+}
+
--- a/lib_sh/time.c
+++ b/lib_sh/time.c
@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processer.h>
+
+static void tmu_timer_start (unsigned int timer)
+{
+	if (timer > 2)
+		return;
+
+	*((volatile unsigned char *) TSTR0) |= (1 << timer);
+}
+
+int timer_init (void)
+{
+	*(volatile u16 *)TCR0 = 0;
+
+	tmu_timer_start (0);
+	return 0;
+}
+
+unsigned long long get_ticks (void)
+{
+	return (0 - *((volatile unsigned int *) TCNT0));
+}
+
+unsigned long get_timer (unsigned long base)
+{
+	return ((0 - *((volatile unsigned int *) TCNT0)) - base);
+}
+
+void set_timer (unsigned long t)
+{
+	*((volatile unsigned int *) TCNT0) = (0 - t);
+}
+
+void reset_timer (void)
+{
+	set_timer (0);
+}
+
+void udelay (unsigned long usec)
+{
+	unsigned int start = get_timer (0);
+	unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+	while (get_timer (0) < end)
+		continue;
+}
+
+unsigned long get_tbclk (void)
+{
+	return CFG_HZ;
+}
--- a/sh_config.mk
+++ b/sh_config.mk
@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__