[PATCH] Add support for the UC101 board from MAN.
Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
parent
cdb97a6678
commit
6dedf3d49d
2
Makefile
2
Makefile
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@ -597,6 +597,8 @@ TQM5200_STK100_config: unconfig
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{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
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}
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@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
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uc101_config: unconfig
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@$(MKCONFIG) uc101 ppc mpc5xxx uc101
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#########################################################################
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## MPC8xx Systems
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,41 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# INKA 4X0 board:
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#
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# Valid values for TEXT_BASE are:
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#
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# 0xFFE00000 boot high
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#
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# 0x00100000 boot from RAM (for testing only)
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#
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ifndef TEXT_BASE
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## Standard: boot high
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TEXT_BASE = 0xFFF00000
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## For testing: boot from RAM
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#TEXT_BASE = 0x00100000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,136 @@
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/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(powerpc)
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mpc5xxx/start.o (.text)
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cpu/mpc5xxx/traps.o (.text)
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lib_generic/crc32.o (.text)
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lib_ppc/cache.o (.text)
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lib_ppc/time.o (.text)
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. = DEFINED(env_offset) ? env_offset : .;
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common/environment.o (.ppcenv)
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*(.text)
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*(.fixup)
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*(.got1)
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. = ALIGN(16);
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*(.rodata)
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*(.rodata1)
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*(.rodata.str1.4)
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*(.eh_frame)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x0FFF) & 0xFFFFF000;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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*(.got)
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(4096);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(4096);
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__init_end = .;
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__bss_start = .;
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.bss :
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{
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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}
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_end = . ;
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PROVIDE (end = .);
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}
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@ -0,0 +1,374 @@
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/*
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* (C) Copyright 2006
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <malloc.h>
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/* some SIMPLE GPIO Pins */
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#define GPIO_USB_8 (31-12)
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#define GPIO_USB_7 (31-13)
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#define GPIO_USB_6 (31-14)
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#define GPIO_USB_0 (31-15)
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#define GPIO_PSC3_7 (31-18)
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#define GPIO_PSC3_6 (31-19)
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#define GPIO_PSC3_1 (31-22)
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#define GPIO_PSC3_0 (31-23)
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/* some simple Interrupt GPIO Pins */
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#define GPIO_PSC3_8 2
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#define GPIO_USB1_9 3
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#define GPT_OUT_0 0x00000027
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#define GPT_OUT_1 0x00000037
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#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
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#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
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pgpio->simple_ddr |= (1 << n); \
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pgpio->simple_gpioe |= (1 << n); \
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}
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#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
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pgpio->simple_gpioe |= (1 << n); \
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}
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#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
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(pgpio->simple_dvo | (1 << n)) : \
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(pgpio->simple_dvo & ~(1 << n)) )
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#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
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#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
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#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
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(pgpio->sint_dvo | (1 << n)) : \
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(pgpio->sint_dvo & ~(1 << n)) )
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#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
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pgpio->sint_ddr |= (1 << n); \
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GP_SINT_SET_O(n, v); \
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pgpio->sint_gpioe |= (1 << n); \
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}
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#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
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pgpio->sint_gpioe |= (1 << n); \
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}
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#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
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#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
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#define GP_TIMER_ENABLE_O(n, v) ( \
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((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
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GPT_OUT_1 : \
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GPT_OUT_0 )
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#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
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#define GP_TIMER_GET_O(n, v) ( \
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(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
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#define GP_TIMER_GET_I(n, v) ( \
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(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
|
||||
if (dramsize2 >= 0x13) {
|
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
||||
} else {
|
||||
dramsize2 = 0;
|
||||
}
|
||||
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/* return dramsize + dramsize2; */
|
||||
return dramsize;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: MAN UC101\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void init_ports (void)
|
||||
{
|
||||
volatile struct mpc5xxx_gpio *pgpio =
|
||||
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
|
||||
|
||||
GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
|
||||
GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
|
||||
GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
|
||||
GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
|
||||
GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
|
||||
GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
|
||||
GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
|
||||
GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
|
||||
GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
|
||||
GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
|
||||
GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
|
||||
GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
|
||||
GP_TIMER_ENABLE_O(3, 0); /* LED HB */
|
||||
GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PREBOOT
|
||||
|
||||
static uchar kbd_magic_prefix[] = "key_magic";
|
||||
static uchar kbd_command_prefix[] = "key_cmd";
|
||||
|
||||
struct kbd_data_t {
|
||||
char s1;
|
||||
};
|
||||
|
||||
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
|
||||
{
|
||||
volatile struct mpc5xxx_gpio *pgpio =
|
||||
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
|
||||
|
||||
kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
|
||||
GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
|
||||
GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
|
||||
GP_SIMP_GET_I(GPIO_USB_0) << 0;
|
||||
return kbd_data;
|
||||
}
|
||||
|
||||
static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
|
||||
{
|
||||
char s1 = str[0];
|
||||
|
||||
if (s1 >= '0' && s1 <= '9')
|
||||
s1 -= '0';
|
||||
else if (s1 >= 'a' && s1 <= 'f')
|
||||
s1 = s1 - 'a' + 10;
|
||||
else if (s1 >= 'A' && s1 <= 'F')
|
||||
s1 = s1 - 'A' + 10;
|
||||
else
|
||||
return -1;
|
||||
|
||||
if (s1 != kbd_data->s1) return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uchar *key_match (const struct kbd_data_t *kbd_data)
|
||||
{
|
||||
uchar magic[sizeof (kbd_magic_prefix) + 1];
|
||||
uchar *suffix;
|
||||
uchar *kbd_magic_keys;
|
||||
|
||||
/*
|
||||
* The following string defines the characters that can be appended
|
||||
* to "key_magic" to form the names of environment variables that
|
||||
* hold "magic" key codes, i. e. such key codes that can cause
|
||||
* pre-boot actions. If the string is empty (""), then only
|
||||
* "key_magic" is checked (old behaviour); the string "125" causes
|
||||
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
|
||||
*/
|
||||
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
|
||||
kbd_magic_keys = "";
|
||||
|
||||
/* loop over all magic keys;
|
||||
* use '\0' suffix in case of empty string
|
||||
*/
|
||||
for (suffix = kbd_magic_keys; *suffix ||
|
||||
suffix == kbd_magic_keys; ++suffix) {
|
||||
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
|
||||
|
||||
if (compare_magic(kbd_data, getenv(magic)) == 0) {
|
||||
uchar cmd_name[sizeof (kbd_command_prefix) + 1];
|
||||
char *cmd;
|
||||
|
||||
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
|
||||
cmd = getenv (cmd_name);
|
||||
|
||||
return (cmd);
|
||||
}
|
||||
}
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PREBOOT */
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
/* Init the I/O ports */
|
||||
init_ports ();
|
||||
|
||||
#ifdef CONFIG_PREBOOT
|
||||
struct kbd_data_t kbd_data;
|
||||
/* Decode keys */
|
||||
uchar *str = strdup (key_match (get_keys (&kbd_data)));
|
||||
/* Set or delete definition */
|
||||
setenv ("preboot", str);
|
||||
free (str);
|
||||
#endif /* CONFIG_PREBOOT */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r (void)
|
||||
{
|
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
*(vu_long *)MPC5XXX_BOOTCS_START =
|
||||
*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
|
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP =
|
||||
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
|
||||
/* Interbus enable it here ?? */
|
||||
*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
|
||||
return 0;
|
||||
}
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
void hw_watchdog_reset(void)
|
||||
{
|
||||
/* Trigger HW Watchdog with TIMER_0 */
|
||||
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
|
||||
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -123,7 +123,7 @@ void cpu_init_f (void)
|
|||
#endif
|
||||
|
||||
#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
|
||||
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
|
||||
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
|
||||
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
|
||||
addecr |= (1 << 27);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
|
|||
|
||||
#if (DEBUG & 0x2)
|
||||
if (fec->xcv_type != SEVENWIRE)
|
||||
mpc5xxx_fec_phydump ();
|
||||
mpc5xxx_fec_phydump (dev->name);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -575,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
|
|||
|
||||
#if (DEBUG & 0x2)
|
||||
if (fec->xcv_type != SEVENWIRE)
|
||||
mpc5xxx_fec_phydump ();
|
||||
mpc5xxx_fec_phydump (dev->name);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -882,7 +882,8 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
|||
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
|
||||
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
|
||||
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
|
||||
defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
|
||||
defined(CONFIG_TQM5200) || defined(CONFIG_V38B) || \
|
||||
defined(CONFIG_UC101)
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
fec->xcv_type = MII100;
|
||||
# else
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)libdtt.a
|
||||
|
||||
COBJS = lm75.o ds1621.o adm1021.o
|
||||
COBJS = lm75.o ds1621.o adm1021.o lm81.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Heiko Schocher, DENX Software Enginnering <hs@denx.de>
|
||||
*
|
||||
* based on dtt/lm75.c which is ...
|
||||
*
|
||||
* (C) Copyright 2001
|
||||
* Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* On Semiconductor's LM81 Temperature Sensor
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DTT_LM81
|
||||
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
|
||||
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
|
||||
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81"
|
||||
#endif
|
||||
|
||||
#include <i2c.h>
|
||||
#include <dtt.h>
|
||||
|
||||
/*
|
||||
* Device code
|
||||
*/
|
||||
#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
|
||||
|
||||
int dtt_read(int sensor, int reg)
|
||||
{
|
||||
int dlen = 1;
|
||||
uchar data[2];
|
||||
|
||||
/*
|
||||
* Calculate sensor address and register.
|
||||
*/
|
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
|
||||
|
||||
/*
|
||||
* Now try to read the register.
|
||||
*/
|
||||
if (i2c_read(sensor, reg, 1, data, dlen) != 0)
|
||||
return -1;
|
||||
|
||||
return (int)data[0];
|
||||
} /* dtt_read() */
|
||||
|
||||
|
||||
int dtt_write(int sensor, int reg, int val)
|
||||
{
|
||||
uchar data;
|
||||
|
||||
/*
|
||||
* Calculate sensor address and register.
|
||||
*/
|
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
|
||||
|
||||
data = (char)(val & 0xff);
|
||||
|
||||
/*
|
||||
* Write value to register.
|
||||
*/
|
||||
if (i2c_write(sensor, reg, 1, data, 1) != 0)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
} /* dtt_write() */
|
||||
|
||||
#define DTT_MANU 0x3e
|
||||
#define DTT_REV 0x3f
|
||||
#define DTT_ADR 0x48
|
||||
|
||||
static int _dtt_init(int sensor)
|
||||
{
|
||||
int man;
|
||||
int adr;
|
||||
int rev;
|
||||
|
||||
if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0)
|
||||
return 1;
|
||||
man = dtt_read (sensor, DTT_MANU);
|
||||
if (man != 0x01)
|
||||
return 1;
|
||||
adr = dtt_read (sensor, DTT_ADR);
|
||||
if (adr < 0)
|
||||
return 1;
|
||||
rev = dtt_read (sensor, DTT_REV);
|
||||
if (adr < 0)
|
||||
return 1;
|
||||
|
||||
printf ("DTT: Found LM81@%x Rev: %d\n", adr, rev);
|
||||
/* The LM81 needs 400ms to get the correct values ... */
|
||||
udelay (400000);
|
||||
return 0;
|
||||
} /* _dtt_init() */
|
||||
|
||||
|
||||
int dtt_init (void)
|
||||
{
|
||||
int i;
|
||||
unsigned char sensors[] = CONFIG_DTT_SENSORS;
|
||||
const char *const header = "DTT: ";
|
||||
|
||||
for (i = 0; i < sizeof(sensors); i++) {
|
||||
if (_dtt_init(sensors[i]) != 0)
|
||||
printf("%s%d FAILED INIT\n", header, i+1);
|
||||
else
|
||||
printf("%s%d is %i C\n", header, i+1,
|
||||
dtt_get_temp(sensors[i]));
|
||||
}
|
||||
|
||||
return (0);
|
||||
} /* dtt_init() */
|
||||
|
||||
#define TEMP_FROM_REG(temp) \
|
||||
((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \
|
||||
((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \
|
||||
|
||||
int dtt_get_temp(int sensor)
|
||||
{
|
||||
int val = dtt_read (sensor, DTT_READ_TEMP);
|
||||
int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP);
|
||||
|
||||
return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
|
||||
} /* dtt_get_temp() */
|
||||
|
||||
#endif /* CONFIG_DTT_LM81 */
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2006
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||
#define CONFIG_UC101 1 /* UC101 board */
|
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DISPLAY | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_SNTP )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
|
||||
|
||||
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
|
||||
# define CFG_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addwdt=setenv bootargs ${bootargs} wdt=off" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x58
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
/* for LM81 */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CFG_I2C_RTC_ADDR 0x51
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFF800000
|
||||
|
||||
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
|
||||
#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
#define CFG_FLASH_CFI_AMD_RESET
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x10000
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xF0000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SRAM_BASE 0x80100000 /* CS 1 */
|
||||
#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
|
||||
#define CFG_IB_MASTER 0xc0510000 /* CS 6 */
|
||||
#define CFG_IB_EPLD 0xc0500000 /* CS 7 */
|
||||
|
||||
/* Settings for XLB = 132 MHz */
|
||||
#define SDRAM_DDR 1
|
||||
#define SDRAM_MODE 0x018D0000
|
||||
#define SDRAM_EMODE 0x40090000
|
||||
#define SDRAM_CONTROL 0x714f0f00
|
||||
#define SDRAM_CONFIG1 0x73722930
|
||||
#define SDRAM_CONFIG2 0x47770000
|
||||
#define SDRAM_TAPDELAY 0x10000000
|
||||
|
||||
/* SRAM */
|
||||
#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
|
||||
#define SRAM_LEN 0x1fffff
|
||||
#define SRAM_END (SRAM_BASE + SRAM_LEN)
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
#define CONFIG_MII 1
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define CFG_GPS_PORT_CONFIG 0x4d558044
|
||||
|
||||
/*use Hardware WDT */
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
#define CFG_MEMTEST_START 0x00300000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x300000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#if defined(CONFIG_MPC5200)
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
#else
|
||||
#define CFG_HID0_INIT 0
|
||||
#define CFG_HID0_FINAL 0
|
||||
#endif
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#define CFG_BOOTCS_CFG 0x00045D00
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
/* 8Mbit SRAM @0x80100000 */
|
||||
#define CFG_CS1_START CFG_SRAM_BASE
|
||||
#define CFG_CS1_SIZE 0x00100000
|
||||
#define CFG_CS1_CFG 0x21D00
|
||||
|
||||
/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
|
||||
#define CFG_CS3_START CFG_DISPLAY_BASE
|
||||
#define CFG_CS3_SIZE 0x00000100
|
||||
#define CFG_CS3_CFG 0x00081802
|
||||
|
||||
/* Interbus Master 16 Bit */
|
||||
#define CFG_CS6_START CFG_IB_MASTER
|
||||
#define CFG_CS6_SIZE 0x00010000
|
||||
#define CFG_CS6_CFG 0x00FF3500
|
||||
|
||||
/* Interbus EPLD 8 Bit */
|
||||
#define CFG_CS7_START CFG_IB_EPLD
|
||||
#define CFG_CS7_SIZE 0x00010000
|
||||
#define CFG_CS7_CFG 0x00081800
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333333
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_IDE_PREINIT 1
|
||||
/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (0x0060)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET (0x005C)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CFG_ATA_STRIDE 4
|
||||
|
||||
#define CONFIG_ATAPI 1
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* Display addresses */
|
||||
/*---------------------------------------------------------------------*/
|
||||
#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
|
||||
#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#if defined(CONFIG_DTT_LM75) || \
|
||||
defined(CONFIG_DTT_DS1621) || \
|
||||
defined(CONFIG_DTT_LM81) || \
|
||||
defined(CONFIG_DTT_ADM1021)
|
||||
|
||||
#define CONFIG_DTT /* We have a DTT */
|
||||
|
|
@ -58,6 +59,14 @@ extern int dtt_get_temp(int sensor);
|
|||
#define DTT_TEMP_SET 0x3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DTT_LM81)
|
||||
#define DTT_READ_TEMP 0x27
|
||||
#define DTT_CONFIG_TEMP 0x4b
|
||||
#define DTT_TEMP_MAX 0x39
|
||||
#define DTT_TEMP_HYST 0x3a
|
||||
#define DTT_CONFIG 0x40
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DTT_DS1621)
|
||||
#define DTT_READ_TEMP 0xAA
|
||||
#define DTT_READ_COUNTER 0xA8
|
||||
|
|
|
|||
Loading…
Reference in New Issue