Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Wolfgang Denk
commit
6c6e042ab3
25
MAINTAINERS
25
MAINTAINERS
|
|
@ -487,6 +487,10 @@ Rowel Atienza <rowel@diwalabs.com>
|
|||
|
||||
armadillo ARM720T
|
||||
|
||||
Dirk Behme <dirk.behme@gmail.com>
|
||||
|
||||
omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
|
||||
|
||||
Rishi Bhattacharya <rishi@ti.com>
|
||||
|
||||
omap5912osk ARM926EJS
|
||||
|
|
@ -527,6 +531,10 @@ Sascha Hauer <s.hauer@pengutronix.de>
|
|||
imx31_litekit i.MX31
|
||||
imx31_phycore i.MX31
|
||||
|
||||
Grazvydas Ignotas <notasas@gmail.com>
|
||||
|
||||
omap3_pandora ARM CORTEX-A8 (OMAP3xx SoC)
|
||||
|
||||
Gary Jennejohn <gj@denx.de>
|
||||
|
||||
smdk2400 ARM920T
|
||||
|
|
@ -554,6 +562,10 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
|||
mx31ads i.MX31
|
||||
SMDK6400 S3C6400
|
||||
|
||||
Nishanth Menon <nm@ti.com>
|
||||
|
||||
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
|
||||
|
||||
David Müller <d.mueller@elsoft.ch>
|
||||
|
||||
smdk2410 ARM920T
|
||||
|
|
@ -577,6 +589,10 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
|
|||
|
||||
omap730p2 ARM926EJS
|
||||
|
||||
Manikandan Pillai <mani.pillai@ti.com>
|
||||
|
||||
omap3_evm ARM CORTEX-A8 (OMAP3xx SoC)
|
||||
|
||||
Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
|
||||
at91cap9adk ARM926EJS (AT91CAP9 SoC)
|
||||
|
|
@ -591,6 +607,15 @@ Stefan Roese <sr@denx.de>
|
|||
pdnb3 xscale
|
||||
scpu xscale
|
||||
|
||||
Alessandro Rubini <rubini@unipv.it>
|
||||
Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
|
||||
|
||||
nmdk8815 ARM926EJS (Nomadik 8815 Soc)
|
||||
|
||||
Steve Sakoman <sakoman@gmail.com>
|
||||
|
||||
omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
|
||||
|
||||
Robert Schwebel <r.schwebel@pengutronix.de>
|
||||
|
||||
csb226 xscale
|
||||
|
|
|
|||
33
MAKEALL
33
MAKEALL
|
|
@ -502,6 +502,7 @@ LIST_ARM9=" \
|
|||
mx1ads \
|
||||
mx1fs2 \
|
||||
netstar \
|
||||
nmdk8815 \
|
||||
omap1510inn \
|
||||
omap1610h2 \
|
||||
omap1610inn \
|
||||
|
|
@ -544,6 +545,17 @@ LIST_ARM11=" \
|
|||
smdk6400 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ARM Cortex-A8 Systems
|
||||
#########################################################################
|
||||
LIST_ARM_CORTEX_A8=" \
|
||||
omap3_beagle \
|
||||
omap3_overo \
|
||||
omap3_evm \
|
||||
omap3_pandora \
|
||||
omap3_zoom1 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## AT91 Systems
|
||||
#########################################################################
|
||||
|
|
@ -598,15 +610,16 @@ LIST_ixp=" \
|
|||
## ARM groups
|
||||
#########################################################################
|
||||
|
||||
LIST_arm=" \
|
||||
${LIST_SA} \
|
||||
${LIST_ARM7} \
|
||||
${LIST_ARM9} \
|
||||
${LIST_ARM10} \
|
||||
${LIST_ARM11} \
|
||||
${LIST_at91} \
|
||||
${LIST_pxa} \
|
||||
${LIST_ixp} \
|
||||
LIST_arm=" \
|
||||
${LIST_SA} \
|
||||
${LIST_ARM7} \
|
||||
${LIST_ARM9} \
|
||||
${LIST_ARM10} \
|
||||
${LIST_ARM11} \
|
||||
${LIST_ARM_CORTEX_A8} \
|
||||
${LIST_at91} \
|
||||
${LIST_pxa} \
|
||||
${LIST_ixp} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -834,7 +847,7 @@ build_target() {
|
|||
for arg in $@
|
||||
do
|
||||
case "$arg" in
|
||||
arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \
|
||||
arm|SA|ARM7|ARM9|ARM10|ARM11|ARM_CORTEX_A8|at91|ixp|pxa \
|
||||
|avr32 \
|
||||
|blackfin \
|
||||
|coldfire \
|
||||
|
|
|
|||
54
Makefile
54
Makefile
|
|
@ -2716,7 +2716,7 @@ ap720t_config \
|
|||
ap920t_config \
|
||||
ap926ejs_config \
|
||||
ap946es_config: unconfig
|
||||
@board/integratorap/split_by_variant.sh $@
|
||||
@board/armltd/integratorap/split_by_variant.sh $@
|
||||
|
||||
integratorcp_config \
|
||||
cp_config \
|
||||
|
|
@ -2728,7 +2728,7 @@ cp966_config \
|
|||
cp922_config \
|
||||
cp922_XA10_config \
|
||||
cp1026_config: unconfig
|
||||
@board/integratorcp/split_by_variant.sh $@
|
||||
@board/armltd/integratorcp/split_by_variant.sh $@
|
||||
|
||||
davinci_dvevm_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
|
||||
|
|
@ -2755,6 +2755,18 @@ mx1fs2_config : unconfig
|
|||
netstar_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm925t netstar
|
||||
|
||||
nmdk8815_config \
|
||||
nmdk8815_onenand_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@ > $(obj)include/config.h
|
||||
@if [ "$(findstring _onenand, $@)" ] ; then \
|
||||
echo "#define CONFIG_BOOT_ONENAND" >> $(obj)include/config.h; \
|
||||
$(XECHO) "... configured for OneNand Flash"; \
|
||||
else \
|
||||
$(XECHO) "... configured for Nand Flash"; \
|
||||
fi
|
||||
@$(MKCONFIG) -a nmdk8815 arm arm926ejs nmdk8815 st nomadik
|
||||
|
||||
omap1510inn_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
|
||||
|
||||
|
|
@ -2806,13 +2818,22 @@ scb9328_config : unconfig
|
|||
@$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
|
||||
|
||||
smdk2400_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 NULL s3c24x0
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 samsung s3c24x0
|
||||
|
||||
smdk2410_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
|
||||
|
||||
SX1_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm925t sx1
|
||||
SX1_stdout_serial_config \
|
||||
SX1_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@if [ "$(findstring _stdout_serial_, $@)" ] ; then \
|
||||
echo "#undef CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
|
||||
$(XECHO) "... configured for stdout serial"; \
|
||||
else \
|
||||
echo "#define CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
|
||||
$(XECHO) "... configured for stdout usbtty"; \
|
||||
fi;
|
||||
@$(MKCONFIG) SX1 arm arm925t sx1
|
||||
|
||||
# TRAB default configuration: 8 MB Flash, 32 MB RAM
|
||||
xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))
|
||||
|
|
@ -2858,7 +2879,7 @@ cm41xx_config : unconfig
|
|||
versatile_config \
|
||||
versatileab_config \
|
||||
versatilepb_config : unconfig
|
||||
@board/versatile/split_by_variant.sh $@
|
||||
@board/armltd/versatile/split_by_variant.sh $@
|
||||
|
||||
voiceblue_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm925t voiceblue
|
||||
|
|
@ -2895,6 +2916,25 @@ lpc2292sodimm_config: unconfig
|
|||
SMN42_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
|
||||
|
||||
#########################################################################
|
||||
## ARM CORTEX Systems
|
||||
#########################################################################
|
||||
|
||||
omap3_beagle_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3
|
||||
|
||||
omap3_overo_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3
|
||||
|
||||
omap3_evm_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm omap3 omap3
|
||||
|
||||
omap3_pandora_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora omap3 omap3
|
||||
|
||||
omap3_zoom1_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
|
||||
|
||||
#########################################################################
|
||||
## XScale Systems
|
||||
#########################################################################
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
/integratorap/u-boot.lds
|
||||
/integratorcp/u-boot.lds
|
||||
|
|
@ -105,15 +105,15 @@ then
|
|||
fi
|
||||
|
||||
mkdir -p ${obj}include
|
||||
mkdir -p ${obj}board/integratorap
|
||||
mkdir -p ${obj}board/armltd/integratorap
|
||||
mv tmp.fil ${obj}include/config.h
|
||||
# ---------------------------------------------------------
|
||||
# Ensure correct core object loaded first in U-Boot image
|
||||
# ---------------------------------------------------------
|
||||
sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorap/u-boot.lds.template > ${obj}board/integratorap/u-boot.lds
|
||||
sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/armltd/integratorap/u-boot.lds.template > ${obj}board/armltd/integratorap/u-boot.lds
|
||||
# ---------------------------------------------------------
|
||||
# Complete the configuration
|
||||
# ---------------------------------------------------------
|
||||
$MKCONFIG -a integratorap arm $cpu integratorap;
|
||||
$MKCONFIG -a integratorap arm $cpu integratorap armltd;
|
||||
echo "Variant:: $variant with core $cpu"
|
||||
|
||||
|
|
@ -100,15 +100,15 @@ then
|
|||
fi
|
||||
|
||||
mkdir -p ${obj}include
|
||||
mkdir -p ${obj}board/integratorcp
|
||||
mkdir -p ${obj}board/armltd/integratorcp
|
||||
mv tmp.fil ${obj}include/config.h
|
||||
# ---------------------------------------------------------
|
||||
# Ensure correct core object loaded first in U-Boot image
|
||||
# ---------------------------------------------------------
|
||||
sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorcp/u-boot.lds.template > ${obj}board/integratorcp/u-boot.lds
|
||||
sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/armltd/integratorcp/u-boot.lds.template > ${obj}board/armltd/integratorcp/u-boot.lds
|
||||
# ---------------------------------------------------------
|
||||
# Complete the configuration
|
||||
# ---------------------------------------------------------
|
||||
$MKCONFIG -a integratorcp arm $cpu integratorcp;
|
||||
$MKCONFIG -a integratorcp arm $cpu integratorcp armltd;
|
||||
echo "Variant:: $variant with core $cpu"
|
||||
|
||||
|
|
@ -38,5 +38,5 @@ fi
|
|||
# ---------------------------------------------------------
|
||||
# Complete the configuration
|
||||
# ---------------------------------------------------------
|
||||
$MKCONFIG -a versatile arm arm926ejs versatile NULL versatile
|
||||
$MKCONFIG -a versatile arm arm926ejs versatile armltd versatile
|
||||
echo "Variant:: $variant"
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := beagle.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "beagle.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure board specific parts
|
||||
*****************************************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
|
||||
gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
|
||||
|
||||
power_init_r();
|
||||
|
||||
/* Configure GPIOs to output */
|
||||
writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
|
||||
writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
|
||||
|
||||
/* Set GPIOs */
|
||||
writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
|
||||
&gpio6_base->setdataout);
|
||||
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*****************************************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_BEAGLE();
|
||||
}
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Dirk Behme <dirk.behme@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _BEAGLE_H_
|
||||
#define _BEAGLE_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
SDP_3430_V1,
|
||||
SDP_3430_V2,
|
||||
DDR_STACKED,
|
||||
"3530",
|
||||
"OMAP3 Beagle board",
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
"OneNAND",
|
||||
#else
|
||||
"NAND",
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_BEAGLE() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/*Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
/*Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
|
||||
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
|
||||
/* USB EHCI (port 2) */\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Texas Instruments, <www.ti.com>
|
||||
#
|
||||
# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm_cortexa8/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(VENDOR).a
|
||||
|
||||
COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o
|
||||
COBJS-$(CONFIG_OMAP3_OVERO) += power.o
|
||||
COBJS-$(CONFIG_OMAP3_PANDORA) += power.o
|
||||
COBJS-$(CONFIG_OMAP3_ZOOM1) += power.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(LIB)
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: power_init_r
|
||||
* Description: Configure power supply
|
||||
*****************************************************************************/
|
||||
void power_init_r(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Configure OMAP3 supply voltages in power management
|
||||
* companion chip.
|
||||
*/
|
||||
|
||||
/* set VAUX3 to 2.8V */
|
||||
byte = DEV_GRP_P1;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1);
|
||||
byte = VAUX3_VSEL_28;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1);
|
||||
|
||||
/* set VPLL2 to 1.8V */
|
||||
byte = DEV_GRP_ALL;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1);
|
||||
byte = VPLL2_VSEL_18;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1);
|
||||
|
||||
/* set VDAC to 1.8V */
|
||||
byte = DEV_GRP_P1;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1);
|
||||
byte = VDAC_VSEL_18;
|
||||
i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1);
|
||||
|
||||
/* enable LED */
|
||||
byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
|
||||
i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := evm.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# (C) Copyright 2006 - 2008
|
||||
# Texas Instruments, <www.ti.com>
|
||||
#
|
||||
# EVM uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "evm.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Init ethernet (done here so udelay works)
|
||||
*****************************************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
setup_net_chip();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*****************************************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_EVM();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: setup_net_chip
|
||||
* Description: Setting up the configuration GPMC registers specific to the
|
||||
* Ethernet hardware.
|
||||
*****************************************************************************/
|
||||
static void setup_net_chip(void)
|
||||
{
|
||||
gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
|
||||
gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
|
||||
ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
|
||||
|
||||
/* Configure GPMC registers */
|
||||
writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
|
||||
writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
|
||||
writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
|
||||
writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
|
||||
writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
|
||||
writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
|
||||
writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
|
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
|
||||
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
|
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
|
||||
&ctrl_base->gpmc_nadv_ale);
|
||||
|
||||
/* Make GPIO 64 as output pin */
|
||||
writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
|
||||
|
||||
/* Now send a pulse on the GPIO pin */
|
||||
writel(GPIO0, &gpio3_base->setdataout);
|
||||
udelay(1);
|
||||
writel(GPIO0, &gpio3_base->cleardataout);
|
||||
udelay(1);
|
||||
writel(GPIO0, &gpio3_base->setdataout);
|
||||
}
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Nishanth Menon <menon.nishanth@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _EVM_H_
|
||||
#define _EVM_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
OMAP3EVM_V1,
|
||||
OMAP3EVM_V2,
|
||||
DDR_DISCRETE,
|
||||
"35X-Family",
|
||||
"OMAP3 EVM board",
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
"OneNAND",
|
||||
#else
|
||||
"NAND",
|
||||
#endif
|
||||
};
|
||||
|
||||
static void setup_net_chip(void);
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_EVM() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
|
||||
/* - ETH_nRESET*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
|
||||
/* - CAM_RESET*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/*Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
|
||||
/*Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
|
||||
/* - LCD_INI*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
|
||||
/* - LCD_ENVDD */\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
|
||||
/* - LCD_QVGA/nVGA */\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
|
||||
/* - LCD_RESB */\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
|
||||
/* RCTX*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
|
||||
/* TS_PEN_IRQ */\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
|
||||
/* - LAN_INTR*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
/* - PEN_IRQ */\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
/* - VIO_1V8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\
|
||||
/*Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm_cortexa8/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := overo.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#
|
||||
# Overo uses OMAP3 (ARM-CortexA8) cpu
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Maintainer : Steve Sakoman <steve@sakoman.com>
|
||||
*
|
||||
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "overo.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OVERO;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure board specific parts
|
||||
*****************************************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
|
||||
gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
|
||||
|
||||
power_init_r();
|
||||
|
||||
/* Configure GPIOs to output */
|
||||
writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe);
|
||||
writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
|
||||
|
||||
/* Set GPIOs */
|
||||
writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout);
|
||||
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
|
||||
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*****************************************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_OVERO();
|
||||
}
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Steve Sakoman <steve@sakoman.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _OVERO_H_
|
||||
#define _OVERO_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
SDP_3430_V1,
|
||||
SDP_3430_V2,
|
||||
DDR_STACKED,
|
||||
"3503",
|
||||
"Gumstix Overo board",
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
"OneNAND",
|
||||
#else
|
||||
"NAND",
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_OVERO() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
|
||||
/* - MMC1_WP*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*CAMERA*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\
|
||||
/*Audio Interface */\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/*Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/*Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
|
||||
/*Bluetooth*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
|
||||
MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
|
||||
/*Serial Interface*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
|
||||
/* BT_NRESET*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
/* - USBH_CPEN*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
/* - USBH_RESET*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
|
||||
/* - W2W_NRESET*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT7*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT6*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT5*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*HSUSB2_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
|
||||
/* die to die */\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm_cortexa8/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := pandora.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Texas Instruments, <www.ti.com>
|
||||
#
|
||||
# Pandora uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Grazvydas Ignotas <notasas@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "pandora.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure board specific parts
|
||||
*****************************************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
|
||||
gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
|
||||
gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
|
||||
gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
|
||||
|
||||
power_init_r();
|
||||
|
||||
/* Configure GPIOs to output */
|
||||
writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
|
||||
writel(~GPIO22, &gpio4_base->oe); /* 118 */
|
||||
writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31),
|
||||
&gpio5_base->oe); /* 128, 129, 156-159 */
|
||||
writel(~GPIO4, &gpio6_base->oe); /* 164 */
|
||||
|
||||
/* Set GPIOs */
|
||||
writel(GPIO28, &gpio5_base->setdataout);
|
||||
writel(GPIO4, &gpio6_base->setdataout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*****************************************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
MUX_PANDORA();
|
||||
}
|
||||
|
|
@ -0,0 +1,420 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Grazvydas Ignotas <notasas@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _PANDORA_H_
|
||||
#define _PANDORA_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
SDP_3430_V1,
|
||||
SDP_3430_V2,
|
||||
DDR_STACKED,
|
||||
"3530",
|
||||
"OMAP3 Pandora",
|
||||
"NAND",
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_PANDORA() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0))\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1))\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1))\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
/*DSS*/\
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
|
||||
/*GPIO based game buttons*/\
|
||||
MUX_VAL(CP(CAM_XCLKA), (IEN | PTU | DIS | M4)) /*GPIO_96 - LEFT*/\
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M4)) /*GPIO_97 - L2*/\
|
||||
MUX_VAL(CP(CAM_FLD), (IEN | PTU | DIS | M4)) /*GPIO_98 - RIGHT*/\
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTU | DIS | M4)) /*GPIO_99 - MENU*/\
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTU | DIS | M4)) /*GPIO_100 - START*/\
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTU | DIS | M4)) /*GPIO_101 - Y*/\
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTU | DIS | M4)) /*GPIO_102 - L1*/\
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTU | DIS | M4)) /*GPIO_103 - DOWN*/\
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTU | DIS | M4)) /*GPIO_104 - SELECT*/\
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTU | DIS | M4)) /*GPIO_105 - R1*/\
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTU | DIS | M4)) /*GPIO_106 - B*/\
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTU | DIS | M4)) /*GPIO_107 - R2*/\
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTU | DIS | M4)) /*GPIO_109 - X*/\
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTU | DIS | M4)) /*GPIO_110 - UP*/\
|
||||
MUX_VAL(CP(CAM_XCLKB), (IEN | PTU | DIS | M4)) /*GPIO_111 - A*/\
|
||||
/*Audio Interface To External DAC (Headphone, Speakers)*/\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\
|
||||
/* - nPOWERDOWN_DAC*/\
|
||||
/*Expansion card 1*/\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
|
||||
/*Expansion card 2*/\
|
||||
MUX_VAL(CP(MMC2_CLK), (IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
|
||||
/*SDIO Interface to WIFI Module*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CMD*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /*MMC3_DAT0*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /*MMC3_DAT1*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /*MMC3_DAT2*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /*MMC3_DAT3*/\
|
||||
/*Audio Interface To Bluetooth chip*/\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
|
||||
/*Digital Interface to Bluetooth (UART)*/\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M0)) /*UART1_CTS*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
/*Audio Interface to Triton2 chip (TPS65950)*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
|
||||
/*GPIO definitions for muxed pins on AV connector*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)) /*GPIO_144,*/\
|
||||
/*UART2_CTS*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTU | DIS | M4)) /*GPIO_145,*/\
|
||||
/*UART2_RTS*/\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTU | EN | M4)) /*GPIO_146,*/\
|
||||
/*UART2_TX*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147,*/\
|
||||
/*UART2_RX*/\
|
||||
/*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
|
||||
/*LEDs (Controlled by OMAP)*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
|
||||
/* - LED_MMC1*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\
|
||||
/* - LED_MMC2*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
|
||||
/* - LED_BT*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
|
||||
/* - LED_WIFI*/\
|
||||
/*Switches*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
|
||||
/* - nHOLD_SWITCH*/\
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTU | DIS | M4)) /*GPIO_108*/\
|
||||
/* - nLID_SWITCH*/\
|
||||
/*External IRQs*/\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M4)) /*GPIO_94*/\
|
||||
/* - nTOUCH_IRQ*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\
|
||||
/* - WIFI_IRQ*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
|
||||
/* - nIRQ_NUB1*/\
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTU | DIS | M4)) /*GPIO_167*/\
|
||||
/* - nIRQ_NUB2*/\
|
||||
/*Various other stuff*/\
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M4)) /*GPIO_95*/\
|
||||
/* - nTOUCH_BUSY*/\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\
|
||||
/* - nOC_USB5*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
|
||||
/* - START_ADC*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\
|
||||
/* - MSECURE*/\
|
||||
MUX_VAL(CP(CAM_STROBE), (IEN | PTU | DIS | M4)) /*GPIO_126*/\
|
||||
/* - HP_DETECT*/\
|
||||
/*External Resets and Enables*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\
|
||||
/* - nHDPHN_SHUTDOWN*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_15*/\
|
||||
/* - nBT_SHUTDOWN*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_23*/\
|
||||
/* - nWIFI_RESET*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157*/\
|
||||
/* - nLCD_RESET*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
|
||||
/* - RESET_NUBS*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164*/\
|
||||
/* - EN_USB_5V*/\
|
||||
/*Unused*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO - NC*/\
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0 - NC*/\
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0 - NC*/\
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1 - NC*/\
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1 - NC*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL - NC*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA - NC*/\
|
||||
/*HS USB OTG Port (connects to HSUSB0)*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
|
||||
/*I2C Ports*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL - T2_CTRL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA - T2_CTRL*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL - NUBS*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA - NUBS*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL - T2_SR*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA - T2_SR*/\
|
||||
/*Serial Interface (Touch, LCD control)*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0 - TOUCH*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTU | EN | M0)) /*McSPI1_CS1 - LCD*/\
|
||||
/*HS USB HOST Port (connects to HSUSB2)*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*USB_HOST_D6*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*USB_HOST_D7*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_16*/\
|
||||
/* - nRESET_USB_HOST*/\
|
||||
/*Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT1 - NC*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*SYS_CLKOUT2 - NC*/\
|
||||
/*JTAG*/\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
|
||||
/*Die to Die stuff*/\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm*/\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq*/\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm_cortexa8/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := zoom1.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# (C) Copyright 2006-2008
|
||||
# Texas Instruments, <www.ti.com>
|
||||
#
|
||||
# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
TEXT_BASE = 0x80e80000
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* January 2004 - Changed to support H4 device
|
||||
* Copyright (c) 2004-2008 Texas Instruments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm_cortexa8/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Nishanth Menon <nm@ti.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include "zoom1.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
*****************************************************************************/
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
|
||||
/* board id for Linux */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
|
||||
/* boot param addr */
|
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: misc_init_r
|
||||
* Description: Configure zoom board specific configurations
|
||||
*****************************************************************************/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
power_init_r();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: set_muxconf_regs
|
||||
* Description: Setting up the configuration Mux registers specific to the
|
||||
* hardware. Many pins need to be moved from protect to primary
|
||||
* mode.
|
||||
*****************************************************************************/
|
||||
void set_muxconf_regs(void)
|
||||
{
|
||||
/* platform specific muxes */
|
||||
MUX_ZOOM1_MDK();
|
||||
}
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments
|
||||
* Nishanth Menon <nm@ti.com>
|
||||
*
|
||||
* Derived from: board/omap3/beagle/beagle.h
|
||||
* Dirk Behme <dirk.behme@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _BOARD_ZOOM1_H_
|
||||
#define _BOARD_ZOOM1_H_
|
||||
|
||||
const omap3_sysinfo sysinfo = {
|
||||
SDP_3430_V1,
|
||||
SDP_3430_V2,
|
||||
DDR_STACKED,
|
||||
"3430",
|
||||
"OMAP3 Zoom MDK Rev 1",
|
||||
"NAND",
|
||||
};
|
||||
|
||||
/*
|
||||
* IEN - Input Enable
|
||||
* IDIS - Input Disable
|
||||
* PTD - Pull type Down
|
||||
* PTU - Pull type Up
|
||||
* DIS - Pull type selection is inactive
|
||||
* EN - Pull type selection is active
|
||||
* M0 - Mode 0
|
||||
* The commented string gives the final mux configuration for that pin
|
||||
*/
|
||||
#define MUX_ZOOM1_MDK() \
|
||||
/*SDRC*/\
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
|
||||
/*GPMC*/\
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
|
||||
MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
|
||||
|
||||
#endif /* _BOARD_ZOOM_H_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2004
|
||||
# ARM Ltd.
|
||||
# Philippe Robin, <philippe.robin@arm.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := nmdk8815.o
|
||||
SOBJS := platform.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# (C) Copyright 2007
|
||||
# STMicroelectronics, <www.st.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# image should be loaded at 0x01000000
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x03F80000
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* STMicrolelctronics, <www.st.com>
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* ARM Ltd.
|
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||
void show_boot_progress(int progress)
|
||||
{
|
||||
printf("%i\n", progress);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
|
||||
gd->bd->bi_boot_params = 0x00000100;
|
||||
writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
|
||||
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
|
||||
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
|
||||
writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
|
||||
|
||||
icache_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
setenv("verify", "n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* set dram bank start addr and size */
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* (C) Copyright 2005
|
||||
* STMicrolelctronics, <www.st.com>
|
||||
*
|
||||
* (C) Copyright 2004, ARM Ltd.
|
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* Jump to the flash address */
|
||||
ldr r0, =CFG_ONENAND_BASE
|
||||
|
||||
/*
|
||||
* Make it independent whether we boot from 0x0 or 0x30000000.
|
||||
* Non-portable: it relies on the knowledge that ip has to be updated
|
||||
*/
|
||||
orr ip, ip, r0 /* adjust return address of cpu_init_crit */
|
||||
orr lr, lr, r0 /* adjust return address */
|
||||
orr pc, pc, r0 /* jump to the normal address */
|
||||
nop
|
||||
|
||||
/* Initialize PLL, Remap clear, FSMC, MPMC here! */
|
||||
/* What about GPIO, CLCD and UART */
|
||||
|
||||
/* PLL Initialization */
|
||||
/* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
|
||||
ldr r0, =NOMADIK_SRC_BASE
|
||||
|
||||
ldr r1, =0x2B013502
|
||||
|
||||
str r1, [r0, #0x14]
|
||||
|
||||
/* Used to set all the timers clock to 2.4MHZ */
|
||||
ldr r1, =0x2AAAA004
|
||||
str r1, [r0]
|
||||
|
||||
ldr r1, =0x10000000
|
||||
str r1, [r0, #0x10]
|
||||
|
||||
/* FSMC setup ---- */
|
||||
ldr r0, =NOMADIK_FSMC_BASE
|
||||
|
||||
ldr r1, =0x10DB /* For 16-bit NOR flash */
|
||||
str r1, [r0, #0x08]
|
||||
|
||||
ldr r1, =0x03333333 /* For 16-bit NOR flash */
|
||||
str r1, [r0, #0xc]
|
||||
|
||||
/* oneNAND setting */
|
||||
ldr r1, =0x0000105B /* BCR0 Prog control register */
|
||||
str r1, [r0]
|
||||
|
||||
ldr r1, =0x0A200551 /* BTR0 Prog timing register */
|
||||
str r1, [r0, #0x04]
|
||||
|
||||
/* preload the instructions into icache */
|
||||
add r0, pc, #0x1F
|
||||
bic r0, r0, #0x1F
|
||||
mcr p15, 0, r0, c7, c13, 1
|
||||
add r0, r0, #0x20
|
||||
mcr p15, 0, r0, c7, c13, 1
|
||||
|
||||
/* Now Clear Remap */
|
||||
ldr r0, =NOMADIK_SRC_BASE
|
||||
|
||||
ldr r1, =0x2004
|
||||
str r1, [r0]
|
||||
|
||||
ldr r1, =0x10000000
|
||||
str r1, [r0, #0x10]
|
||||
|
||||
ldr r0, =0x101E9000
|
||||
ldr r1, =0x2004
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =NOMADIK_SRC_BASE
|
||||
ldr r1, =0x2104
|
||||
str r1, [r0]
|
||||
|
||||
/* FSMC setup -- */
|
||||
mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
|
||||
orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
|
||||
|
||||
ldr r1, =0x10DB /* For 16-bit NOR flash */
|
||||
str r1, [r0, #0x8]
|
||||
|
||||
ldr r1, =0x03333333 /* For 16-bit NOR flash */
|
||||
str r1, [r0, #0xc]
|
||||
|
||||
/* MPMC Setup */
|
||||
ldr r0, =NOMADIK_MPMC_BASE
|
||||
|
||||
ldr r1, =0xF00003
|
||||
str r1, [r0] /* Enable the MPMC and the DLL */
|
||||
|
||||
ldr r1, =0x183
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
ldr r2, =NOMADIK_PMU_BASE
|
||||
|
||||
ldr r1, =0x1111
|
||||
str r1, [r2]
|
||||
|
||||
ldr r1, =0x1111 /* Prog the, mand delay strategy */
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
ldr r1, =0x103 /* NOP ,mand */
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
/* FIXME -- Wait required here */
|
||||
|
||||
ldr r1, =0x103 /* PALL ,mand*/
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x24] /* To do at least two auto-refresh */
|
||||
|
||||
/* FIXME -- Wait required here */
|
||||
|
||||
/* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
|
||||
ldr r1, =0x31
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
/* Prog Little Endian, Not defined in 8800 board */
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x8]
|
||||
|
||||
|
||||
ldr r1, =0x2
|
||||
str r1, [r0, #0x30] /* Prog tRP timing */
|
||||
|
||||
ldr r1, =0x4 /* Change for 8815 */
|
||||
str r1, [r0, #0x34] /* Prog tRAS timing */
|
||||
|
||||
ldr r1, =0xB
|
||||
str r1, [r0, #0x38] /* Prog tSREX timing */
|
||||
|
||||
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x44] /* Prog tWR timing */
|
||||
|
||||
ldr r1, =0x8
|
||||
str r1, [r0, #0x48] /* Prog tRC timing */
|
||||
|
||||
ldr r1, =0xA
|
||||
str r1, [r0, #0x4C] /* Prog tRFC timing */
|
||||
|
||||
ldr r1, =0xB
|
||||
str r1, [r0, #0x50] /* Prog tXSR timing */
|
||||
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x54] /* Prog tRRD timing */
|
||||
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x58] /* Prog tMRD timing */
|
||||
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x5C] /* Prog tCDLR timing */
|
||||
|
||||
/* DDR-SDRAM MEMORY IS ON BANK0 8815 */
|
||||
ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */
|
||||
str r1, [r0, #0x104]
|
||||
|
||||
/* SDR-SDRAM MEMORY IS ON BANK1 8815 */
|
||||
ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */
|
||||
str r1, [r0, #0x124]
|
||||
/* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
|
||||
/* DDR-SDRAM MEMORY IS ON BANK0*/
|
||||
|
||||
ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */
|
||||
str r1, [r0, #0x100]
|
||||
|
||||
/*SDR-SDRAM MEMORY IS ON BANK1*/
|
||||
|
||||
ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */
|
||||
str r1, [r0, #0x120]
|
||||
|
||||
ldr r1, =0x83 /*MODE Mand*/
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
|
||||
|
||||
ldr r1, =0x62000 /*Data in*/
|
||||
ldr r1, [r1]
|
||||
|
||||
/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
|
||||
|
||||
ldr r1, =0x8062000
|
||||
ldr r1, [r1]
|
||||
|
||||
ldr r1, =0x003
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
/* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 0 */
|
||||
str r1, [r0, #0x400]
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 1 */
|
||||
str r1, [r0, #0x420]
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 2 */
|
||||
str r1, [r0, #0x440]
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 3 */
|
||||
str r1, [r0, #0x460]
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 4 */
|
||||
str r1, [r0, #0x480]
|
||||
|
||||
ldr r1, =0x01 /* Enable buffer 5 */
|
||||
str r1, [r0, #0x4A0]
|
||||
|
||||
/* GPIO settings */
|
||||
|
||||
ldr r0, =NOMADIK_GPIO1_BASE
|
||||
|
||||
ldr r1, =0xC0600000
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
ldr r0, =NOMADIK_GPIO0_BASE
|
||||
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #0x20]
|
||||
|
||||
ldr r1, =0x00
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
ldr r1, =0x00
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
/* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
|
||||
|
||||
ldr r0, =NOMADIK_FSMC_BASE
|
||||
|
||||
ldr r1, =0x10DB /* INIT FSMC bank 0 */
|
||||
str r1, [r0, #0x00]
|
||||
|
||||
ldr r1, =0x0FFFFFFF
|
||||
str r1, [r0, #0x04]
|
||||
|
||||
ldr r1, =0x010DB /* INIT FSMC bank 1 */
|
||||
str r1, [r0, #0x08]
|
||||
|
||||
ldr r1, =0x00FFFFFFF
|
||||
str r1, [r0, #0x0C]
|
||||
|
||||
ldr r0, =NOMADIK_UART0_BASE
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x0000004e
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
ldr r1, =0x00000060
|
||||
str r1, [r0, #0x2C]
|
||||
|
||||
ldr r1, =0x00000301
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x00000066
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =NOMADIK_UART1_BASE
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x0000004e
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
ldr r1, =0x00000060
|
||||
str r1, [r0, #0x2C]
|
||||
|
||||
ldr r1, =0x00000301
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x00000066
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =NOMADIK_UART2_BASE
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x0000004e
|
||||
str r1, [r0, #0x24]
|
||||
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x28]
|
||||
|
||||
ldr r1, =0x00000060
|
||||
str r1, [r0, #0x2C]
|
||||
|
||||
ldr r1, =0x00000301
|
||||
str r1, [r0, #0x30]
|
||||
|
||||
ldr r1, =0x00000066
|
||||
str r1, [r0]
|
||||
|
||||
/* Configure CPLD to enable UART0 */
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = timer.o
|
||||
SOBJS = reset.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#include <config.h>
|
||||
/*
|
||||
* Processor reset for Nomadik
|
||||
*/
|
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu:
|
||||
#if defined CONFIG_NOMADIK_8815
|
||||
ldr r0, =NOMADIK_SRC_BASE
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x18]
|
||||
#else
|
||||
ldr r1, rstctl1 /* get clkm1 reset ctl */
|
||||
mov r3, #0x0
|
||||
strh r3, [r1] /* clear it */
|
||||
mov r3, #0x8
|
||||
strh r3, [r1] /* force dsp+arm reset */
|
||||
#endif
|
||||
|
||||
_loop_forever:
|
||||
b _loop_forever
|
||||
|
||||
rstctl1:
|
||||
.word 0xfffece10
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Texas Instruments <www.ti.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002-2004
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <arm926ejs.h>
|
||||
|
||||
#define TIMER_LOAD_VAL 0xffffffff
|
||||
|
||||
/* macro to read the 32 bit timer */
|
||||
#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20)
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastdec;
|
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */
|
||||
int timer_init(void)
|
||||
{
|
||||
/* Load timer with initial value */
|
||||
writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16);
|
||||
|
||||
/*
|
||||
* Set timer to be enabled, free-running, no interrupts, 256 divider,
|
||||
* 32-bit, wrap-mode
|
||||
*/
|
||||
writel(0x8a, CONFIG_SYS_TIMERBASE + 24);
|
||||
|
||||
/* init the timestamp and lastdec value */
|
||||
reset_timer_masked();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
if (usec >= 1000) {
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else {
|
||||
/* small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000 * 1000);
|
||||
}
|
||||
|
||||
tmp = get_timer(0); /* get current timestamp */
|
||||
if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */
|
||||
reset_timer_masked(); /* reset to 0, set lastdec value */
|
||||
else
|
||||
tmo += tmp;
|
||||
|
||||
while (get_timer_masked() < tmo)
|
||||
/* nothing */ ;
|
||||
}
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time */
|
||||
lastdec = READ_TIMER; /* capure current decrementer value time */
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong now = READ_TIMER; /* current tick value */
|
||||
|
||||
if (lastdec >= now) { /* normal mode (non roll) */
|
||||
/* move stamp fordward */
|
||||
timestamp += lastdec - now;
|
||||
} else {
|
||||
/*
|
||||
* An overflow is expected.
|
||||
* nts = ts + ld + (TLV - now)
|
||||
* ts=old stamp, ld=time that passed before passing through -1
|
||||
* (TLV-now) amount of time after passing though -1
|
||||
* nts = new "advancing time stamp"...it could also roll
|
||||
*/
|
||||
timestamp += lastdec + TIMER_LOAD_VAL - now;
|
||||
}
|
||||
lastdec = now;
|
||||
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
/* waits specified delay value and resets timestamp */
|
||||
void udelay_masked(unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
|
||||
if (usec >= 1000) {
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000; /* start to normalize */
|
||||
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else {
|
||||
/* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000*1000);
|
||||
}
|
||||
|
||||
reset_timer_masked();
|
||||
/* set "advancing" timestamp to 0, set lastdec vaule */
|
||||
|
||||
while (get_timer_masked() < tmo)
|
||||
/* nothing */ ;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
ulong tbclk;
|
||||
|
||||
tbclk = CONFIG_SYS_HZ;
|
||||
return tbclk;
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(CPU).a
|
||||
|
||||
START := start.o
|
||||
COBJS := cpu.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
||||
all: $(obj).depend $(START) $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-msoft-float
|
||||
|
||||
# Make ARMv5 to allow more compilers to work, even though its v7a.
|
||||
PLATFORM_CPPFLAGS += -march=armv5
|
||||
# =========================================================================
|
||||
#
|
||||
# Supply options according to compiler version
|
||||
#
|
||||
# =========================================================================
|
||||
PLATFORM_CPPFLAGS +=$(call cc-option)
|
||||
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
|
||||
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
|
||||
$(call cc-option,-malignment-traps,))
|
||||
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* (C) Copyright 2008 Texas Insturments
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* CPU specific code
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L2_OFF
|
||||
void l2cache_disable(void);
|
||||
#endif
|
||||
|
||||
static void cache_flush(void);
|
||||
|
||||
/* read co-processor 15, register #1 (control register) */
|
||||
static unsigned long read_p15_c1(void)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
|
||||
@ read control reg\n":"=r"(value)
|
||||
::"memory");
|
||||
return value;
|
||||
}
|
||||
|
||||
/* write to co-processor 15, register #1 (control register) */
|
||||
static void write_p15_c1(unsigned long value)
|
||||
{
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
|
||||
@ write it back\n"::"r"(value)
|
||||
: "memory");
|
||||
|
||||
read_p15_c1();
|
||||
}
|
||||
|
||||
static void cp_delay(void)
|
||||
{
|
||||
/* Many OMAP regs need at least 2 nops */
|
||||
asm("nop");
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
/* See also ARM Ref. Man. */
|
||||
#define C1_MMU (1<<0) /* mmu off/on */
|
||||
#define C1_ALIGN (1<<1) /* alignment faults off/on */
|
||||
#define C1_DC (1<<2) /* dcache off/on */
|
||||
#define C1_WB (1<<3) /* merging write buffer on/off */
|
||||
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
|
||||
#define C1_SYS_PROT (1<<8) /* system protection */
|
||||
#define C1_ROM_PROT (1<<9) /* ROM protection */
|
||||
#define C1_IC (1<<12) /* icache off/on */
|
||||
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
|
||||
#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
|
||||
|
||||
int cpu_init(void)
|
||||
{
|
||||
/*
|
||||
* setup up stacks if necessary
|
||||
*/
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
IRQ_STACK_START =
|
||||
_armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
|
||||
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cleanup_before_linux(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/*
|
||||
* this function is called just before we call linux
|
||||
* it prepares the processor for linux
|
||||
*
|
||||
* we turn off caches etc ...
|
||||
*/
|
||||
disable_interrupts();
|
||||
|
||||
/* turn off I/D-cache */
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
|
||||
/* invalidate I-cache */
|
||||
cache_flush();
|
||||
|
||||
#ifndef CONFIG_L2_OFF
|
||||
/* turn off L2 cache */
|
||||
l2cache_disable();
|
||||
/* invalidate L2 cache also */
|
||||
v7_flush_dcache_all(get_device_type());
|
||||
#endif
|
||||
i = 0;
|
||||
/* mem barrier to sync up things */
|
||||
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
|
||||
|
||||
#ifndef CONFIG_L2_OFF
|
||||
l2cache_enable();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
disable_interrupts();
|
||||
reset_cpu(0);
|
||||
|
||||
/* NOTREACHED */
|
||||
return 0;
|
||||
}
|
||||
|
||||
void icache_enable(void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1(); /* get control reg. */
|
||||
cp_delay();
|
||||
write_p15_c1(reg | C1_IC);
|
||||
}
|
||||
|
||||
void icache_disable(void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1();
|
||||
cp_delay();
|
||||
write_p15_c1(reg & ~C1_IC);
|
||||
}
|
||||
|
||||
void dcache_disable (void)
|
||||
{
|
||||
ulong reg;
|
||||
|
||||
reg = read_p15_c1 ();
|
||||
cp_delay ();
|
||||
write_p15_c1 (reg & ~C1_DC);
|
||||
}
|
||||
|
||||
void l2cache_enable()
|
||||
{
|
||||
unsigned long i;
|
||||
volatile unsigned int j;
|
||||
|
||||
/* ES2 onwards we can disable/enable L2 ourselves */
|
||||
if (get_cpu_rev() == CPU_3430_ES2) {
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
} else {
|
||||
/* Save r0, r12 and restore them after usage */
|
||||
__asm__ __volatile__("mov %0, r12":"=r"(j));
|
||||
__asm__ __volatile__("mov %0, r0":"=r"(i));
|
||||
|
||||
/*
|
||||
* GP Device ROM code API usage here
|
||||
* r12 = AUXCR Write function and r0 value
|
||||
*/
|
||||
__asm__ __volatile__("mov r12, #0x3");
|
||||
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
|
||||
__asm__ __volatile__("orr r0, r0, #0x2");
|
||||
/* SMI instruction to call ROM Code API */
|
||||
__asm__ __volatile__(".word 0xE1600070");
|
||||
__asm__ __volatile__("mov r0, %0":"=r"(i));
|
||||
__asm__ __volatile__("mov r12, %0":"=r"(j));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void l2cache_disable()
|
||||
{
|
||||
unsigned long i;
|
||||
volatile unsigned int j;
|
||||
|
||||
/* ES2 onwards we can disable/enable L2 ourselves */
|
||||
if (get_cpu_rev() == CPU_3430_ES2) {
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
} else {
|
||||
/* Save r0, r12 and restore them after usage */
|
||||
__asm__ __volatile__("mov %0, r12":"=r"(j));
|
||||
__asm__ __volatile__("mov %0, r0":"=r"(i));
|
||||
|
||||
/*
|
||||
* GP Device ROM code API usage here
|
||||
* r12 = AUXCR Write function and r0 value
|
||||
*/
|
||||
__asm__ __volatile__("mov r12, #0x3");
|
||||
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
|
||||
__asm__ __volatile__("bic r0, r0, #0x2");
|
||||
/* SMI instruction to call ROM Code API */
|
||||
__asm__ __volatile__(".word 0xE1600070");
|
||||
__asm__ __volatile__("mov r0, %0":"=r"(i));
|
||||
__asm__ __volatile__("mov r12, %0":"=r"(j));
|
||||
}
|
||||
}
|
||||
|
||||
int icache_status(void)
|
||||
{
|
||||
return (read_p15_c1() & C1_IC) != 0;
|
||||
}
|
||||
|
||||
static void cache_flush(void)
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#
|
||||
# (C) Copyright 2000-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
SOBJS := lowlevel_init.o
|
||||
COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/*
|
||||
*
|
||||
* Common board functions for OMAP3 based boards.
|
||||
*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
|
||||
extern omap3_sysinfo sysinfo;
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: delay
|
||||
* Description: spinning delay to use before udelay works
|
||||
*****************************************************************************/
|
||||
static inline void delay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secure_unlock
|
||||
* Description: Setup security registers for access
|
||||
* (GP Device only)
|
||||
*****************************************************************************/
|
||||
void secure_unlock_mem(void)
|
||||
{
|
||||
pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
|
||||
pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
|
||||
pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
|
||||
pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
|
||||
sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
|
||||
|
||||
/* Protection Module Register Target APE (PM_RT) */
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
|
||||
writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
|
||||
|
||||
writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
|
||||
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
|
||||
writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
|
||||
|
||||
/* IVA Changes */
|
||||
writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
|
||||
|
||||
/* SDRC region 0 public */
|
||||
writel(UNLOCK_1, &sms_base->rg_att0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secureworld_exit()
|
||||
* Description: If chip is EMU and boot type is external
|
||||
* configure secure registers and exit secure world
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void secureworld_exit()
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
/* configrue non-secure access control register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
/* enabling co-processor CP10 and CP11 accesses in NS world */
|
||||
__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
|
||||
/*
|
||||
* allow allocation of locked TLBs and L2 lines in NS world
|
||||
* allow use of PLE registers in NS world also
|
||||
*/
|
||||
__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
|
||||
/* Enable ASA in ACR register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
|
||||
/* Exiting secure world */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: setup_auxcr()
|
||||
* Description: Write to AuxCR desired value using SMI.
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void setup_auxcr()
|
||||
{
|
||||
unsigned long i;
|
||||
volatile unsigned int j;
|
||||
/* Save r0, r12 and restore them after usage */
|
||||
__asm__ __volatile__("mov %0, r12":"=r"(j));
|
||||
__asm__ __volatile__("mov %0, r0":"=r"(i));
|
||||
|
||||
/*
|
||||
* GP Device ROM code API usage here
|
||||
* r12 = AUXCR Write function and r0 value
|
||||
*/
|
||||
__asm__ __volatile__("mov r12, #0x3");
|
||||
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
|
||||
/* Enabling ASA */
|
||||
__asm__ __volatile__("orr r0, r0, #0x10");
|
||||
/* Enable L1NEON */
|
||||
__asm__ __volatile__("orr r0, r0, #1 << 5");
|
||||
/* SMI instruction to call ROM Code API */
|
||||
__asm__ __volatile__(".word 0xE1600070");
|
||||
__asm__ __volatile__("mov r0, %0":"=r"(i));
|
||||
__asm__ __volatile__("mov r12, %0":"=r"(j));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: try_unlock_sram()
|
||||
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void try_unlock_memory()
|
||||
{
|
||||
int mode;
|
||||
int in_sdram = is_running_in_sdram();
|
||||
|
||||
/*
|
||||
* if GP device unlock device SRAM for general use
|
||||
* secure code breaks for Secure/Emulation device - HS/E/T
|
||||
*/
|
||||
mode = get_device_type();
|
||||
if (mode == GP_DEVICE)
|
||||
secure_unlock_mem();
|
||||
|
||||
/*
|
||||
* If device is EMU and boot is XIP external booting
|
||||
* Unlock firewalls and disable L2 and put chip
|
||||
* out of secure world
|
||||
*
|
||||
* Assuming memories are unlocked by the demon who put us in SDRAM
|
||||
*/
|
||||
if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
|
||||
&& (!in_sdram)) {
|
||||
secure_unlock_mem();
|
||||
secureworld_exit();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: s_init
|
||||
* Description: Does early system init of muxing and clocks.
|
||||
* - Called path is with SRAM stack.
|
||||
*****************************************************************************/
|
||||
void s_init(void)
|
||||
{
|
||||
int in_sdram = is_running_in_sdram();
|
||||
|
||||
watchdog_init();
|
||||
|
||||
try_unlock_memory();
|
||||
|
||||
/*
|
||||
* Right now flushing at low MPU speed.
|
||||
* Need to move after clock init
|
||||
*/
|
||||
v7_flush_dcache_all(get_device_type());
|
||||
#ifndef CONFIG_ICACHE_OFF
|
||||
icache_enable();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L2_OFF
|
||||
l2cache_disable();
|
||||
#else
|
||||
l2cache_enable();
|
||||
#endif
|
||||
/*
|
||||
* Writing to AuxCR in U-boot using SMI for GP DEV
|
||||
* Currently SMI in Kernel on ES2 devices seems to have an issue
|
||||
* Once that is resolved, we can postpone this config to kernel
|
||||
*/
|
||||
if (get_device_type() == GP_DEVICE)
|
||||
setup_auxcr();
|
||||
|
||||
set_muxconf_regs();
|
||||
delay(100);
|
||||
|
||||
prcm_init();
|
||||
|
||||
per_clocks_enable();
|
||||
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: wait_for_command_complete
|
||||
* Description: Wait for posting to finish on watchdog
|
||||
*****************************************************************************/
|
||||
void wait_for_command_complete(watchdog_t *wd_base)
|
||||
{
|
||||
int pending = 1;
|
||||
do {
|
||||
pending = readl(&wd_base->wwps);
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: watchdog_init
|
||||
* Description: Shut down watch dogs
|
||||
*****************************************************************************/
|
||||
void watchdog_init(void)
|
||||
{
|
||||
watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
|
||||
prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
|
||||
|
||||
/*
|
||||
* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
|
||||
* either taken care of by ROM (HS/EMU) or not accessible (GP).
|
||||
* We need to take care of WD2-MPU or take a PRCM reset. WD3
|
||||
* should not be running and does not generate a PRCM reset.
|
||||
*/
|
||||
|
||||
sr32(&prcm_base->fclken_wkup, 5, 1, 1);
|
||||
sr32(&prcm_base->iclken_wkup, 5, 1, 1);
|
||||
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
|
||||
|
||||
writel(WD_UNLOCK1, &wd2_base->wspr);
|
||||
wait_for_command_complete(wd2_base);
|
||||
writel(WD_UNLOCK2, &wd2_base->wspr);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: dram_init
|
||||
* Description: sets uboots idea of sdram size
|
||||
*****************************************************************************/
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
unsigned int size0 = 0, size1 = 0;
|
||||
u32 btype;
|
||||
|
||||
btype = get_board_type();
|
||||
|
||||
display_board_info(btype);
|
||||
|
||||
/*
|
||||
* If a second bank of DDR is attached to CS1 this is
|
||||
* where it can be started. Early init code will init
|
||||
* memory on CS0.
|
||||
*/
|
||||
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
|
||||
do_sdrc_init(CS1, NOT_EARLY);
|
||||
make_cs1_contiguous();
|
||||
}
|
||||
|
||||
size0 = get_sdr_cs_size(CS0);
|
||||
size1 = get_sdr_cs_size(CS1);
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = size0;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
|
||||
gd->bd->bi_dram[1].size = size1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Dummy function to handle errors for EABI incompatibility
|
||||
*****************************************************************************/
|
||||
void raise(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Dummy function to handle errors for EABI incompatibility
|
||||
*****************************************************************************/
|
||||
void abort(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NAND_OMAP_GPMC
|
||||
/******************************************************************************
|
||||
* OMAP3 specific command to switch between NAND HW and SW ecc
|
||||
*****************************************************************************/
|
||||
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (argc != 2)
|
||||
goto usage;
|
||||
if (strncmp(argv[1], "hw", 2) == 0)
|
||||
omap_nand_switch_ecc(1);
|
||||
else if (strncmp(argv[1], "sw", 2) == 0)
|
||||
omap_nand_switch_ecc(0);
|
||||
else
|
||||
goto usage;
|
||||
|
||||
return 0;
|
||||
|
||||
usage:
|
||||
printf ("Usage: nandecc %s\n", cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
nandecc, 2, 1, do_switch_ecc,
|
||||
"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
|
||||
"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
|
||||
);
|
||||
|
||||
#endif /* CONFIG_NAND_OMAP_GPMC */
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Derived from Beagle Board and OMAP3 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/arch/clocks_omap3.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <environment.h>
|
||||
#include <command.h>
|
||||
|
||||
/******************************************************************************
|
||||
* get_sys_clk_speed() - determine reference oscillator speed
|
||||
* based on known 32kHz clock and gptimer.
|
||||
*****************************************************************************/
|
||||
u32 get_osc_clk_speed(void)
|
||||
{
|
||||
u32 start, cstart, cend, cdiff, val;
|
||||
prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
|
||||
prm_t *prm_base = (prm_t *)PRM_BASE;
|
||||
gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
|
||||
s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
|
||||
|
||||
val = readl(&prm_base->clksrc_ctrl);
|
||||
|
||||
/* If SYS_CLK is being divided by 2, remove for now */
|
||||
val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
|
||||
writel(val, &prm_base->clksrc_ctrl);
|
||||
|
||||
/* enable timer2 */
|
||||
val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
|
||||
|
||||
/* select sys_clk for GPT1 */
|
||||
writel(val, &prcm_base->clksel_wkup);
|
||||
|
||||
/* Enable I and F Clocks for GPT1 */
|
||||
val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
|
||||
writel(val, &prcm_base->iclken_wkup);
|
||||
val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
|
||||
writel(val, &prcm_base->fclken_wkup);
|
||||
|
||||
writel(0, &gpt1_base->tldr); /* start counting at 0 */
|
||||
writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
|
||||
|
||||
/* enable 32kHz source, determine sys_clk via gauging */
|
||||
|
||||
/* start time in 20 cycles */
|
||||
start = 20 + readl(&s32k_base->s32k_cr);
|
||||
|
||||
/* dead loop till start time */
|
||||
while (readl(&s32k_base->s32k_cr) < start);
|
||||
|
||||
/* get start sys_clk count */
|
||||
cstart = readl(&gpt1_base->tcrr);
|
||||
|
||||
/* wait for 40 cycles */
|
||||
while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
|
||||
cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
|
||||
cdiff = cend - cstart; /* get elapsed ticks */
|
||||
|
||||
/* based on number of ticks assign speed */
|
||||
if (cdiff > 19000)
|
||||
return S38_4M;
|
||||
else if (cdiff > 15200)
|
||||
return S26M;
|
||||
else if (cdiff > 13000)
|
||||
return S24M;
|
||||
else if (cdiff > 9000)
|
||||
return S19_2M;
|
||||
else if (cdiff > 7600)
|
||||
return S13M;
|
||||
else
|
||||
return S12M;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
|
||||
* input oscillator clock frequency.
|
||||
*****************************************************************************/
|
||||
void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
|
||||
{
|
||||
switch(osc_clk) {
|
||||
case S38_4M:
|
||||
*sys_clkin_sel = 4;
|
||||
break;
|
||||
case S26M:
|
||||
*sys_clkin_sel = 3;
|
||||
break;
|
||||
case S19_2M:
|
||||
*sys_clkin_sel = 2;
|
||||
break;
|
||||
case S13M:
|
||||
*sys_clkin_sel = 1;
|
||||
break;
|
||||
case S12M:
|
||||
default:
|
||||
*sys_clkin_sel = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* prcm_init() - inits clocks for PRCM as defined in clocks.h
|
||||
* called from SRAM, or Flash (using temp SRAM stack).
|
||||
*****************************************************************************/
|
||||
void prcm_init(void)
|
||||
{
|
||||
void (*f_lock_pll) (u32, u32, u32, u32);
|
||||
int xip_safe, p0, p1, p2, p3;
|
||||
u32 osc_clk = 0, sys_clkin_sel;
|
||||
u32 clk_index, sil_index;
|
||||
prm_t *prm_base = (prm_t *)PRM_BASE;
|
||||
prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
|
||||
dpll_param *dpll_param_p;
|
||||
|
||||
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
|
||||
SRAM_VECT_CODE);
|
||||
|
||||
xip_safe = is_running_in_sram();
|
||||
|
||||
/*
|
||||
* Gauge the input clock speed and find out the sys_clkin_sel
|
||||
* value corresponding to the input clock.
|
||||
*/
|
||||
osc_clk = get_osc_clk_speed();
|
||||
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
|
||||
|
||||
/* set input crystal speed */
|
||||
sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
|
||||
|
||||
/* If the input clock is greater than 19.2M always divide/2 */
|
||||
if (sys_clkin_sel > 2) {
|
||||
/* input clock divider */
|
||||
sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
|
||||
clk_index = sys_clkin_sel / 2;
|
||||
} else {
|
||||
/* input clock divider */
|
||||
sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
|
||||
clk_index = sys_clkin_sel;
|
||||
}
|
||||
|
||||
/*
|
||||
* The DPLL tables are defined according to sysclk value and
|
||||
* silicon revision. The clk_index value will be used to get
|
||||
* the values for that input sysclk from the DPLL param table
|
||||
* and sil_index will get the values for that SysClk for the
|
||||
* appropriate silicon rev.
|
||||
*/
|
||||
sil_index = get_cpu_rev() - 1;
|
||||
|
||||
/* Unlock MPU DPLL (slows things down, and needed later) */
|
||||
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
|
||||
wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
|
||||
|
||||
/* Getting the base address of Core DPLL param table */
|
||||
dpll_param_p = (dpll_param *) get_core_dpll_param();
|
||||
|
||||
/* Moving it to the right sysclk and ES rev base */
|
||||
dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
|
||||
if (xip_safe) {
|
||||
/*
|
||||
* CORE DPLL
|
||||
* sr32(CM_CLKSEL2_EMU) set override to work when asleep
|
||||
*/
|
||||
sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
|
||||
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
|
||||
LDELAY);
|
||||
|
||||
/*
|
||||
* For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
|
||||
* work. write another value and then default value.
|
||||
*/
|
||||
|
||||
/* m3x2 */
|
||||
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
|
||||
/* m3x2 */
|
||||
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
|
||||
/* Set M2 */
|
||||
sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
|
||||
/* Set M */
|
||||
sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
|
||||
/* Set N */
|
||||
sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
|
||||
/* 96M Src */
|
||||
sr32(&prcm_base->clksel1_pll, 6, 1, 0);
|
||||
/* ssi */
|
||||
sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
|
||||
/* fsusb */
|
||||
sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
|
||||
/* l4 */
|
||||
sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
|
||||
/* l3 */
|
||||
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
|
||||
/* gfx */
|
||||
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
|
||||
/* reset mgr */
|
||||
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
|
||||
/* FREQSEL */
|
||||
sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
|
||||
/* lock mode */
|
||||
sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
|
||||
|
||||
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
|
||||
LDELAY);
|
||||
} else if (is_running_in_flash()) {
|
||||
/*
|
||||
* if running from flash, jump to small relocated code
|
||||
* area in SRAM.
|
||||
*/
|
||||
p0 = readl(&prcm_base->clken_pll);
|
||||
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
|
||||
sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
|
||||
|
||||
p1 = readl(&prcm_base->clksel1_pll);
|
||||
sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
|
||||
sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
|
||||
sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
|
||||
sr32(&p1, 6, 1, 0); /* set source for 96M */
|
||||
|
||||
p2 = readl(&prcm_base->clksel_core);
|
||||
sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
|
||||
sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
|
||||
sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
|
||||
sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
|
||||
|
||||
p3 = (u32)&prcm_base->idlest_ckgen;
|
||||
|
||||
(*f_lock_pll) (p0, p1, p2, p3);
|
||||
}
|
||||
|
||||
/* PER DPLL */
|
||||
sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
|
||||
wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
|
||||
|
||||
/* Getting the base address to PER DPLL param table */
|
||||
|
||||
/* Set N */
|
||||
dpll_param_p = (dpll_param *) get_per_dpll_param();
|
||||
|
||||
/* Moving it to the right sysclk base */
|
||||
dpll_param_p = dpll_param_p + clk_index;
|
||||
|
||||
/*
|
||||
* Errata 1.50 Workaround for OMAP3 ES1.0 only
|
||||
* If using default divisors, write default divisor + 1
|
||||
* and then the actual divisor value
|
||||
*/
|
||||
sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
|
||||
sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
|
||||
sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
|
||||
sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
|
||||
sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
|
||||
sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
|
||||
sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
|
||||
sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
|
||||
sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
|
||||
sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
|
||||
/* Workaround end */
|
||||
|
||||
sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
|
||||
sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
|
||||
sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
|
||||
sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
|
||||
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
|
||||
|
||||
/* Getting the base address to MPU DPLL param table */
|
||||
dpll_param_p = (dpll_param *) get_mpu_dpll_param();
|
||||
|
||||
/* Moving it to the right sysclk and ES rev base */
|
||||
dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
|
||||
|
||||
/* MPU DPLL (unlocked already) */
|
||||
|
||||
/* Set M2 */
|
||||
sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
|
||||
/* Set M */
|
||||
sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
|
||||
/* Set N */
|
||||
sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
|
||||
/* FREQSEL */
|
||||
sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
|
||||
/* lock mode */
|
||||
sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
|
||||
wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
|
||||
|
||||
/* Getting the base address to IVA DPLL param table */
|
||||
dpll_param_p = (dpll_param *) get_iva_dpll_param();
|
||||
|
||||
/* Moving it to the right sysclk and ES rev base */
|
||||
dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
|
||||
|
||||
/* IVA DPLL (set to 12*20=240MHz) */
|
||||
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
|
||||
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
|
||||
/* set M2 */
|
||||
sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
|
||||
/* set M */
|
||||
sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
|
||||
/* set N */
|
||||
sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
|
||||
/* FREQSEL */
|
||||
sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
|
||||
/* lock mode */
|
||||
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
|
||||
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
|
||||
|
||||
/* Set up GPTimers to sys_clk source only */
|
||||
sr32(&prcm_base->clksel_per, 0, 8, 0xff);
|
||||
sr32(&prcm_base->clksel_wkup, 0, 1, 1);
|
||||
|
||||
sdelay(5000);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
|
||||
*****************************************************************************/
|
||||
void per_clocks_enable(void)
|
||||
{
|
||||
prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
|
||||
|
||||
/* Enable GP2 timer. */
|
||||
sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
|
||||
sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
|
||||
sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
|
||||
|
||||
#ifdef CONFIG_SYS_NS16550
|
||||
/* Enable UART1 clocks */
|
||||
sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
|
||||
sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
|
||||
|
||||
/* UART 3 Clocks */
|
||||
sr32(&prcm_base->fclken_per, 11, 1, 0x1);
|
||||
sr32(&prcm_base->iclken_per, 11, 1, 0x1);
|
||||
#endif
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
/* Turn on all 3 I2C clocks */
|
||||
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
|
||||
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
|
||||
#endif
|
||||
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
|
||||
sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
|
||||
|
||||
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
|
||||
sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
|
||||
sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
|
||||
sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
|
||||
sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
|
||||
sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
|
||||
sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
|
||||
sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
|
||||
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
|
||||
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
|
||||
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
|
||||
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
|
||||
|
||||
sdelay(1000);
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-msoft-float
|
||||
|
||||
# Make ARMv5 to allow more compilers to work, even though its v7a.
|
||||
PLATFORM_CPPFLAGS += -march=armv5
|
||||
# =========================================================================
|
||||
#
|
||||
# Supply options according to compiler version
|
||||
#
|
||||
# =========================================================================
|
||||
PLATFORM_CPPFLAGS +=$(call cc-option)
|
||||
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
|
||||
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
|
||||
$(call cc-option,-malignment-traps,))
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Moahmmed Khasim <khasim@ti.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
#define TIMER_LOAD_VAL 0
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable IRQ interrupts */
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
unsigned long temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
|
||||
::"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts
|
||||
* returns true if interrupts had been enabled before we disabled them
|
||||
*/
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
unsigned long old, temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"orr %1, %0, #0xc0\n"
|
||||
"msr cpsr_c, %1":"=r"(old), "=r"(temp)
|
||||
::"memory");
|
||||
return (old & 0x80) == 0;
|
||||
}
|
||||
#else
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void bad_mode(void)
|
||||
{
|
||||
panic("Resetting CPU ...\n");
|
||||
reset_cpu(0);
|
||||
}
|
||||
|
||||
void show_regs(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
const char *processor_modes[] = {
|
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
|
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
|
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
|
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
|
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
|
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
|
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32",
|
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
|
||||
};
|
||||
|
||||
flags = condition_codes(regs);
|
||||
|
||||
printf("pc : [<%08lx>] lr : [<%08lx>]\n"
|
||||
"sp : %08lx ip : %08lx fp : %08lx\n",
|
||||
instruction_pointer(regs),
|
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
|
||||
printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
|
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
|
||||
printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
|
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
|
||||
printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
|
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
|
||||
printf("Flags: %c%c%c%c",
|
||||
flags & CC_N_BIT ? 'N' : 'n',
|
||||
flags & CC_Z_BIT ? 'Z' : 'z',
|
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
|
||||
printf(" IRQs %s FIQs %s Mode %s%s\n",
|
||||
interrupts_enabled(regs) ? "on" : "off",
|
||||
fast_interrupts_enabled(regs) ? "on" : "off",
|
||||
processor_modes[processor_mode(regs)],
|
||||
thumb_mode(regs) ? " (T)" : "");
|
||||
}
|
||||
|
||||
void do_undefined_instruction(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("undefined instruction\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_software_interrupt(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("software interrupt\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_prefetch_abort(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("prefetch abort\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_data_abort(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("data abort\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_not_used(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("not used\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_fiq(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("fast interrupt request\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_irq(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("interrupt request\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
|
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */
|
||||
int interrupt_init(void)
|
||||
{
|
||||
/* start the counter ticking up, reload value on overflow */
|
||||
writel(TIMER_LOAD_VAL, &timer_base->tldr);
|
||||
/* enable timer */
|
||||
writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
|
||||
&timer_base->tclr);
|
||||
|
||||
reset_timer_masked(); /* init the timestamp and lastinc value */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
if (usec >= 1000) {
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000;
|
||||
/* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else {/* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000 * 1000);
|
||||
}
|
||||
|
||||
tmp = get_timer(0); /* get current timestamp */
|
||||
/* if setting this forward will roll time stamp */
|
||||
if ((tmo + tmp + 1) < tmp)
|
||||
/* reset "advancing" timestamp to 0, set lastinc value */
|
||||
reset_timer_masked();
|
||||
else
|
||||
tmo += tmp; /* else, set advancing stamp wake up time */
|
||||
while (get_timer_masked() < tmo) /* loop till event */
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time, capture current incrementer value time */
|
||||
lastinc = readl(&timer_base->tcrr);
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong now = readl(&timer_base->tcrr); /* current tick value */
|
||||
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
/* move stamp fordward with absoulte diff ticks */
|
||||
timestamp += (now - lastinc);
|
||||
else /* we have rollover of incrementer */
|
||||
timestamp += (0xFFFFFFFF - lastinc) + now;
|
||||
lastinc = now;
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
/* waits specified delay value and resets timestamp */
|
||||
void udelay_masked(unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong endtime;
|
||||
signed long diff;
|
||||
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
if (usec >= 1000) {
|
||||
/* start to normalize for usec to ticks per sec */
|
||||
tmo = usec / 1000;
|
||||
/* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else { /* else small number, */
|
||||
/* don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000 * 1000);
|
||||
}
|
||||
endtime = get_timer_masked() + tmo;
|
||||
|
||||
do {
|
||||
ulong now = get_timer_masked();
|
||||
diff = endtime - now;
|
||||
} while (diff >= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
ulong tbclk;
|
||||
tbclk = CONFIG_SYS_HZ;
|
||||
return tbclk;
|
||||
}
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Initial Code by:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/clocks_omap3.h>
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE /* sdram load addr from config.mk */
|
||||
|
||||
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
|
||||
/**************************************************************************
|
||||
* cpy_clk_code: relocates clock code into SRAM where its safer to execute
|
||||
* R1 = SRAM destination address.
|
||||
*************************************************************************/
|
||||
.global cpy_clk_code
|
||||
cpy_clk_code:
|
||||
/* Copy DPLL code into SRAM */
|
||||
adr r0, go_to_speed /* get addr of clock setting code */
|
||||
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
|
||||
mov r1, r1 /* r1 <- dest address (passed in) */
|
||||
add r2, r2, r0 /* r2 <- source end address */
|
||||
next2:
|
||||
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3 - r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end address [r2] */
|
||||
bne next2
|
||||
mov pc, lr /* back to caller */
|
||||
|
||||
/* ***************************************************************************
|
||||
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
|
||||
* -executed from SRAM.
|
||||
* R0 = CM_CLKEN_PLL-bypass value
|
||||
* R1 = CM_CLKSEL1_PLL-m, n, and divider values
|
||||
* R2 = CM_CLKSEL_CORE-divider values
|
||||
* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
|
||||
*
|
||||
* Note: If core unlocks/relocks and SDRAM is running fast already it gets
|
||||
* confused. A reset of the controller gets it back. Taking away its
|
||||
* L3 when its not in self refresh seems bad for it. Normally, this
|
||||
* code runs from flash before SDR is init so that should be ok.
|
||||
****************************************************************************/
|
||||
.global go_to_speed
|
||||
go_to_speed:
|
||||
stmfd sp!, {r4 - r6}
|
||||
|
||||
/* move into fast relock bypass */
|
||||
ldr r4, pll_ctl_add
|
||||
str r0, [r4]
|
||||
wait1:
|
||||
ldr r5, [r3] /* get status */
|
||||
and r5, r5, #0x1 /* isolate core status */
|
||||
cmp r5, #0x1 /* still locked? */
|
||||
beq wait1 /* if lock, loop */
|
||||
|
||||
/* set new dpll dividers _after_ in bypass */
|
||||
ldr r5, pll_div_add1
|
||||
str r1, [r5] /* set m, n, m2 */
|
||||
ldr r5, pll_div_add2
|
||||
str r2, [r5] /* set l3/l4/.. dividers*/
|
||||
ldr r5, pll_div_add3 /* wkup */
|
||||
ldr r2, pll_div_val3 /* rsm val */
|
||||
str r2, [r5]
|
||||
ldr r5, pll_div_add4 /* gfx */
|
||||
ldr r2, pll_div_val4
|
||||
str r2, [r5]
|
||||
ldr r5, pll_div_add5 /* emu */
|
||||
ldr r2, pll_div_val5
|
||||
str r2, [r5]
|
||||
|
||||
/* now prepare GPMC (flash) for new dpll speed */
|
||||
/* flash needs to be stable when we jump back to it */
|
||||
ldr r5, flash_cfg3_addr
|
||||
ldr r2, flash_cfg3_val
|
||||
str r2, [r5]
|
||||
ldr r5, flash_cfg4_addr
|
||||
ldr r2, flash_cfg4_val
|
||||
str r2, [r5]
|
||||
ldr r5, flash_cfg5_addr
|
||||
ldr r2, flash_cfg5_val
|
||||
str r2, [r5]
|
||||
ldr r5, flash_cfg1_addr
|
||||
ldr r2, [r5]
|
||||
orr r2, r2, #0x3 /* up gpmc divider */
|
||||
str r2, [r5]
|
||||
|
||||
/* lock DPLL3 and wait a bit */
|
||||
orr r0, r0, #0x7 /* set up for lock mode */
|
||||
str r0, [r4] /* lock */
|
||||
nop /* ARM slow at this point working at sys_clk */
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
wait2:
|
||||
ldr r5, [r3] /* get status */
|
||||
and r5, r5, #0x1 /* isolate core status */
|
||||
cmp r5, #0x1 /* still locked? */
|
||||
bne wait2 /* if lock, loop */
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
ldmfd sp!, {r4 - r6}
|
||||
mov pc, lr /* back to caller, locked */
|
||||
|
||||
_go_to_speed: .word go_to_speed
|
||||
|
||||
/* these constants need to be close for PIC code */
|
||||
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
|
||||
flash_cfg1_addr:
|
||||
.word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
|
||||
flash_cfg3_addr:
|
||||
.word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
|
||||
flash_cfg3_val:
|
||||
.word STNOR_GPMC_CONFIG3
|
||||
flash_cfg4_addr:
|
||||
.word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
|
||||
flash_cfg4_val:
|
||||
.word STNOR_GPMC_CONFIG4
|
||||
flash_cfg5_val:
|
||||
.word STNOR_GPMC_CONFIG5
|
||||
flash_cfg5_addr:
|
||||
.word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
|
||||
pll_ctl_add:
|
||||
.word CM_CLKEN_PLL
|
||||
pll_div_add1:
|
||||
.word CM_CLKSEL1_PLL
|
||||
pll_div_add2:
|
||||
.word CM_CLKSEL_CORE
|
||||
pll_div_add3:
|
||||
.word CM_CLKSEL_WKUP
|
||||
pll_div_val3:
|
||||
.word (WKUP_RSM << 1)
|
||||
pll_div_add4:
|
||||
.word CM_CLKSEL_GFX
|
||||
pll_div_val4:
|
||||
.word (GFX_DIV << 0)
|
||||
pll_div_add5:
|
||||
.word CM_CLKSEL1_EMU
|
||||
pll_div_val5:
|
||||
.word CLSEL1_EMU_VAL
|
||||
|
||||
#endif
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
ldr sp, SRAM_STACK
|
||||
str ip, [sp] /* stash old link register */
|
||||
mov ip, lr /* save link reg across call */
|
||||
bl s_init /* go setup pll, mux, memory */
|
||||
ldr ip, [sp] /* restore save ip */
|
||||
mov lr, ip /* restore link reg */
|
||||
|
||||
/* back to arch calling code */
|
||||
mov pc, lr
|
||||
|
||||
/* the literal pools origin */
|
||||
.ltorg
|
||||
|
||||
REG_CONTROL_STATUS:
|
||||
.word CONTROL_STATUS
|
||||
SRAM_STACK:
|
||||
.word LOW_LEVEL_SRAM_STACK
|
||||
|
||||
/* DPLL(1-4) PARAM TABLES */
|
||||
|
||||
/*
|
||||
* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
|
||||
* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
|
||||
* The values are defined for all possible sysclk and for ES1 and ES2.
|
||||
*/
|
||||
|
||||
mpu_dpll_param:
|
||||
/* 12MHz */
|
||||
/* ES1 */
|
||||
.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
|
||||
/* ES2 */
|
||||
.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
|
||||
/* 3410 */
|
||||
.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
|
||||
|
||||
/* 13MHz */
|
||||
/* ES1 */
|
||||
.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
|
||||
/* ES2 */
|
||||
.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
|
||||
/* 3410 */
|
||||
.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
|
||||
|
||||
/* 19.2MHz */
|
||||
/* ES1 */
|
||||
.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
|
||||
/* ES2 */
|
||||
.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
|
||||
/* 3410 */
|
||||
.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
|
||||
|
||||
/* 26MHz */
|
||||
/* ES1 */
|
||||
.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
|
||||
/* ES2 */
|
||||
.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
|
||||
/* 3410 */
|
||||
.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
|
||||
|
||||
/* 38.4MHz */
|
||||
/* ES1 */
|
||||
.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
|
||||
/* ES2 */
|
||||
.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
|
||||
/* 3410 */
|
||||
.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
|
||||
|
||||
|
||||
.globl get_mpu_dpll_param
|
||||
get_mpu_dpll_param:
|
||||
adr r0, mpu_dpll_param
|
||||
mov pc, lr
|
||||
|
||||
iva_dpll_param:
|
||||
/* 12MHz */
|
||||
/* ES1 */
|
||||
.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
|
||||
/* ES2 */
|
||||
.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
|
||||
/* 3410 */
|
||||
.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
|
||||
|
||||
/* 13MHz */
|
||||
/* ES1 */
|
||||
.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
|
||||
/* ES2 */
|
||||
.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
|
||||
/* 3410 */
|
||||
.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
|
||||
|
||||
/* 19.2MHz */
|
||||
/* ES1 */
|
||||
.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
|
||||
/* ES2 */
|
||||
.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
|
||||
/* 3410 */
|
||||
.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
|
||||
|
||||
/* 26MHz */
|
||||
/* ES1 */
|
||||
.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
|
||||
/* ES2 */
|
||||
.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
|
||||
/* 3410 */
|
||||
.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
|
||||
|
||||
/* 38.4MHz */
|
||||
/* ES1 */
|
||||
.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
|
||||
/* ES2 */
|
||||
.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
|
||||
/* 3410 */
|
||||
.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
|
||||
|
||||
|
||||
.globl get_iva_dpll_param
|
||||
get_iva_dpll_param:
|
||||
adr r0, iva_dpll_param
|
||||
mov pc, lr
|
||||
|
||||
/* Core DPLL targets for L3 at 166 & L133 */
|
||||
core_dpll_param:
|
||||
/* 12MHz */
|
||||
/* ES1 */
|
||||
.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
|
||||
/* ES2 */
|
||||
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
|
||||
/* 3410 */
|
||||
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
|
||||
|
||||
/* 13MHz */
|
||||
/* ES1 */
|
||||
.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
|
||||
/* ES2 */
|
||||
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
|
||||
/* 3410 */
|
||||
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
|
||||
|
||||
/* 19.2MHz */
|
||||
/* ES1 */
|
||||
.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
|
||||
/* ES2 */
|
||||
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
|
||||
/* 3410 */
|
||||
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
|
||||
|
||||
/* 26MHz */
|
||||
/* ES1 */
|
||||
.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
|
||||
/* ES2 */
|
||||
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
|
||||
/* 3410 */
|
||||
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
|
||||
|
||||
/* 38.4MHz */
|
||||
/* ES1 */
|
||||
.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
|
||||
/* ES2 */
|
||||
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
|
||||
/* 3410 */
|
||||
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
|
||||
|
||||
.globl get_core_dpll_param
|
||||
get_core_dpll_param:
|
||||
adr r0, core_dpll_param
|
||||
mov pc, lr
|
||||
|
||||
/* PER DPLL values are same for both ES1 and ES2 */
|
||||
per_dpll_param:
|
||||
/* 12MHz */
|
||||
.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
|
||||
|
||||
/* 13MHz */
|
||||
.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
|
||||
|
||||
/* 19.2MHz */
|
||||
.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
|
||||
|
||||
/* 26MHz */
|
||||
.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
|
||||
|
||||
/* 38.4MHz */
|
||||
.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
|
||||
|
||||
.globl get_per_dpll_param
|
||||
get_per_dpll_param:
|
||||
adr r0, per_dpll_param
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Initial Code from:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <command.h>
|
||||
|
||||
/*
|
||||
* Only One NAND allowed on board at a time.
|
||||
* The GPMC CS Base for the same
|
||||
*/
|
||||
unsigned int boot_flash_base;
|
||||
unsigned int boot_flash_off;
|
||||
unsigned int boot_flash_sec;
|
||||
unsigned int boot_flash_type;
|
||||
volatile unsigned int boot_flash_env_addr;
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
static u32 gpmc_m_nand[GPMC_MAX_REG] = {
|
||||
M_NAND_GPMC_CONFIG1,
|
||||
M_NAND_GPMC_CONFIG2,
|
||||
M_NAND_GPMC_CONFIG3,
|
||||
M_NAND_GPMC_CONFIG4,
|
||||
M_NAND_GPMC_CONFIG5,
|
||||
M_NAND_GPMC_CONFIG6, 0
|
||||
};
|
||||
|
||||
gpmc_csx_t *nand_cs_base;
|
||||
gpmc_t *gpmc_cfg_base;
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#define GPMC_CS 0
|
||||
#else
|
||||
#define GPMC_CS 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_ONENAND)
|
||||
static u32 gpmc_onenand[GPMC_MAX_REG] = {
|
||||
ONENAND_GPMC_CONFIG1,
|
||||
ONENAND_GPMC_CONFIG2,
|
||||
ONENAND_GPMC_CONFIG3,
|
||||
ONENAND_GPMC_CONFIG4,
|
||||
ONENAND_GPMC_CONFIG5,
|
||||
ONENAND_GPMC_CONFIG6, 0
|
||||
};
|
||||
|
||||
gpmc_csx_t *onenand_cs_base;
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
#define GPMC_CS 0
|
||||
#else
|
||||
#define GPMC_CS 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
|
||||
|
||||
/**************************************************************************
|
||||
* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
|
||||
* command line mem=xyz use all memory with out discontinuous support
|
||||
* compiled in. Could do it at the ATAG, but there really is two banks...
|
||||
* Called as part of 2nd phase DDR init.
|
||||
**************************************************************************/
|
||||
void make_cs1_contiguous(void)
|
||||
{
|
||||
u32 size, a_add_low, a_add_high;
|
||||
|
||||
size = get_sdr_cs_size(CS0);
|
||||
size /= SZ_32M; /* find size to offset CS1 */
|
||||
a_add_high = (size & 3) << 8; /* set up low field */
|
||||
a_add_low = (size & 0x3C) >> 2; /* set up high field */
|
||||
writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
|
||||
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* mem_ok() - test used to see if timings are correct
|
||||
* for a part. Helps in guessing which part
|
||||
* we are currently using.
|
||||
*******************************************************/
|
||||
u32 mem_ok(u32 cs)
|
||||
{
|
||||
u32 val1, val2, addr;
|
||||
u32 pattern = 0x12345678;
|
||||
|
||||
addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
|
||||
|
||||
writel(0x0, addr + 0x400); /* clear pos A */
|
||||
writel(pattern, addr); /* pattern to pos B */
|
||||
writel(0x0, addr + 4); /* remove pattern off the bus */
|
||||
val1 = readl(addr + 0x400); /* get pos A value */
|
||||
val2 = readl(addr); /* get val2 */
|
||||
|
||||
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* sdrc_init() - init the sdrc chip selects CS0 and CS1
|
||||
* - early init routines, called from flash or
|
||||
* SRAM.
|
||||
*******************************************************/
|
||||
void sdrc_init(void)
|
||||
{
|
||||
/* only init up first bank here */
|
||||
do_sdrc_init(CS0, EARLY_INIT);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* do_sdrc_init(): initialize the SDRAM for use.
|
||||
* -code sets up SDRAM basic SDRC timings for CS0
|
||||
* -optimal settings can be placed here, or redone after i2c
|
||||
* inspection of board info
|
||||
*
|
||||
* - code called once in C-Stack only context for CS0 and a possible 2nd
|
||||
* time depending on memory configuration from stack+global context
|
||||
**************************************************************************/
|
||||
|
||||
void do_sdrc_init(u32 cs, u32 early)
|
||||
{
|
||||
sdrc_actim_t *sdrc_actim_base;
|
||||
|
||||
if(cs)
|
||||
sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
|
||||
else
|
||||
sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
|
||||
|
||||
if (early) {
|
||||
/* reset sdrc controller */
|
||||
writel(SOFTRESET, &sdrc_base->sysconfig);
|
||||
wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
|
||||
12000000);
|
||||
writel(0, &sdrc_base->sysconfig);
|
||||
|
||||
/* setup sdrc to ball mux */
|
||||
writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
|
||||
|
||||
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
|
||||
writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
|
||||
|
||||
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
|
||||
sdelay(0x20000);
|
||||
}
|
||||
|
||||
writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
|
||||
RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
|
||||
DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
|
||||
writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
|
||||
writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
|
||||
writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
|
||||
|
||||
writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
|
||||
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
|
||||
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
|
||||
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
|
||||
|
||||
/*
|
||||
* CAS latency 3, Write Burst = Read Burst, Serial Mode,
|
||||
* Burst length = 4
|
||||
*/
|
||||
writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
|
||||
|
||||
if (!mem_ok(cs))
|
||||
writel(0, &sdrc_base->cs[cs].mcfg);
|
||||
}
|
||||
|
||||
void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base,
|
||||
u32 size)
|
||||
{
|
||||
writel(0, &gpmc_cs_base->config7);
|
||||
sdelay(1000);
|
||||
/* Delay for settling */
|
||||
writel(gpmc_config[0], &gpmc_cs_base->config1);
|
||||
writel(gpmc_config[1], &gpmc_cs_base->config2);
|
||||
writel(gpmc_config[2], &gpmc_cs_base->config3);
|
||||
writel(gpmc_config[3], &gpmc_cs_base->config4);
|
||||
writel(gpmc_config[4], &gpmc_cs_base->config5);
|
||||
writel(gpmc_config[5], &gpmc_cs_base->config6);
|
||||
/* Enable the config */
|
||||
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
|
||||
(1 << 6)), &gpmc_cs_base->config7);
|
||||
sdelay(2000);
|
||||
}
|
||||
|
||||
/*****************************************************
|
||||
* gpmc_init(): init gpmc bus
|
||||
* Init GPMC for x16, MuxMode (SDRAM in x32).
|
||||
* This code can only be executed from SRAM or SDRAM.
|
||||
*****************************************************/
|
||||
void gpmc_init(void)
|
||||
{
|
||||
/* putting a blanket check on GPMC based on ZeBu for now */
|
||||
u32 *gpmc_config = NULL;
|
||||
gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
|
||||
gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
|
||||
u32 base = 0;
|
||||
u32 size = 0;
|
||||
u32 f_off = CONFIG_SYS_MONITOR_LEN;
|
||||
u32 f_sec = 0;
|
||||
u32 config = 0;
|
||||
|
||||
/* global settings */
|
||||
writel(0, &gpmc_base->irqenable); /* isr's sources masked */
|
||||
writel(0, &gpmc_base->timeout_control);/* timeout disable */
|
||||
|
||||
config = readl(&gpmc_base->config);
|
||||
config &= (~0xf00);
|
||||
writel(config, &gpmc_base->config);
|
||||
|
||||
/*
|
||||
* Disable the GPMC0 config set by ROM code
|
||||
* It conflicts with our MPDB (both at 0x08000000)
|
||||
*/
|
||||
writel(0, &gpmc_cs_base->config7);
|
||||
sdelay(1000);
|
||||
|
||||
#if defined(CONFIG_CMD_NAND) /* CS 0 */
|
||||
gpmc_config = gpmc_m_nand;
|
||||
gpmc_cfg_base = gpmc_base;
|
||||
nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
|
||||
(GPMC_CS * GPMC_CONFIG_WIDTH));
|
||||
base = PISMO1_NAND_BASE;
|
||||
size = PISMO1_NAND_SIZE;
|
||||
enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
|
||||
#if defined(CONFIG_ENV_IS_IN_NAND)
|
||||
f_off = SMNAND_ENV_OFFSET;
|
||||
f_sec = SZ_128K;
|
||||
/* env setup */
|
||||
boot_flash_base = base;
|
||||
boot_flash_off = f_off;
|
||||
boot_flash_sec = f_sec;
|
||||
boot_flash_env_addr = f_off;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_ONENAND)
|
||||
gpmc_config = gpmc_onenand;
|
||||
onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
|
||||
(GPMC_CS * GPMC_CONFIG_WIDTH));
|
||||
base = PISMO1_ONEN_BASE;
|
||||
size = PISMO1_ONEN_SIZE;
|
||||
enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
|
||||
#if defined(CONFIG_ENV_IS_IN_ONENAND)
|
||||
f_off = ONENAND_ENV_OFFSET;
|
||||
f_sec = SZ_128K;
|
||||
/* env setup */
|
||||
boot_flash_base = base;
|
||||
boot_flash_off = f_off;
|
||||
boot_flash_sec = f_sec;
|
||||
boot_flash_env_addr = f_off;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h> /* get mem tables */
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
|
||||
extern omap3_sysinfo sysinfo;
|
||||
static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
|
||||
static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
|
||||
static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
|
||||
|
||||
/******************************************
|
||||
* get_cpu_rev(void) - extract version info
|
||||
******************************************/
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 cpuid = 0;
|
||||
|
||||
/*
|
||||
* On ES1.0 the IDCODE register is not exposed on L4
|
||||
* so using CPU ID to differentiate
|
||||
* between ES2.0 and ES1.0.
|
||||
*/
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
|
||||
if ((cpuid & 0xf) == 0x0)
|
||||
return CPU_3430_ES1;
|
||||
else
|
||||
return CPU_3430_ES2;
|
||||
|
||||
}
|
||||
|
||||
/****************************************************
|
||||
* is_mem_sdr() - return 1 if mem type in use is SDR
|
||||
****************************************************/
|
||||
u32 is_mem_sdr(void)
|
||||
{
|
||||
if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_cs0_size() - get size of chip select 0/1
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_size(u32 cs)
|
||||
{
|
||||
u32 size;
|
||||
|
||||
/* get ram size field */
|
||||
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
|
||||
size &= 0x3FF; /* remove unwanted bits */
|
||||
size *= SZ_2M; /* find size in MB */
|
||||
return size;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_sdr_cs_offset() - get offset of cs from cs0 start
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_offset(u32 cs)
|
||||
{
|
||||
u32 offset;
|
||||
|
||||
if (!cs)
|
||||
return 0;
|
||||
|
||||
offset = readl(&sdrc_base->cs_cfg);
|
||||
offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_board_type() - get board type based on current production stats.
|
||||
* - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
|
||||
* when they are available we can get info from there. This should
|
||||
* be correct of all known boards up until today.
|
||||
* - NOTE-2- EEPROMs are populated but they are updated very slowly. To
|
||||
* avoid waiting on them we will use ES version of the chip to get info.
|
||||
* A later version of the FPGA migth solve their speed issue.
|
||||
************************************************************************/
|
||||
u32 get_board_type(void)
|
||||
{
|
||||
if (get_cpu_rev() == CPU_3430_ES2)
|
||||
return sysinfo.board_type_v2;
|
||||
else
|
||||
return sysinfo.board_type_v1;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* get_gpmc0_base() - Return current address hardware will be
|
||||
* fetching from. The below effectively gives what is correct, its a bit
|
||||
* mis-leading compared to the TRM. For the most general case the mask
|
||||
* needs to be also taken into account this does work in practice.
|
||||
* - for u-boot we currently map:
|
||||
* -- 0 to nothing,
|
||||
* -- 4 to flash
|
||||
* -- 8 to enent
|
||||
* -- c to wifi
|
||||
****************************************************************************/
|
||||
u32 get_gpmc0_base(void)
|
||||
{
|
||||
u32 b;
|
||||
|
||||
b = readl(&gpmc_cs_base->config7);
|
||||
b &= 0x1F; /* keep base [5:0] */
|
||||
b = b << 24; /* ret 0x0b000000 */
|
||||
return b;
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
|
||||
*******************************************************************/
|
||||
u32 get_gpmc0_width(void)
|
||||
{
|
||||
return WIDTH_16BIT;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* get_board_rev() - setup to pass kernel board revision information
|
||||
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
|
||||
*************************************************************************/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return 0x20;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* display_board_info() - print banner with board info.
|
||||
*********************************************************************/
|
||||
void display_board_info(u32 btype)
|
||||
{
|
||||
char *mem_s, *sec_s;
|
||||
|
||||
if (is_mem_sdr())
|
||||
mem_s = "mSDR";
|
||||
else
|
||||
mem_s = "LPDDR";
|
||||
|
||||
switch (get_device_type()) {
|
||||
case TST_DEVICE:
|
||||
sec_s = "TST";
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = "EMU";
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = "HS";
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = "GP";
|
||||
break;
|
||||
default:
|
||||
sec_s = "?";
|
||||
}
|
||||
|
||||
printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", sysinfo.cpu_string,
|
||||
sec_s, get_cpu_rev());
|
||||
printf("%s + %s/%s\n", sysinfo.board_string,
|
||||
mem_s, sysinfo.nand_string);
|
||||
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* get_base(); get upper addr of current execution
|
||||
*******************************************************/
|
||||
u32 get_base(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
|
||||
val &= 0xF0000000;
|
||||
val >>= 28;
|
||||
return val;
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_flash() - tell if currently running in
|
||||
* FLASH.
|
||||
*******************************************************/
|
||||
u32 is_running_in_flash(void)
|
||||
{
|
||||
if (get_base() < 4)
|
||||
return 1; /* in FLASH */
|
||||
|
||||
return 0; /* running in SRAM or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_sram() - tell if currently running in
|
||||
* SRAM.
|
||||
*******************************************************/
|
||||
u32 is_running_in_sram(void)
|
||||
{
|
||||
if (get_base() == 4)
|
||||
return 1; /* in SRAM */
|
||||
|
||||
return 0; /* running in FLASH or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_sdram() - tell if currently running in
|
||||
* SDRAM.
|
||||
*******************************************************/
|
||||
u32 is_running_in_sdram(void)
|
||||
{
|
||||
if (get_base() > 4)
|
||||
return 1; /* in SDRAM */
|
||||
|
||||
return 0; /* running in SRAM or FLASH */
|
||||
}
|
||||
|
||||
/***************************************************************
|
||||
* get_boot_type() - Is this an XIP type device or a stream one
|
||||
* bits 4-0 specify type. Bit 5 says mem/perif
|
||||
***************************************************************/
|
||||
u32 get_boot_type(void)
|
||||
{
|
||||
return (readl(&ctrl_base->status) & SYSBOOT_MASK);
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*************************************************************/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/************************************************************
|
||||
* sdelay() - simple spin loop. Will be constant time as
|
||||
* its generally used in bypass conditions only. This
|
||||
* is necessary until timers are accessible.
|
||||
*
|
||||
* not inline to increase chances its in cache when called
|
||||
*************************************************************/
|
||||
void sdelay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* sr32 - clear & set a value in a bit range for a 32 bit address
|
||||
*****************************************************************/
|
||||
void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
|
||||
{
|
||||
u32 tmp, msk = 0;
|
||||
msk = 1 << num_bits;
|
||||
--msk;
|
||||
tmp = readl((u32)addr) & ~(msk << start_bit);
|
||||
tmp |= value << start_bit;
|
||||
writel(tmp, (u32)addr);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* wait_on_value() - common routine to allow waiting for changes in
|
||||
* volatile regs.
|
||||
*********************************************************************/
|
||||
u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
|
||||
u32 bound)
|
||||
{
|
||||
u32 i = 0, val;
|
||||
do {
|
||||
++i;
|
||||
val = readl((u32)read_addr) & read_bit_mask;
|
||||
if (val == match_value)
|
||||
return 1;
|
||||
if (i == bound)
|
||||
return 0;
|
||||
} while (1);
|
||||
}
|
||||
|
|
@ -0,0 +1,516 @@
|
|||
/*
|
||||
* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
|
||||
*
|
||||
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
|
||||
*
|
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
||||
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
.globl _start
|
||||
_start: b reset
|
||||
ldr pc, _undefined_instruction
|
||||
ldr pc, _software_interrupt
|
||||
ldr pc, _prefetch_abort
|
||||
ldr pc, _data_abort
|
||||
ldr pc, _not_used
|
||||
ldr pc, _irq
|
||||
ldr pc, _fiq
|
||||
|
||||
_undefined_instruction: .word undefined_instruction
|
||||
_software_interrupt: .word software_interrupt
|
||||
_prefetch_abort: .word prefetch_abort
|
||||
_data_abort: .word data_abort
|
||||
_not_used: .word not_used
|
||||
_irq: .word irq
|
||||
_fiq: .word fiq
|
||||
_pad: .word 0x12345678 /* now 16*4=64 */
|
||||
.global _end_vect
|
||||
_end_vect:
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
/*************************************************************************
|
||||
*
|
||||
* Startup Code (reset vector)
|
||||
*
|
||||
* do important init only if we don't start from memory!
|
||||
* setup Memory and board specific bits prior to relocation.
|
||||
* relocate armboot to ram
|
||||
* setup stack
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word _end
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */
|
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START:
|
||||
.word 0x0badc0de
|
||||
#endif
|
||||
|
||||
/*
|
||||
* the actual reset code
|
||||
*/
|
||||
|
||||
reset:
|
||||
/*
|
||||
* set the cpu to SVC32 mode
|
||||
*/
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1f
|
||||
orr r0, r0, #0xd3
|
||||
msr cpsr,r0
|
||||
|
||||
#if (CONFIG_OMAP34XX)
|
||||
/* Copy vectors to mask ROM indirect addr */
|
||||
adr r0, _start @ r0 <- current position of code
|
||||
add r0, r0, #4 @ skip reset vector
|
||||
mov r2, #64 @ r2 <- size to copy
|
||||
add r2, r0, r2 @ r2 <- source end address
|
||||
mov r1, #SRAM_OFFSET0 @ build vect addr
|
||||
mov r3, #SRAM_OFFSET1
|
||||
add r1, r1, r3
|
||||
mov r3, #SRAM_OFFSET2
|
||||
add r1, r1, r3
|
||||
next:
|
||||
ldmia r0!, {r3 - r10} @ copy from source address [r0]
|
||||
stmia r1!, {r3 - r10} @ copy to target address [r1]
|
||||
cmp r0, r2 @ until source end address [r2]
|
||||
bne next @ loop until equal */
|
||||
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
|
||||
/* No need to copy/exec the clock code - DPLL adjust already done
|
||||
* in NAND/oneNAND Boot.
|
||||
*/
|
||||
bl cpy_clk_code @ put dpll adjust code behind vectors
|
||||
#endif /* NAND Boot */
|
||||
#endif
|
||||
/* the mask ROM code should have PLL and others stable */
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
relocate: @ relocate U-Boot to RAM
|
||||
adr r0, _start @ r0 <- current position of code
|
||||
ldr r1, _TEXT_BASE @ test if we run from flash or RAM
|
||||
cmp r0, r1 @ don't reloc during debug
|
||||
beq stack_setup
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 @ r2 <- size of armboot
|
||||
add r2, r0, r2 @ r2 <- source end address
|
||||
|
||||
copy_loop: @ copy 32 bytes at a time
|
||||
ldmia r0!, {r3 - r10} @ copy from source address [r0]
|
||||
stmia r1!, {r3 - r10} @ copy to target address [r1]
|
||||
cmp r0, r2 @ until source end addreee [r2]
|
||||
ble copy_loop
|
||||
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
|
||||
|
||||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
|
||||
sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
|
||||
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
|
||||
#endif
|
||||
sub sp, r0, #12 @ leave 3 words for abort-stack
|
||||
and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
|
||||
|
||||
/* Clear BSS (if any). Is below tx (watch load addr - need space) */
|
||||
clear_bss:
|
||||
ldr r0, _bss_start @ find start of bss segment
|
||||
ldr r1, _bss_end @ stop here
|
||||
mov r2, #0x00000000 @ clear value
|
||||
clbss_l:
|
||||
str r2, [r0] @ clear BSS location
|
||||
cmp r0, r1 @ are we at the end yet
|
||||
add r0, r0, #4 @ increment clear index pointer
|
||||
bne clbss_l @ keep clearing till at end
|
||||
|
||||
ldr pc, _start_armboot @ jump to C code
|
||||
|
||||
_start_armboot: .word start_armboot
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
*
|
||||
* setup important registers
|
||||
* setup memory timing
|
||||
*
|
||||
*************************************************************************/
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* Invalidate L1 I/D
|
||||
*/
|
||||
mov r0, #0 @ set up for MCR
|
||||
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
|
||||
|
||||
/*
|
||||
* disable MMU stuff and caches
|
||||
*/
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
|
||||
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
|
||||
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
|
||||
orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
/*
|
||||
* Jump to board specific initialization...
|
||||
* The Mask ROM will have already initialized
|
||||
* basic memory. Go here to bump up clock rate and handle
|
||||
* wake up conditions.
|
||||
*/
|
||||
mov ip, lr @ persevere link reg across call
|
||||
bl lowlevel_init @ go setup pll,mux,memory
|
||||
mov lr, ip @ restore link
|
||||
mov pc, lr @ back to my caller
|
||||
/*
|
||||
*************************************************************************
|
||||
*
|
||||
* Interrupt handling
|
||||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72
|
||||
|
||||
#define S_OLD_R0 68
|
||||
#define S_PSR 64
|
||||
#define S_PC 60
|
||||
#define S_LR 56
|
||||
#define S_SP 52
|
||||
|
||||
#define S_IP 48
|
||||
#define S_FP 44
|
||||
#define S_R10 40
|
||||
#define S_R9 36
|
||||
#define S_R8 32
|
||||
#define S_R7 28
|
||||
#define S_R6 24
|
||||
#define S_R5 20
|
||||
#define S_R4 16
|
||||
#define S_R3 12
|
||||
#define S_R2 8
|
||||
#define S_R1 4
|
||||
#define S_R0 0
|
||||
|
||||
#define MODE_SVC 0x13
|
||||
#define I_BIT 0x80
|
||||
|
||||
/*
|
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
|
||||
*/
|
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
|
||||
@ user stack
|
||||
stmia sp, {r0 - r12} @ Save user registers (now in
|
||||
@ svc mode) r0-r12
|
||||
|
||||
ldr r2, _armboot_start
|
||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
|
||||
@ stack
|
||||
ldmia r2, {r2 - r3} @ get values for "aborted" pc
|
||||
@ and cpsr (into parm regs)
|
||||
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
||||
|
||||
add r5, sp, #S_SP
|
||||
mov r1, lr
|
||||
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||
mov r0, sp @ save current stack into r0
|
||||
@ (param register)
|
||||
.endm
|
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
|
||||
@ a reserved stack spot would
|
||||
@ be good.
|
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr
|
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0
|
||||
ldr lr, [sp, #S_PC] @ Get PC
|
||||
add sp, sp, #S_FRAME_SIZE
|
||||
subs pc, lr, #4 @ return & move spsr_svc into
|
||||
@ cpsr
|
||||
.endm
|
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_start @ setup our mode stack (enter
|
||||
@ in banked mode)
|
||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
|
||||
@ spots for abort stack
|
||||
|
||||
str lr, [r13] @ save caller lr in position 0
|
||||
@ of saved stack
|
||||
mrs lr, spsr @ get the spsr
|
||||
str lr, [r13, #4] @ save spsr in position 1 of
|
||||
@ saved stack
|
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode
|
||||
@ msr spsr_c, r13
|
||||
msr spsr, r13 @ switch modes, make sure
|
||||
@ moves will execute
|
||||
mov lr, pc @ capture return pc
|
||||
movs pc, lr @ jump to next instruction &
|
||||
@ switch modes.
|
||||
.endm
|
||||
|
||||
.macro get_bad_stack_swi
|
||||
sub r13, r13, #4 @ space on current stack for
|
||||
@ scratch reg.
|
||||
str r0, [r13] @ save R0's value.
|
||||
ldr r0, _armboot_start @ get data regions start
|
||||
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
|
||||
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
|
||||
@ spots for abort stack
|
||||
str lr, [r0] @ save caller lr in position 0
|
||||
@ of saved stack
|
||||
mrs r0, spsr @ get the spsr
|
||||
str lr, [r0, #4] @ save spsr in position 1 of
|
||||
@ saved stack
|
||||
ldr r0, [r13] @ restore r0
|
||||
add r13, r13, #4 @ pop stack entry
|
||||
.endm
|
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START
|
||||
.endm
|
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START
|
||||
.endm
|
||||
|
||||
/*
|
||||
* exception handlers
|
||||
*/
|
||||
.align 5
|
||||
undefined_instruction:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_undefined_instruction
|
||||
|
||||
.align 5
|
||||
software_interrupt:
|
||||
get_bad_stack_swi
|
||||
bad_save_user_regs
|
||||
bl do_software_interrupt
|
||||
|
||||
.align 5
|
||||
prefetch_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_prefetch_abort
|
||||
|
||||
.align 5
|
||||
data_abort:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_data_abort
|
||||
|
||||
.align 5
|
||||
not_used:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_not_used
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_irq_stack
|
||||
irq_save_user_regs
|
||||
bl do_irq
|
||||
irq_restore_user_regs
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_fiq_stack
|
||||
/* someone ought to write a more effective fiq_save_user_regs */
|
||||
irq_save_user_regs
|
||||
bl do_fiq
|
||||
irq_restore_user_regs
|
||||
|
||||
#else
|
||||
|
||||
.align 5
|
||||
irq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_irq
|
||||
|
||||
.align 5
|
||||
fiq:
|
||||
get_bad_stack
|
||||
bad_save_user_regs
|
||||
bl do_fiq
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* v7_flush_dcache_all()
|
||||
*
|
||||
* Flush the whole D-cache.
|
||||
*
|
||||
* Corrupted registers: r0-r5, r7, r9-r11
|
||||
*
|
||||
* - mm - mm_struct describing address space
|
||||
*/
|
||||
.align 5
|
||||
.global v7_flush_dcache_all
|
||||
v7_flush_dcache_all:
|
||||
stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
|
||||
|
||||
mov r7, r0 @ take a backup of device type
|
||||
cmp r0, #0x3 @ check if the device type is
|
||||
@ GP
|
||||
moveq r12, #0x1 @ set up to invalide L2
|
||||
smi: .word 0x01600070 @ Call SMI monitor (smieq)
|
||||
cmp r7, #0x3 @ compare again in case its
|
||||
@ lost
|
||||
beq finished_inval @ if GP device, inval done
|
||||
@ above
|
||||
|
||||
mrc p15, 1, r0, c0, c0, 1 @ read clidr
|
||||
ands r3, r0, #0x7000000 @ extract loc from clidr
|
||||
mov r3, r3, lsr #23 @ left align loc bit field
|
||||
beq finished_inval @ if loc is 0, then no need to
|
||||
@ clean
|
||||
mov r10, #0 @ start clean at cache level 0
|
||||
inval_loop1:
|
||||
add r2, r10, r10, lsr #1 @ work out 3x current cache
|
||||
@ level
|
||||
mov r1, r0, lsr r2 @ extract cache type bits from
|
||||
@ clidr
|
||||
and r1, r1, #7 @ mask of the bits for current
|
||||
@ cache only
|
||||
cmp r1, #2 @ see what cache we have at
|
||||
@ this level
|
||||
blt skip_inval @ skip if no cache, or just
|
||||
@ i-cache
|
||||
mcr p15, 2, r10, c0, c0, 0 @ select current cache level
|
||||
@ in cssr
|
||||
mov r2, #0 @ operand for mcr SBZ
|
||||
mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
|
||||
@ sych the new cssr&csidr,
|
||||
@ with armv7 this is 'isb',
|
||||
@ but we compile with armv5
|
||||
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
|
||||
and r2, r1, #7 @ extract the length of the
|
||||
@ cache lines
|
||||
add r2, r2, #4 @ add 4 (line length offset)
|
||||
ldr r4, =0x3ff
|
||||
ands r4, r4, r1, lsr #3 @ find maximum number on the
|
||||
@ way size
|
||||
clz r5, r4 @ find bit position of way
|
||||
@ size increment
|
||||
ldr r7, =0x7fff
|
||||
ands r7, r7, r1, lsr #13 @ extract max number of the
|
||||
@ index size
|
||||
inval_loop2:
|
||||
mov r9, r4 @ create working copy of max
|
||||
@ way size
|
||||
inval_loop3:
|
||||
orr r11, r10, r9, lsl r5 @ factor way and cache number
|
||||
@ into r11
|
||||
orr r11, r11, r7, lsl r2 @ factor index number into r11
|
||||
mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
|
||||
subs r9, r9, #1 @ decrement the way
|
||||
bge inval_loop3
|
||||
subs r7, r7, #1 @ decrement the index
|
||||
bge inval_loop2
|
||||
skip_inval:
|
||||
add r10, r10, #2 @ increment cache number
|
||||
cmp r3, r10
|
||||
bgt inval_loop1
|
||||
finished_inval:
|
||||
mov r10, #0 @ swith back to cache level 0
|
||||
mcr p15, 2, r10, c0, c0, 0 @ select current cache level
|
||||
@ in cssr
|
||||
mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
|
||||
@ with armv7 this is 'isb',
|
||||
@ but we compile with armv5
|
||||
|
||||
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
|
||||
|
||||
|
||||
.align 5
|
||||
.global reset_cpu
|
||||
reset_cpu:
|
||||
ldr r1, rstctl @ get addr for global reset
|
||||
@ reg
|
||||
mov r3, #0x2 @ full reset pll + mpu
|
||||
str r3, [r1] @ force reset
|
||||
mov r0, r0
|
||||
_loop_forever:
|
||||
b _loop_forever
|
||||
rstctl:
|
||||
.word PRM_RSTCTRL
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
The Nomadik 8815 CPU has a "secure" boot mode where no external access
|
||||
(not even JTAG) is allowed. The "remap" bits in the evaluation board
|
||||
are configured in order to boot from the internal ROM memory (in
|
||||
secure mode).
|
||||
|
||||
The boot process as defined by the manufacturer executes external code
|
||||
(loaded from NAND or OneNAND) that that disables such "security" in
|
||||
order to run u-boot and later the kernel without constraints. Such
|
||||
code is a proprietary initial boot loader, called "X-Loader" (in case
|
||||
anyone wonders, it has no relations with other loaders with the same
|
||||
name and there is no GPL code inside the ST X-Loader).
|
||||
|
||||
SDRAM configuration, PLL setup and initial loading from NAND is
|
||||
implemented in the X-Loader, so U-Boot is already running in SDRAM
|
||||
when control is handed over to it.
|
||||
|
||||
|
||||
On www.st.com/nomadik and on www.stnwireless.com there are documents,
|
||||
summary data and white papers on Nomadik. The full datasheet for
|
||||
STn8815 is not currently available on line but under specific request
|
||||
to the local ST sales offices.
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
|
||||
Summary
|
||||
=======
|
||||
|
||||
This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
|
||||
family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
|
||||
some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D
|
||||
graphics processor and various other standard peripherals.
|
||||
|
||||
Currently the following boards are supported:
|
||||
|
||||
* OMAP3530 BeagleBoard [2]
|
||||
|
||||
* Gumstix Overo [3]
|
||||
|
||||
* TI EVM [4]
|
||||
|
||||
* OpenPandora Ltd. Pandora [5]
|
||||
|
||||
* TI/Logic PD Zoom MDK [6]
|
||||
|
||||
Toolchain
|
||||
=========
|
||||
|
||||
While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
|
||||
with -march=armv5 to allow more compilers to work. For U-Boot code this has
|
||||
no performance impact.
|
||||
|
||||
Build
|
||||
=====
|
||||
|
||||
* BeagleBoard:
|
||||
|
||||
make omap3_beagle_config
|
||||
make
|
||||
|
||||
* Gumstix Overo:
|
||||
|
||||
make omap3_overo_config
|
||||
make
|
||||
|
||||
* TI EVM:
|
||||
|
||||
make omap3_evm_config
|
||||
make
|
||||
|
||||
* Pandora:
|
||||
|
||||
make omap3_pandora_config
|
||||
make
|
||||
|
||||
* Zoom MDK:
|
||||
|
||||
make omap3_zoom1_config
|
||||
make
|
||||
|
||||
Custom commands
|
||||
===============
|
||||
|
||||
To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
|
||||
for OMAP3 supports custom user command
|
||||
|
||||
nandecc hw/sw
|
||||
|
||||
To be compatible with NAND drivers using SW ECC (e.g. kernel code)
|
||||
|
||||
nandecc sw
|
||||
|
||||
enables SW ECC calculation. HW ECC enabled with
|
||||
|
||||
nandecc hw
|
||||
|
||||
is typically used to write 2nd stage bootloader (known as 'x-loader') which is
|
||||
executed by OMAP3's boot rom and therefore has to be written with HW ECC.
|
||||
|
||||
For all other commands see
|
||||
|
||||
help
|
||||
|
||||
Acknowledgements
|
||||
================
|
||||
|
||||
OMAP3 U-Boot is based on U-Boot tar ball [7] for BeagleBoard and EVM done by
|
||||
several TI employees.
|
||||
|
||||
Links
|
||||
=====
|
||||
|
||||
[1] OMAP3:
|
||||
|
||||
http://www.ti.com/omap3 (high volume) and
|
||||
http://www.ti.com/omap35x (broad market)
|
||||
|
||||
[2] OMAP3530 BeagleBoard:
|
||||
|
||||
http://beagleboard.org/
|
||||
|
||||
[3] Gumstix Overo:
|
||||
|
||||
http://www.gumstix.net/Overo/
|
||||
|
||||
[4] TI EVM:
|
||||
|
||||
http://focus.ti.com/docs/toolsw/folders/print/tmdxevm3503.html
|
||||
|
||||
[5] OpenPandora Ltd. Pandora:
|
||||
|
||||
http://openpandora.org/
|
||||
|
||||
[6] TI/Logic PD Zoom MDK:
|
||||
|
||||
http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit
|
||||
|
||||
[7] TI OMAP3 U-Boot:
|
||||
|
||||
http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
|
||||
|
|
@ -30,6 +30,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
|
|||
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
|
||||
COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
|
||||
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
|
||||
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
|
||||
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
|
||||
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
|
||||
|
||||
|
|
|
|||
|
|
@ -109,7 +109,11 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
|
|||
|
||||
status = wait_for_pin ();
|
||||
if (status & I2C_STAT_RRDY) {
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
*value = readb (I2C_DATA);
|
||||
#else
|
||||
*value = readw (I2C_DATA);
|
||||
#endif
|
||||
udelay (20000);
|
||||
} else {
|
||||
i2c_error = 1;
|
||||
|
|
@ -150,8 +154,23 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
|
|||
status = wait_for_pin ();
|
||||
|
||||
if (status & I2C_STAT_XRDY) {
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
/* send out 1 byte */
|
||||
writeb (regoffset, I2C_DATA);
|
||||
writew (I2C_STAT_XRDY, I2C_STAT);
|
||||
|
||||
status = wait_for_pin ();
|
||||
if ((status & I2C_STAT_XRDY)) {
|
||||
/* send out next 1 byte */
|
||||
writeb (value, I2C_DATA);
|
||||
writew (I2C_STAT_XRDY, I2C_STAT);
|
||||
} else {
|
||||
i2c_error = 1;
|
||||
}
|
||||
#else
|
||||
/* send out two bytes */
|
||||
writew ((value << 8) + regoffset, I2C_DATA);
|
||||
#endif
|
||||
/* must have enough delay to allow BB bit to go low */
|
||||
udelay (50000);
|
||||
if (readw (I2C_STAT) & I2C_STAT_NACK) {
|
||||
|
|
@ -188,7 +207,11 @@ static void flush_fifo(void)
|
|||
while(1){
|
||||
stat = readw(I2C_STAT);
|
||||
if(stat == I2C_STAT_RRDY){
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
readb(I2C_DATA);
|
||||
#else
|
||||
readw(I2C_DATA);
|
||||
#endif
|
||||
writew(I2C_STAT_RRDY,I2C_STAT);
|
||||
udelay(1000);
|
||||
}else
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
|
|||
LIB := $(obj)libmmc.a
|
||||
|
||||
COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
|
||||
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,558 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation's version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <fat.h>
|
||||
#include <mmc.h>
|
||||
#include <part.h>
|
||||
#include <i2c.h>
|
||||
|
||||
const unsigned short mmc_transspeed_val[15][4] = {
|
||||
{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
|
||||
{CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
|
||||
{CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
|
||||
{CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
|
||||
{CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
|
||||
{CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
|
||||
{CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
|
||||
{CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
|
||||
{CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
|
||||
{CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
|
||||
{CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
|
||||
{CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
|
||||
{CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
|
||||
{CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
|
||||
{CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
|
||||
};
|
||||
|
||||
mmc_card_data cur_card_data;
|
||||
static block_dev_desc_t mmc_blk_dev;
|
||||
|
||||
block_dev_desc_t *mmc_get_dev(int dev)
|
||||
{
|
||||
return (block_dev_desc_t *) &mmc_blk_dev;
|
||||
}
|
||||
|
||||
void twl4030_mmc_config(void)
|
||||
{
|
||||
unsigned char data;
|
||||
|
||||
data = 0x20;
|
||||
i2c_write(0x4B, 0x82, 1, &data, 1);
|
||||
data = 0x2;
|
||||
i2c_write(0x4B, 0x85, 1, &data, 1);
|
||||
}
|
||||
|
||||
unsigned char mmc_board_init(void)
|
||||
{
|
||||
unsigned int value = 0;
|
||||
|
||||
twl4030_mmc_config();
|
||||
|
||||
value = CONTROL_PBIAS_LITE;
|
||||
CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9);
|
||||
|
||||
value = CONTROL_DEV_CONF0;
|
||||
CONTROL_DEV_CONF0 = value | (1 << 24);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void mmc_init_stream(void)
|
||||
{
|
||||
volatile unsigned int mmc_stat;
|
||||
|
||||
OMAP_HSMMC_CON |= INIT_INITSTREAM;
|
||||
|
||||
OMAP_HSMMC_CMD = MMC_CMD0;
|
||||
do {
|
||||
mmc_stat = OMAP_HSMMC_STAT;
|
||||
} while (!(mmc_stat & CC_MASK));
|
||||
|
||||
OMAP_HSMMC_STAT = CC_MASK;
|
||||
|
||||
OMAP_HSMMC_CMD = MMC_CMD0;
|
||||
do {
|
||||
mmc_stat = OMAP_HSMMC_STAT;
|
||||
} while (!(mmc_stat & CC_MASK));
|
||||
|
||||
OMAP_HSMMC_STAT = OMAP_HSMMC_STAT;
|
||||
OMAP_HSMMC_CON &= ~INIT_INITSTREAM;
|
||||
}
|
||||
|
||||
unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK),
|
||||
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
|
||||
|
||||
switch (iclk) {
|
||||
case CLK_INITSEQ:
|
||||
val = MMC_INIT_SEQ_CLK / 2;
|
||||
break;
|
||||
case CLK_400KHZ:
|
||||
val = MMC_400kHz_CLK;
|
||||
break;
|
||||
case CLK_MISC:
|
||||
val = clk_div;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
mmc_reg_out(OMAP_HSMMC_SYSCTL,
|
||||
ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
|
||||
|
||||
while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ;
|
||||
|
||||
OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char mmc_init_setup(void)
|
||||
{
|
||||
unsigned int reg_val;
|
||||
|
||||
mmc_board_init();
|
||||
|
||||
OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
|
||||
while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
|
||||
|
||||
OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
|
||||
while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
|
||||
|
||||
OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
|
||||
OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
|
||||
|
||||
reg_val = OMAP_HSMMC_CON & RESERVED_MASK;
|
||||
|
||||
OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH |
|
||||
CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC |
|
||||
STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN;
|
||||
|
||||
mmc_clock_config(CLK_INITSEQ, 0);
|
||||
OMAP_HSMMC_HCTL |= SDBP_PWRON;
|
||||
|
||||
OMAP_HSMMC_IE = 0x307f0033;
|
||||
|
||||
mmc_init_stream();
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
|
||||
unsigned int *response)
|
||||
{
|
||||
volatile unsigned int mmc_stat;
|
||||
|
||||
while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ;
|
||||
|
||||
OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
|
||||
OMAP_HSMMC_STAT = 0xFFFFFFFF;
|
||||
OMAP_HSMMC_ARG = arg;
|
||||
OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK |
|
||||
CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE |
|
||||
DE_DISABLE;
|
||||
|
||||
while (1) {
|
||||
do {
|
||||
mmc_stat = OMAP_HSMMC_STAT;
|
||||
} while (mmc_stat == 0);
|
||||
|
||||
if ((mmc_stat & ERRI_MASK) != 0)
|
||||
return (unsigned char) mmc_stat;
|
||||
|
||||
if (mmc_stat & CC_MASK) {
|
||||
OMAP_HSMMC_STAT = CC_MASK;
|
||||
response[0] = OMAP_HSMMC_RSP10;
|
||||
if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
|
||||
response[1] = OMAP_HSMMC_RSP32;
|
||||
response[2] = OMAP_HSMMC_RSP54;
|
||||
response[3] = OMAP_HSMMC_RSP76;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char mmc_read_data(unsigned int *output_buf)
|
||||
{
|
||||
volatile unsigned int mmc_stat;
|
||||
unsigned int read_count = 0;
|
||||
|
||||
/*
|
||||
* Start Polled Read
|
||||
*/
|
||||
while (1) {
|
||||
do {
|
||||
mmc_stat = OMAP_HSMMC_STAT;
|
||||
} while (mmc_stat == 0);
|
||||
|
||||
if ((mmc_stat & ERRI_MASK) != 0)
|
||||
return (unsigned char) mmc_stat;
|
||||
|
||||
if (mmc_stat & BRR_MASK) {
|
||||
unsigned int k;
|
||||
|
||||
OMAP_HSMMC_STAT |= BRR_MASK;
|
||||
for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
|
||||
*output_buf = OMAP_HSMMC_DATA;
|
||||
output_buf++;
|
||||
read_count += 4;
|
||||
}
|
||||
}
|
||||
|
||||
if (mmc_stat & BWR_MASK)
|
||||
OMAP_HSMMC_STAT |= BWR_MASK;
|
||||
|
||||
if (mmc_stat & TC_MASK) {
|
||||
OMAP_HSMMC_STAT |= TC_MASK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
|
||||
{
|
||||
unsigned char err;
|
||||
unsigned int argument = 0;
|
||||
unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val;
|
||||
unsigned int resp[4];
|
||||
unsigned short retry_cnt = 2000;
|
||||
|
||||
/* Set to Initialization Clock */
|
||||
err = mmc_clock_config(CLK_400KHZ, 0);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS;
|
||||
argument = 0x00000000;
|
||||
|
||||
ocr_value = (0x1FF << 15);
|
||||
err = mmc_send_cmd(MMC_CMD0, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE;
|
||||
err = mmc_send_cmd(MMC_SDCMD8, argument, resp);
|
||||
hcs_val = (err == 1) ?
|
||||
MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR :
|
||||
MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE;
|
||||
|
||||
argument = 0x0000 << 16;
|
||||
err = mmc_send_cmd(MMC_CMD55, argument, resp);
|
||||
if (err == 1) {
|
||||
mmc_card_cur->card_type = SD_CARD;
|
||||
ocr_value |= hcs_val;
|
||||
ret_cmd41 = MMC_ACMD41;
|
||||
} else {
|
||||
mmc_card_cur->card_type = MMC_CARD;
|
||||
ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
|
||||
ret_cmd41 = MMC_CMD1;
|
||||
OMAP_HSMMC_CON &= ~OD;
|
||||
OMAP_HSMMC_CON |= OPENDRAIN;
|
||||
}
|
||||
|
||||
argument = ocr_value;
|
||||
err = mmc_send_cmd(ret_cmd41, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
|
||||
|
||||
while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) {
|
||||
retry_cnt--;
|
||||
if (mmc_card_cur->card_type == SD_CARD) {
|
||||
argument = 0x0000 << 16;
|
||||
err = mmc_send_cmd(MMC_CMD55, argument, resp);
|
||||
}
|
||||
|
||||
argument = ocr_value;
|
||||
err = mmc_send_cmd(ret_cmd41, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
|
||||
}
|
||||
|
||||
if (!(ocr_recvd & (0x1 << 31)))
|
||||
return 0;
|
||||
|
||||
if (mmc_card_cur->card_type == MMC_CARD) {
|
||||
if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) ==
|
||||
MMC_OCR_REG_ACCESS_MODE_SECTOR) {
|
||||
mmc_card_cur->mode = SECTOR_MODE;
|
||||
} else {
|
||||
mmc_card_cur->mode = BYTE_MODE;
|
||||
}
|
||||
|
||||
ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK;
|
||||
} else {
|
||||
if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK)
|
||||
== MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) {
|
||||
mmc_card_cur->mode = SECTOR_MODE;
|
||||
} else {
|
||||
mmc_card_cur->mode = BYTE_MODE;
|
||||
}
|
||||
ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK;
|
||||
}
|
||||
|
||||
ocr_recvd &= ~(0x1 << 31);
|
||||
if (!(ocr_recvd & ocr_value))
|
||||
return 0;
|
||||
|
||||
err = mmc_send_cmd(MMC_CMD2, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
if (mmc_card_cur->card_type == MMC_CARD) {
|
||||
argument = mmc_card_cur->RCA << 16;
|
||||
err = mmc_send_cmd(MMC_CMD3, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
} else {
|
||||
argument = 0x00000000;
|
||||
err = mmc_send_cmd(MMC_SDCMD3, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca;
|
||||
}
|
||||
|
||||
OMAP_HSMMC_CON &= ~OD;
|
||||
OMAP_HSMMC_CON |= NOOPENDRAIN;
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data,
|
||||
mmc_csd_reg_t *cur_csd)
|
||||
{
|
||||
mmc_extended_csd_reg_t ext_csd;
|
||||
unsigned int size, count, blk_len, blk_no, card_size, argument;
|
||||
unsigned char err;
|
||||
unsigned int resp[4];
|
||||
|
||||
if (mmc_dev_data->mode == SECTOR_MODE) {
|
||||
if (mmc_dev_data->card_type == SD_CARD) {
|
||||
card_size =
|
||||
(((mmc_sd2_csd_reg_t *) cur_csd)->
|
||||
c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) |
|
||||
((((mmc_sd2_csd_reg_t *) cur_csd)->
|
||||
c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK)
|
||||
<< MMC_SD2_CSD_C_SIZE_MSB_OFFSET);
|
||||
mmc_dev_data->size = card_size * 1024;
|
||||
if (mmc_dev_data->size == 0)
|
||||
return 0;
|
||||
} else {
|
||||
argument = 0x00000000;
|
||||
err = mmc_send_cmd(MMC_CMD8, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
err = mmc_read_data((unsigned int *) &ext_csd);
|
||||
if (err != 1)
|
||||
return err;
|
||||
mmc_dev_data->size = ext_csd.sectorcount;
|
||||
|
||||
if (mmc_dev_data->size == 0)
|
||||
mmc_dev_data->size = 8388608;
|
||||
}
|
||||
} else {
|
||||
if (cur_csd->c_size_mult >= 8)
|
||||
return 0;
|
||||
|
||||
if (cur_csd->read_bl_len >= 12)
|
||||
return 0;
|
||||
|
||||
/* Compute size */
|
||||
count = 1 << (cur_csd->c_size_mult + 2);
|
||||
card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) |
|
||||
((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK)
|
||||
<< MMC_CSD_C_SIZE_MSB_OFFSET);
|
||||
blk_no = (card_size + 1) * count;
|
||||
blk_len = 1 << cur_csd->read_bl_len;
|
||||
size = blk_no * blk_len;
|
||||
mmc_dev_data->size = size / MMCSD_SECTOR_SIZE;
|
||||
if (mmc_dev_data->size == 0)
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes,
|
||||
mmc_card_data *mmc_c,
|
||||
unsigned long *output_buf)
|
||||
{
|
||||
unsigned char err;
|
||||
unsigned int argument;
|
||||
unsigned int resp[4];
|
||||
unsigned int num_sec_val =
|
||||
(num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE;
|
||||
unsigned int sec_inc_val;
|
||||
|
||||
if (num_sec_val == 0)
|
||||
return 1;
|
||||
|
||||
if (mmc_c->mode == SECTOR_MODE) {
|
||||
argument = start_sec;
|
||||
sec_inc_val = 1;
|
||||
} else {
|
||||
argument = start_sec * MMCSD_SECTOR_SIZE;
|
||||
sec_inc_val = MMCSD_SECTOR_SIZE;
|
||||
}
|
||||
|
||||
while (num_sec_val) {
|
||||
err = mmc_send_cmd(MMC_CMD17, argument, resp);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
err = mmc_read_data((unsigned int *) output_buf);
|
||||
if (err != 1)
|
||||
return err;
|
||||
|
||||
output_buf += (MMCSD_SECTOR_SIZE / 4);
|
||||
argument += sec_inc_val;
|
||||
num_sec_val--;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
|
||||
{
|
||||
unsigned char ret_val;
|
||||
unsigned int argument;
|
||||
unsigned int resp[4];
|
||||
unsigned int trans_clk, trans_fact, trans_unit, retries = 2;
|
||||
mmc_csd_reg_t Card_CSD;
|
||||
unsigned char trans_speed;
|
||||
|
||||
ret_val = mmc_init_setup();
|
||||
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
do {
|
||||
ret_val = mmc_detect_card(mmc_card_cur);
|
||||
retries--;
|
||||
} while ((retries > 0) && (ret_val != 1));
|
||||
|
||||
argument = mmc_card_cur->RCA << 16;
|
||||
ret_val = mmc_send_cmd(MMC_CMD9, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
((unsigned int *) &Card_CSD)[3] = resp[3];
|
||||
((unsigned int *) &Card_CSD)[2] = resp[2];
|
||||
((unsigned int *) &Card_CSD)[1] = resp[1];
|
||||
((unsigned int *) &Card_CSD)[0] = resp[0];
|
||||
|
||||
if (mmc_card_cur->card_type == MMC_CARD)
|
||||
mmc_card_cur->version = Card_CSD.spec_vers;
|
||||
|
||||
trans_speed = Card_CSD.tran_speed;
|
||||
|
||||
ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK;
|
||||
trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK;
|
||||
|
||||
if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ)
|
||||
return 0;
|
||||
|
||||
if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) ||
|
||||
(trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0))
|
||||
return 0;
|
||||
|
||||
trans_unit >>= 0;
|
||||
trans_fact >>= 3;
|
||||
|
||||
trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2;
|
||||
ret_val = mmc_clock_config(CLK_MISC, trans_clk);
|
||||
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
argument = mmc_card_cur->RCA << 16;
|
||||
ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
/* Configure the block length to 512 bytes */
|
||||
argument = MMCSD_SECTOR_SIZE;
|
||||
ret_val = mmc_send_cmd(MMC_CMD16, argument, resp);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
/* get the card size in sectors */
|
||||
ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD);
|
||||
if (ret_val != 1)
|
||||
return ret_val;
|
||||
|
||||
return 1;
|
||||
}
|
||||
unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
|
||||
void *dst)
|
||||
{
|
||||
omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
|
||||
(unsigned long *) dst);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
if (configure_mmc(&cur_card_data) != 1)
|
||||
return 1;
|
||||
|
||||
mmc_blk_dev.if_type = IF_TYPE_MMC;
|
||||
mmc_blk_dev.part_type = PART_TYPE_DOS;
|
||||
mmc_blk_dev.dev = 0;
|
||||
mmc_blk_dev.lun = 0;
|
||||
mmc_blk_dev.type = 0;
|
||||
|
||||
/* FIXME fill in the correct size (is set to 32MByte) */
|
||||
mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
|
||||
mmc_blk_dev.lba = 0x10000;
|
||||
mmc_blk_dev.removable = 0;
|
||||
mmc_blk_dev.block_read = mmc_bread;
|
||||
|
||||
fat_register_device(&mmc_blk_dev, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar *dst, int size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_write(uchar *src, ulong dst, int size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -38,6 +38,7 @@ endif
|
|||
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
|
||||
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
|
||||
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
|
||||
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
|
||||
endif
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
|
||||
* Rohit Choraria <rohitkc@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/omap_gpmc.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <nand.h>
|
||||
|
||||
static uint8_t cs;
|
||||
static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
|
||||
static gpmc_csx_t *gpmc_cs_base;
|
||||
static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
|
||||
|
||||
/*
|
||||
* omap_nand_hwcontrol - Set the address pointers corretly for the
|
||||
* following address/data/command operation
|
||||
*/
|
||||
static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
|
||||
uint32_t ctrl)
|
||||
{
|
||||
register struct nand_chip *this = mtd->priv;
|
||||
|
||||
/*
|
||||
* Point the IO_ADDR to DATA and ADDRESS registers instead
|
||||
* of chip address
|
||||
*/
|
||||
switch (ctrl) {
|
||||
case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
|
||||
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
|
||||
break;
|
||||
case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
|
||||
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr;
|
||||
break;
|
||||
case NAND_CTRL_CHANGE | NAND_NCE:
|
||||
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
/*
|
||||
* omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
|
||||
* GPMC controller
|
||||
* @mtd: MTD device structure
|
||||
*
|
||||
*/
|
||||
static void omap_hwecc_init(struct nand_chip *chip)
|
||||
{
|
||||
/*
|
||||
* Init ECC Control Register
|
||||
* Clear all ECC | Enable Reg1
|
||||
*/
|
||||
writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
|
||||
writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config);
|
||||
}
|
||||
|
||||
/*
|
||||
* gen_true_ecc - This function will generate true ECC value, which
|
||||
* can be used when correcting data read from NAND flash memory core
|
||||
*
|
||||
* @ecc_buf: buffer to store ecc code
|
||||
*
|
||||
* @return: re-formatted ECC value
|
||||
*/
|
||||
static uint32_t gen_true_ecc(uint8_t *ecc_buf)
|
||||
{
|
||||
return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
|
||||
((ecc_buf[2] & 0x0F) << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* omap_correct_data - Compares the ecc read from nand spare area with ECC
|
||||
* registers values and corrects one bit error if it has occured
|
||||
* Further details can be had from OMAP TRM and the following selected links:
|
||||
* http://en.wikipedia.org/wiki/Hamming_code
|
||||
* http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
|
||||
*
|
||||
* @mtd: MTD device structure
|
||||
* @dat: page data
|
||||
* @read_ecc: ecc read from nand flash
|
||||
* @calc_ecc: ecc read from ECC registers
|
||||
*
|
||||
* @return 0 if data is OK or corrected, else returns -1
|
||||
*/
|
||||
static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
|
||||
uint8_t *read_ecc, uint8_t *calc_ecc)
|
||||
{
|
||||
uint32_t orig_ecc, new_ecc, res, hm;
|
||||
uint16_t parity_bits, byte;
|
||||
uint8_t bit;
|
||||
|
||||
/* Regenerate the orginal ECC */
|
||||
orig_ecc = gen_true_ecc(read_ecc);
|
||||
new_ecc = gen_true_ecc(calc_ecc);
|
||||
/* Get the XOR of real ecc */
|
||||
res = orig_ecc ^ new_ecc;
|
||||
if (res) {
|
||||
/* Get the hamming width */
|
||||
hm = hweight32(res);
|
||||
/* Single bit errors can be corrected! */
|
||||
if (hm == 12) {
|
||||
/* Correctable data! */
|
||||
parity_bits = res >> 16;
|
||||
bit = (parity_bits & 0x7);
|
||||
byte = (parity_bits >> 3) & 0x1FF;
|
||||
/* Flip the bit to correct */
|
||||
dat[byte] ^= (0x1 << bit);
|
||||
} else if (hm == 1) {
|
||||
printf("Error: Ecc is wrong\n");
|
||||
/* ECC itself is corrupted */
|
||||
return 2;
|
||||
} else {
|
||||
/*
|
||||
* hm distance != parity pairs OR one, could mean 2 bit
|
||||
* error OR potentially be on a blank page..
|
||||
* orig_ecc: contains spare area data from nand flash.
|
||||
* new_ecc: generated ecc while reading data area.
|
||||
* Note: if the ecc = 0, all data bits from which it was
|
||||
* generated are 0xFF.
|
||||
* The 3 byte(24 bits) ecc is generated per 512byte
|
||||
* chunk of a page. If orig_ecc(from spare area)
|
||||
* is 0xFF && new_ecc(computed now from data area)=0x0,
|
||||
* this means that data area is 0xFF and spare area is
|
||||
* 0xFF. A sure sign of a erased page!
|
||||
*/
|
||||
if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
|
||||
return 0;
|
||||
printf("Error: Bad compare! failed\n");
|
||||
/* detected 2 bit error */
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* omap_calculate_ecc - Generate non-inverted ECC bytes.
|
||||
*
|
||||
* Using noninverted ECC can be considered ugly since writing a blank
|
||||
* page ie. padding will clear the ECC bytes. This is no problem as
|
||||
* long nobody is trying to write data on the seemingly unused page.
|
||||
* Reading an erased page will produce an ECC mismatch between
|
||||
* generated and read ECC bytes that has to be dealt with separately.
|
||||
* E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
|
||||
* is used, the result of read will be 0x0 while the ECC offsets of the
|
||||
* spare area will be 0xFF which will result in an ECC mismatch.
|
||||
* @mtd: MTD structure
|
||||
* @dat: unused
|
||||
* @ecc_code: ecc_code buffer
|
||||
*/
|
||||
static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
|
||||
uint8_t *ecc_code)
|
||||
{
|
||||
u_int32_t val;
|
||||
|
||||
/* Start Reading from HW ECC1_Result = 0x200 */
|
||||
val = readl(&gpmc_base->ecc1_result);
|
||||
|
||||
ecc_code[0] = val & 0xFF;
|
||||
ecc_code[1] = (val >> 16) & 0xFF;
|
||||
ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
|
||||
|
||||
/*
|
||||
* Stop reading anymore ECC vals and clear old results
|
||||
* enable will be called if more reads are required
|
||||
*/
|
||||
writel(0x000, &gpmc_base->ecc_config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* omap_enable_ecc - This function enables the hardware ecc functionality
|
||||
* @mtd: MTD device structure
|
||||
* @mode: Read/Write mode
|
||||
*/
|
||||
static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
|
||||
|
||||
switch (mode) {
|
||||
case NAND_ECC_READ:
|
||||
case NAND_ECC_WRITE:
|
||||
/* Clear the ecc result registers, select ecc reg as 1 */
|
||||
writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
|
||||
|
||||
/*
|
||||
* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
|
||||
* tell all regs to generate size0 sized regs
|
||||
* we just have a single ECC engine for all CS
|
||||
*/
|
||||
writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
|
||||
&gpmc_base->ecc_size_config);
|
||||
val = (dev_width << 7) | (cs << 1) | (0x1);
|
||||
writel(val, &gpmc_base->ecc_config);
|
||||
break;
|
||||
default:
|
||||
printf("Error: Unrecognized Mode[%d]!\n", mode);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
|
||||
* The default is to come up on s/w ecc
|
||||
*
|
||||
* @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
|
||||
*
|
||||
*/
|
||||
void omap_nand_switch_ecc(int32_t hardware)
|
||||
{
|
||||
struct nand_chip *nand;
|
||||
struct mtd_info *mtd;
|
||||
|
||||
if (nand_curr_device < 0 ||
|
||||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
|
||||
!nand_info[nand_curr_device].name) {
|
||||
printf("Error: Can't switch ecc, no devices available\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mtd = &nand_info[nand_curr_device];
|
||||
nand = mtd->priv;
|
||||
|
||||
nand->options |= NAND_OWN_BUFFERS;
|
||||
|
||||
/* Reset ecc interface */
|
||||
nand->ecc.read_page = NULL;
|
||||
nand->ecc.write_page = NULL;
|
||||
nand->ecc.read_oob = NULL;
|
||||
nand->ecc.write_oob = NULL;
|
||||
nand->ecc.hwctl = NULL;
|
||||
nand->ecc.correct = NULL;
|
||||
nand->ecc.calculate = NULL;
|
||||
|
||||
/* Setup the ecc configurations again */
|
||||
if (hardware) {
|
||||
nand->ecc.mode = NAND_ECC_HW;
|
||||
nand->ecc.layout = &hw_nand_oob;
|
||||
nand->ecc.size = 512;
|
||||
nand->ecc.bytes = 3;
|
||||
nand->ecc.hwctl = omap_enable_hwecc;
|
||||
nand->ecc.correct = omap_correct_data;
|
||||
nand->ecc.calculate = omap_calculate_ecc;
|
||||
omap_hwecc_init(nand);
|
||||
printf("HW ECC selected\n");
|
||||
} else {
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
/* Use mtd default settings */
|
||||
nand->ecc.layout = NULL;
|
||||
printf("SW ECC selected\n");
|
||||
}
|
||||
|
||||
/* Update NAND handling after ECC mode switch */
|
||||
nand_scan_tail(mtd);
|
||||
|
||||
nand->options &= ~NAND_OWN_BUFFERS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Board-specific NAND initialization. The following members of the
|
||||
* argument are board-specific:
|
||||
* - IO_ADDR_R: address to read the 8 I/O lines of the flash device
|
||||
* - IO_ADDR_W: address to write the 8 I/O lines of the flash device
|
||||
* - cmd_ctrl: hardwarespecific function for accesing control-lines
|
||||
* - waitfunc: hardwarespecific function for accesing device ready/busy line
|
||||
* - ecc.hwctl: function to enable (reset) hardware ecc generator
|
||||
* - ecc.mode: mode of ecc, see defines
|
||||
* - chip_delay: chip dependent delay for transfering data from array to
|
||||
* read regs (tR)
|
||||
* - options: various chip options. They can partly be set to inform
|
||||
* nand_scan about special functionality. See the defines for further
|
||||
* explanation
|
||||
*/
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
int32_t gpmc_config = 0;
|
||||
cs = 0;
|
||||
|
||||
/*
|
||||
* xloader/Uboot's gpmc configuration would have configured GPMC for
|
||||
* nand type of memory. The following logic scans and latches on to the
|
||||
* first CS with NAND type memory.
|
||||
* TBD: need to make this logic generic to handle multiple CS NAND
|
||||
* devices.
|
||||
*/
|
||||
while (cs < GPMC_MAX_CS) {
|
||||
/*
|
||||
* Each GPMC set for a single CS is at offset 0x30
|
||||
* - already remapped for us
|
||||
*/
|
||||
gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
|
||||
(cs * GPMC_CONFIG_WIDTH));
|
||||
/* Check if NAND type is set */
|
||||
if ((readl(&gpmc_cs_base->config1) & 0xC00) ==
|
||||
0x800) {
|
||||
/* Found it!! */
|
||||
break;
|
||||
}
|
||||
cs++;
|
||||
}
|
||||
if (cs >= GPMC_MAX_CS) {
|
||||
printf("NAND: Unable to find NAND settings in "
|
||||
"GPMC Configuration - quitting\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpmc_config = readl(&gpmc_base->config);
|
||||
/* Disable Write protect */
|
||||
gpmc_config |= 0x10;
|
||||
writel(gpmc_config, &gpmc_base->config);
|
||||
|
||||
nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat;
|
||||
nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
|
||||
|
||||
nand->cmd_ctrl = omap_nand_hwcontrol;
|
||||
nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
|
||||
/* If we are 16 bit dev, our gpmc config tells us that */
|
||||
if ((readl(gpmc_cs_base) & 0x3000) == 0x1000)
|
||||
nand->options |= NAND_BUSWIDTH_16;
|
||||
|
||||
nand->chip_delay = 100;
|
||||
/* Default ECC mode */
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -33,9 +33,13 @@ ifeq ($(ARCH),arm)
|
|||
ifeq ($(BOARD),omap2420h4)
|
||||
LOAD_ADDR = 0x80300000
|
||||
else
|
||||
ifeq ($(CPU),omap3)
|
||||
LOAD_ADDR = 0x80300000
|
||||
else
|
||||
LOAD_ADDR = 0xc100000
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(ARCH),mips)
|
||||
LOAD_ADDR = 0x80200000 -T mips.lds
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#define CCM_PDR1 (CCM_BASE + 0x08)
|
||||
#define CCM_RCSR (CCM_BASE + 0x0c)
|
||||
#define CCM_MPCTL (CCM_BASE + 0x10)
|
||||
#define CCM_UPCTL (CCM_BASE + 0x10)
|
||||
#define CCM_UPCTL (CCM_BASE + 0x14)
|
||||
#define CCM_SPCTL (CCM_BASE + 0x18)
|
||||
#define CCM_COSR (CCM_BASE + 0x1C)
|
||||
#define CCM_CGR0 (CCM_BASE + 0x20)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _CLOCKS_H_
|
||||
#define _CLOCKS_H_
|
||||
|
||||
#define LDELAY 12000000
|
||||
|
||||
#define S12M 12000000
|
||||
#define S13M 13000000
|
||||
#define S19_2M 19200000
|
||||
#define S24M 24000000
|
||||
#define S26M 26000000
|
||||
#define S38_4M 38400000
|
||||
|
||||
#define FCK_IVA2_ON 0x00000001
|
||||
#define FCK_CORE1_ON 0x03fffe29
|
||||
#define ICK_CORE1_ON 0x3ffffffb
|
||||
#define ICK_CORE2_ON 0x0000001f
|
||||
#define FCK_WKUP_ON 0x000000e9
|
||||
#define ICK_WKUP_ON 0x0000003f
|
||||
#define FCK_DSS_ON 0x00000005
|
||||
#define ICK_DSS_ON 0x00000001
|
||||
#define FCK_CAM_ON 0x00000001
|
||||
#define ICK_CAM_ON 0x00000001
|
||||
#define FCK_PER_ON 0x0003ffff
|
||||
#define ICK_PER_ON 0x0003ffff
|
||||
|
||||
/* Used to index into DPLL parameter tables */
|
||||
typedef struct {
|
||||
unsigned int m;
|
||||
unsigned int n;
|
||||
unsigned int fsel;
|
||||
unsigned int m2;
|
||||
} dpll_param;
|
||||
|
||||
/* Following functions are exported from lowlevel_init.S */
|
||||
extern dpll_param *get_mpu_dpll_param(void);
|
||||
extern dpll_param *get_iva_dpll_param(void);
|
||||
extern dpll_param *get_core_dpll_param(void);
|
||||
extern dpll_param *get_per_dpll_param(void);
|
||||
|
||||
extern void *_end_vect, *_start;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _CLOCKS_OMAP3_H_
|
||||
#define _CLOCKS_OMAP3_H_
|
||||
|
||||
#define PLL_STOP 1 /* PER & IVA */
|
||||
#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
|
||||
#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
|
||||
#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
|
||||
|
||||
/*
|
||||
* The following configurations are OPP and SysClk value independant
|
||||
* and hence are defined here. All the other DPLL related values are
|
||||
* tabulated in lowlevel_init.S.
|
||||
*/
|
||||
|
||||
/* CORE DPLL */
|
||||
#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
|
||||
#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
|
||||
#define CORE_FUSB_DIV 2 /* 41.5MHz: */
|
||||
#define CORE_L4_DIV 2 /* 83MHz : L4 */
|
||||
#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
|
||||
#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
|
||||
#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
|
||||
|
||||
/* PER DPLL */
|
||||
#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
|
||||
#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
|
||||
#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
|
||||
#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
|
||||
|
||||
#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
|
||||
|
||||
/* MPU DPLL */
|
||||
|
||||
#define MPU_M_12_ES1 0x0FE
|
||||
#define MPU_N_12_ES1 0x07
|
||||
#define MPU_FSEL_12_ES1 0x05
|
||||
#define MPU_M2_12_ES1 0x01
|
||||
|
||||
#define MPU_M_12_ES2 0x0FA
|
||||
#define MPU_N_12_ES2 0x05
|
||||
#define MPU_FSEL_12_ES2 0x07
|
||||
#define MPU_M2_ES2 0x01
|
||||
|
||||
#define MPU_M_12 0x085
|
||||
#define MPU_N_12 0x05
|
||||
#define MPU_FSEL_12 0x07
|
||||
#define MPU_M2_12 0x01
|
||||
|
||||
#define MPU_M_13_ES1 0x17D
|
||||
#define MPU_N_13_ES1 0x0C
|
||||
#define MPU_FSEL_13_ES1 0x03
|
||||
#define MPU_M2_13_ES1 0x01
|
||||
|
||||
#define MPU_M_13_ES2 0x1F4
|
||||
#define MPU_N_13_ES2 0x0C
|
||||
#define MPU_FSEL_13_ES2 0x03
|
||||
#define MPU_M2_13_ES2 0x01
|
||||
|
||||
#define MPU_M_13 0x10A
|
||||
#define MPU_N_13 0x0C
|
||||
#define MPU_FSEL_13 0x03
|
||||
#define MPU_M2_13 0x01
|
||||
|
||||
#define MPU_M_19P2_ES1 0x179
|
||||
#define MPU_N_19P2_ES1 0x12
|
||||
#define MPU_FSEL_19P2_ES1 0x04
|
||||
#define MPU_M2_19P2_ES1 0x01
|
||||
|
||||
#define MPU_M_19P2_ES2 0x271
|
||||
#define MPU_N_19P2_ES2 0x17
|
||||
#define MPU_FSEL_19P2_ES2 0x03
|
||||
#define MPU_M2_19P2_ES2 0x01
|
||||
|
||||
#define MPU_M_19P2 0x14C
|
||||
#define MPU_N_19P2 0x17
|
||||
#define MPU_FSEL_19P2 0x03
|
||||
#define MPU_M2_19P2 0x01
|
||||
|
||||
#define MPU_M_26_ES1 0x17D
|
||||
#define MPU_N_26_ES1 0x19
|
||||
#define MPU_FSEL_26_ES1 0x03
|
||||
#define MPU_M2_26_ES1 0x01
|
||||
|
||||
#define MPU_M_26_ES2 0x0FA
|
||||
#define MPU_N_26_ES2 0x0C
|
||||
#define MPU_FSEL_26_ES2 0x07
|
||||
#define MPU_M2_26_ES2 0x01
|
||||
|
||||
#define MPU_M_26 0x085
|
||||
#define MPU_N_26 0x0C
|
||||
#define MPU_FSEL_26 0x07
|
||||
#define MPU_M2_26 0x01
|
||||
|
||||
#define MPU_M_38P4_ES1 0x1FA
|
||||
#define MPU_N_38P4_ES1 0x32
|
||||
#define MPU_FSEL_38P4_ES1 0x03
|
||||
#define MPU_M2_38P4_ES1 0x01
|
||||
|
||||
#define MPU_M_38P4_ES2 0x271
|
||||
#define MPU_N_38P4_ES2 0x2F
|
||||
#define MPU_FSEL_38P4_ES2 0x03
|
||||
#define MPU_M2_38P4_ES2 0x01
|
||||
|
||||
#define MPU_M_38P4 0x14C
|
||||
#define MPU_N_38P4 0x2F
|
||||
#define MPU_FSEL_38P4 0x03
|
||||
#define MPU_M2_38P4 0x01
|
||||
|
||||
/* IVA DPLL */
|
||||
|
||||
#define IVA_M_12_ES1 0x07D
|
||||
#define IVA_N_12_ES1 0x05
|
||||
#define IVA_FSEL_12_ES1 0x07
|
||||
#define IVA_M2_12_ES1 0x01
|
||||
|
||||
#define IVA_M_12_ES2 0x0B4
|
||||
#define IVA_N_12_ES2 0x05
|
||||
#define IVA_FSEL_12_ES2 0x07
|
||||
#define IVA_M2_12_ES2 0x01
|
||||
|
||||
#define IVA_M_12 0x085
|
||||
#define IVA_N_12 0x05
|
||||
#define IVA_FSEL_12 0x07
|
||||
#define IVA_M2_12 0x01
|
||||
|
||||
#define IVA_M_13_ES1 0x0FA
|
||||
#define IVA_N_13_ES1 0x0C
|
||||
#define IVA_FSEL_13_ES1 0x03
|
||||
#define IVA_M2_13_ES1 0x01
|
||||
|
||||
#define IVA_M_13_ES2 0x168
|
||||
#define IVA_N_13_ES2 0x0C
|
||||
#define IVA_FSEL_13_ES2 0x03
|
||||
#define IVA_M2_13_ES2 0x01
|
||||
|
||||
#define IVA_M_13 0x10A
|
||||
#define IVA_N_13 0x0C
|
||||
#define IVA_FSEL_13 0x03
|
||||
#define IVA_M2_13 0x01
|
||||
|
||||
#define IVA_M_19P2_ES1 0x082
|
||||
#define IVA_N_19P2_ES1 0x09
|
||||
#define IVA_FSEL_19P2_ES1 0x07
|
||||
#define IVA_M2_19P2_ES1 0x01
|
||||
|
||||
#define IVA_M_19P2_ES2 0x0E1
|
||||
#define IVA_N_19P2_ES2 0x0B
|
||||
#define IVA_FSEL_19P2_ES2 0x06
|
||||
#define IVA_M2_19P2_ES2 0x01
|
||||
|
||||
#define IVA_M_19P2 0x14C
|
||||
#define IVA_N_19P2 0x17
|
||||
#define IVA_FSEL_19P2 0x03
|
||||
#define IVA_M2_19P2 0x01
|
||||
|
||||
#define IVA_M_26_ES1 0x07D
|
||||
#define IVA_N_26_ES1 0x0C
|
||||
#define IVA_FSEL_26_ES1 0x07
|
||||
#define IVA_M2_26_ES1 0x01
|
||||
|
||||
#define IVA_M_26_ES2 0x0B4
|
||||
#define IVA_N_26_ES2 0x0C
|
||||
#define IVA_FSEL_26_ES2 0x07
|
||||
#define IVA_M2_26_ES2 0x01
|
||||
|
||||
#define IVA_M_26 0x085
|
||||
#define IVA_N_26 0x0C
|
||||
#define IVA_FSEL_26 0x07
|
||||
#define IVA_M2_26 0x01
|
||||
|
||||
#define IVA_M_38P4_ES1 0x13F
|
||||
#define IVA_N_38P4_ES1 0x30
|
||||
#define IVA_FSEL_38P4_ES1 0x03
|
||||
#define IVA_M2_38P4_ES1 0x01
|
||||
|
||||
#define IVA_M_38P4_ES2 0x0E1
|
||||
#define IVA_N_38P4_ES2 0x17
|
||||
#define IVA_FSEL_38P4_ES2 0x06
|
||||
#define IVA_M2_38P4_ES2 0x01
|
||||
|
||||
#define IVA_M_38P4 0x14C
|
||||
#define IVA_N_38P4 0x2F
|
||||
#define IVA_FSEL_38P4 0x03
|
||||
#define IVA_M2_38P4 0x01
|
||||
|
||||
/* CORE DPLL */
|
||||
|
||||
#define CORE_M_12 0xA6
|
||||
#define CORE_N_12 0x05
|
||||
#define CORE_FSEL_12 0x07
|
||||
#define CORE_M2_12 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_12_ES1 0x19F
|
||||
#define CORE_N_12_ES1 0x0E
|
||||
#define CORE_FSL_12_ES1 0x03
|
||||
#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_13 0x14C
|
||||
#define CORE_N_13 0x0C
|
||||
#define CORE_FSEL_13 0x03
|
||||
#define CORE_M2_13 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_13_ES1 0x1B2
|
||||
#define CORE_N_13_ES1 0x10
|
||||
#define CORE_FSL_13_ES1 0x03
|
||||
#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_19P2 0x19F
|
||||
#define CORE_N_19P2 0x17
|
||||
#define CORE_FSEL_19P2 0x03
|
||||
#define CORE_M2_19P2 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_19P2_ES1 0x19F
|
||||
#define CORE_N_19P2_ES1 0x17
|
||||
#define CORE_FSL_19P2_ES1 0x03
|
||||
#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_26 0xA6
|
||||
#define CORE_N_26 0x0C
|
||||
#define CORE_FSEL_26 0x07
|
||||
#define CORE_M2_26 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_26_ES1 0x1B2
|
||||
#define CORE_N_26_ES1 0x21
|
||||
#define CORE_FSL_26_ES1 0x03
|
||||
#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_38P4 0x19F
|
||||
#define CORE_N_38P4 0x2F
|
||||
#define CORE_FSEL_38P4 0x03
|
||||
#define CORE_M2_38P4 0x01 /* M3 of 2 */
|
||||
|
||||
#define CORE_M_38P4_ES1 0x19F
|
||||
#define CORE_N_38P4_ES1 0x2F
|
||||
#define CORE_FSL_38P4_ES1 0x03
|
||||
#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
|
||||
|
||||
/* PER DPLL */
|
||||
|
||||
#define PER_M_12 0xD8
|
||||
#define PER_N_12 0x05
|
||||
#define PER_FSEL_12 0x07
|
||||
#define PER_M2_12 0x09
|
||||
|
||||
#define PER_M_13 0x1B0
|
||||
#define PER_N_13 0x0C
|
||||
#define PER_FSEL_13 0x03
|
||||
#define PER_M2_13 0x09
|
||||
|
||||
#define PER_M_19P2 0xE1
|
||||
#define PER_N_19P2 0x09
|
||||
#define PER_FSEL_19P2 0x07
|
||||
#define PER_M2_19P2 0x09
|
||||
|
||||
#define PER_M_26 0xD8
|
||||
#define PER_N_26 0x0C
|
||||
#define PER_FSEL_26 0x07
|
||||
#define PER_M2_26 0x09
|
||||
|
||||
#define PER_M_38P4 0xE1
|
||||
#define PER_N_38P4 0x13
|
||||
#define PER_FSEL_38P4 0x07
|
||||
#define PER_M2_38P4 0x09
|
||||
|
||||
#endif /* endif _CLOCKS_OMAP3_H_ */
|
||||
|
|
@ -0,0 +1,402 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H
|
||||
#define _CPU_H
|
||||
|
||||
/* Register offsets of common modules */
|
||||
/* Control */
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct ctrl {
|
||||
unsigned char res1[0xC0];
|
||||
unsigned short gpmc_nadv_ale; /* 0xC0 */
|
||||
unsigned short gpmc_noe; /* 0xC2 */
|
||||
unsigned short gpmc_nwe; /* 0xC4 */
|
||||
unsigned char res2[0x22A];
|
||||
unsigned int status; /* 0x2F0 */
|
||||
} ctrl_t;
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define CONTROL_STATUS 0x2F0
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* device type */
|
||||
#define DEVICE_MASK (0x7 << 8)
|
||||
#define SYSBOOT_MASK 0x1F
|
||||
#define TST_DEVICE 0x0
|
||||
#define EMU_DEVICE 0x1
|
||||
#define HS_DEVICE 0x2
|
||||
#define GP_DEVICE 0x3
|
||||
|
||||
/* GPMC CS3/cs4/cs6 not avaliable */
|
||||
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
|
||||
#define GPMC_CONFIG_CS0 0x60
|
||||
#define GPMC_CONFIG_CS6 0x150
|
||||
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
|
||||
#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
|
||||
#define GPMC_CONFIG_WP 0x10
|
||||
|
||||
#define GPMC_CONFIG_WIDTH 0x30
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct gpmc {
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned char res2[0x4];
|
||||
unsigned int irqstatus; /* 0x18 */
|
||||
unsigned int irqenable; /* 0x1C */
|
||||
unsigned char res3[0x20];
|
||||
unsigned int timeout_control; /* 0x40 */
|
||||
unsigned char res4[0xC];
|
||||
unsigned int config; /* 0x50 */
|
||||
unsigned int status; /* 0x54 */
|
||||
unsigned char res5[0x19C];
|
||||
unsigned int ecc_config; /* 0x1F4 */
|
||||
unsigned int ecc_control; /* 0x1F8 */
|
||||
unsigned int ecc_size_config; /* 0x1FC */
|
||||
unsigned int ecc1_result; /* 0x200 */
|
||||
unsigned int ecc2_result; /* 0x204 */
|
||||
unsigned int ecc3_result; /* 0x208 */
|
||||
unsigned int ecc4_result; /* 0x20C */
|
||||
unsigned int ecc5_result; /* 0x210 */
|
||||
unsigned int ecc6_result; /* 0x214 */
|
||||
unsigned int ecc7_result; /* 0x218 */
|
||||
unsigned int ecc8_result; /* 0x21C */
|
||||
unsigned int ecc9_result; /* 0x220 */
|
||||
} gpmc_t;
|
||||
|
||||
typedef struct gpmc_csx {
|
||||
unsigned int config1; /* 0x00 */
|
||||
unsigned int config2; /* 0x04 */
|
||||
unsigned int config3; /* 0x08 */
|
||||
unsigned int config4; /* 0x0C */
|
||||
unsigned int config5; /* 0x10 */
|
||||
unsigned int config6; /* 0x14 */
|
||||
unsigned int config7; /* 0x18 */
|
||||
unsigned int nand_cmd; /* 0x1C */
|
||||
unsigned int nand_adr; /* 0x20 */
|
||||
unsigned int nand_dat; /* 0x24 */
|
||||
} gpmc_csx_t;
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define GPMC_CONFIG1 0x00
|
||||
#define GPMC_CONFIG2 0x04
|
||||
#define GPMC_CONFIG3 0x08
|
||||
#define GPMC_CONFIG4 0x0C
|
||||
#define GPMC_CONFIG5 0x10
|
||||
#define GPMC_CONFIG6 0x14
|
||||
#define GPMC_CONFIG7 0x18
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* GPMC Mapping */
|
||||
#define FLASH_BASE 0x10000000 /* NOR flash, */
|
||||
/* aligned to 256 Meg */
|
||||
#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
|
||||
/* aligned to 64 Meg */
|
||||
#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
|
||||
/* aligned to 256 Meg */
|
||||
#define DEBUG_BASE 0x08000000 /* debug board */
|
||||
#define NAND_BASE 0x30000000 /* NAND addr */
|
||||
/* (actual size small port) */
|
||||
#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
|
||||
#define ONENAND_MAP 0x20000000 /* OneNand addr */
|
||||
/* (actual size small port) */
|
||||
/* SMS */
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct sms {
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned char res2[0x34];
|
||||
unsigned int rg_att0; /* 0x48 */
|
||||
unsigned char res3[0x84];
|
||||
unsigned int class_arb0; /* 0xD0 */
|
||||
} sms_t;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
|
||||
|
||||
/* SDRC */
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct sdrc_cs {
|
||||
unsigned int mcfg; /* 0x80 || 0xB0 */
|
||||
unsigned int mr; /* 0x84 || 0xB4 */
|
||||
unsigned char res1[0x4];
|
||||
unsigned int emr2; /* 0x8C || 0xBC */
|
||||
unsigned char res2[0x14];
|
||||
unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
|
||||
unsigned int manual; /* 0xA8 || 0xD8 */
|
||||
unsigned char res3[0x4];
|
||||
} sdrc_cs_t;
|
||||
|
||||
typedef struct sdrc_actim {
|
||||
unsigned int ctrla; /* 0x9C || 0xC4 */
|
||||
unsigned int ctrlb; /* 0xA0 || 0xC8 */
|
||||
} sdrc_actim_t;
|
||||
|
||||
typedef struct sdrc {
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned int status; /* 0x14 */
|
||||
unsigned char res2[0x28];
|
||||
unsigned int cs_cfg; /* 0x40 */
|
||||
unsigned int sharing; /* 0x44 */
|
||||
unsigned char res3[0x18];
|
||||
unsigned int dlla_ctrl; /* 0x60 */
|
||||
unsigned int dlla_status; /* 0x64 */
|
||||
unsigned int dllb_ctrl; /* 0x68 */
|
||||
unsigned int dllb_status; /* 0x6C */
|
||||
unsigned int power; /* 0x70 */
|
||||
unsigned char res4[0xC];
|
||||
sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
|
||||
} sdrc_t;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define DLLPHASE_90 (0x1 << 1)
|
||||
#define LOADDLL (0x1 << 2)
|
||||
#define ENADLL (0x1 << 3)
|
||||
#define DLL_DELAY_MASK 0xFF00
|
||||
#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
|
||||
|
||||
#define PAGEPOLICY_HIGH (0x1 << 0)
|
||||
#define SRFRONRESET (0x1 << 7)
|
||||
#define WAKEUPPROC (0x1 << 26)
|
||||
|
||||
#define DDR_SDRAM (0x1 << 0)
|
||||
#define DEEPPD (0x1 << 3)
|
||||
#define B32NOT16 (0x1 << 4)
|
||||
#define BANKALLOCATION (0x2 << 6)
|
||||
#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
|
||||
#define ADDRMUXLEGACY (0x1 << 19)
|
||||
#define CASWIDTH_10BITS (0x5 << 20)
|
||||
#define RASWIDTH_13BITS (0x2 << 24)
|
||||
#define BURSTLENGTH4 (0x2 << 0)
|
||||
#define CASL3 (0x3 << 4)
|
||||
#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
|
||||
#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
|
||||
#define ARE_ARCV_1 (0x1 << 0)
|
||||
#define ARCV (0x4e2 << 8) /* Autorefresh count */
|
||||
#define OMAP34XX_SDRC_CS0 0x80000000
|
||||
#define OMAP34XX_SDRC_CS1 0xA0000000
|
||||
#define CMD_NOP 0x0
|
||||
#define CMD_PRECHARGE 0x1
|
||||
#define CMD_AUTOREFRESH 0x2
|
||||
#define CMD_ENTR_PWRDOWN 0x3
|
||||
#define CMD_EXIT_PWRDOWN 0x4
|
||||
#define CMD_ENTR_SRFRSH 0x5
|
||||
#define CMD_CKE_HIGH 0x6
|
||||
#define CMD_CKE_LOW 0x7
|
||||
#define SOFTRESET (0x1 << 1)
|
||||
#define SMART_IDLE (0x2 << 3)
|
||||
#define REF_ON_IDLE (0x1 << 6)
|
||||
|
||||
/* timer regs offsets (32 bit regs) */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct gptimer {
|
||||
unsigned int tidr; /* 0x00 r */
|
||||
unsigned char res[0xc];
|
||||
unsigned int tiocp_cfg; /* 0x10 rw */
|
||||
unsigned int tistat; /* 0x14 r */
|
||||
unsigned int tisr; /* 0x18 rw */
|
||||
unsigned int tier; /* 0x1c rw */
|
||||
unsigned int twer; /* 0x20 rw */
|
||||
unsigned int tclr; /* 0x24 rw */
|
||||
unsigned int tcrr; /* 0x28 rw */
|
||||
unsigned int tldr; /* 0x2c rw */
|
||||
unsigned int ttgr; /* 0x30 rw */
|
||||
unsigned int twpc; /* 0x34 r*/
|
||||
unsigned int tmar; /* 0x38 rw*/
|
||||
unsigned int tcar1; /* 0x3c r */
|
||||
unsigned int tcicr; /* 0x40 rw */
|
||||
unsigned int tcar2; /* 0x44 r */
|
||||
} gptimer_t;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* enable sys_clk NO-prescale /1 */
|
||||
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
|
||||
|
||||
/* Watchdog */
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct watchdog {
|
||||
unsigned char res1[0x34];
|
||||
unsigned int wwps; /* 0x34 r */
|
||||
unsigned char res2[0x10];
|
||||
unsigned int wspr; /* 0x48 rw */
|
||||
} watchdog_t;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define WD_UNLOCK1 0xAAAA
|
||||
#define WD_UNLOCK2 0x5555
|
||||
|
||||
/* PRCM */
|
||||
#define PRCM_BASE 0x48004000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct prcm {
|
||||
unsigned int fclken_iva2; /* 0x00 */
|
||||
unsigned int clken_pll_iva2; /* 0x04 */
|
||||
unsigned char res1[0x1c];
|
||||
unsigned int idlest_pll_iva2; /* 0x24 */
|
||||
unsigned char res2[0x18];
|
||||
unsigned int clksel1_pll_iva2 ; /* 0x40 */
|
||||
unsigned int clksel2_pll_iva2; /* 0x44 */
|
||||
unsigned char res3[0x8bc];
|
||||
unsigned int clken_pll_mpu; /* 0x904 */
|
||||
unsigned char res4[0x1c];
|
||||
unsigned int idlest_pll_mpu; /* 0x924 */
|
||||
unsigned char res5[0x18];
|
||||
unsigned int clksel1_pll_mpu; /* 0x940 */
|
||||
unsigned int clksel2_pll_mpu; /* 0x944 */
|
||||
unsigned char res6[0xb8];
|
||||
unsigned int fclken1_core; /* 0xa00 */
|
||||
unsigned char res7[0xc];
|
||||
unsigned int iclken1_core; /* 0xa10 */
|
||||
unsigned int iclken2_core; /* 0xa14 */
|
||||
unsigned char res8[0x28];
|
||||
unsigned int clksel_core; /* 0xa40 */
|
||||
unsigned char res9[0xbc];
|
||||
unsigned int fclken_gfx; /* 0xb00 */
|
||||
unsigned char res10[0xc];
|
||||
unsigned int iclken_gfx; /* 0xb10 */
|
||||
unsigned char res11[0x2c];
|
||||
unsigned int clksel_gfx; /* 0xb40 */
|
||||
unsigned char res12[0xbc];
|
||||
unsigned int fclken_wkup; /* 0xc00 */
|
||||
unsigned char res13[0xc];
|
||||
unsigned int iclken_wkup; /* 0xc10 */
|
||||
unsigned char res14[0xc];
|
||||
unsigned int idlest_wkup; /* 0xc20 */
|
||||
unsigned char res15[0x1c];
|
||||
unsigned int clksel_wkup; /* 0xc40 */
|
||||
unsigned char res16[0xbc];
|
||||
unsigned int clken_pll; /* 0xd00 */
|
||||
unsigned char res17[0x1c];
|
||||
unsigned int idlest_ckgen; /* 0xd20 */
|
||||
unsigned char res18[0x1c];
|
||||
unsigned int clksel1_pll; /* 0xd40 */
|
||||
unsigned int clksel2_pll; /* 0xd44 */
|
||||
unsigned int clksel3_pll; /* 0xd48 */
|
||||
unsigned char res19[0xb4];
|
||||
unsigned int fclken_dss; /* 0xe00 */
|
||||
unsigned char res20[0xc];
|
||||
unsigned int iclken_dss; /* 0xe10 */
|
||||
unsigned char res21[0x2c];
|
||||
unsigned int clksel_dss; /* 0xe40 */
|
||||
unsigned char res22[0xbc];
|
||||
unsigned int fclken_cam; /* 0xf00 */
|
||||
unsigned char res23[0xc];
|
||||
unsigned int iclken_cam; /* 0xf10 */
|
||||
unsigned char res24[0x2c];
|
||||
unsigned int clksel_cam; /* 0xf40 */
|
||||
unsigned char res25[0xbc];
|
||||
unsigned int fclken_per; /* 0x1000 */
|
||||
unsigned char res26[0xc];
|
||||
unsigned int iclken_per; /* 0x1010 */
|
||||
unsigned char res27[0x2c];
|
||||
unsigned int clksel_per; /* 0x1040 */
|
||||
unsigned char res28[0xfc];
|
||||
unsigned int clksel1_emu; /* 0x1140 */
|
||||
} prcm_t;
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define CM_CLKSEL_CORE 0x48004a40
|
||||
#define CM_CLKSEL_GFX 0x48004b40
|
||||
#define CM_CLKSEL_WKUP 0x48004c40
|
||||
#define CM_CLKEN_PLL 0x48004d00
|
||||
#define CM_CLKSEL1_PLL 0x48004d40
|
||||
#define CM_CLKSEL1_EMU 0x48005140
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define PRM_BASE 0x48306000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct prm {
|
||||
unsigned char res1[0xd40];
|
||||
unsigned int clksel; /* 0xd40 */
|
||||
unsigned char res2[0x50c];
|
||||
unsigned int rstctrl; /* 0x1250 */
|
||||
unsigned char res3[0x1c];
|
||||
unsigned int clksrc_ctrl; /* 0x1270 */
|
||||
} prm_t;
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define PRM_RSTCTRL 0x48307250
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define SYSCLKDIV_1 (0x1 << 6)
|
||||
#define SYSCLKDIV_2 (0x1 << 7)
|
||||
|
||||
#define CLKSEL_GPT1 (0x1 << 0)
|
||||
|
||||
#define EN_GPT1 (0x1 << 0)
|
||||
#define EN_32KSYNC (0x1 << 2)
|
||||
|
||||
#define ST_WDT2 (0x1 << 5)
|
||||
|
||||
#define ST_MPU_CLK (0x1 << 0)
|
||||
|
||||
#define ST_CORE_CLK (0x1 << 0)
|
||||
|
||||
#define ST_PERIPH_CLK (0x1 << 1)
|
||||
|
||||
#define ST_IVA2_CLK (0x1 << 0)
|
||||
|
||||
#define RESETDONE (0x1 << 0)
|
||||
|
||||
#define TCLR_ST (0x1 << 0)
|
||||
#define TCLR_AR (0x1 << 1)
|
||||
#define TCLR_PRE (0x1 << 5)
|
||||
|
||||
/* SMX-APE */
|
||||
#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
|
||||
#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
|
||||
#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
|
||||
#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct pm {
|
||||
unsigned char res1[0x48];
|
||||
unsigned int req_info_permission_0; /* 0x48 */
|
||||
unsigned char res2[0x4];
|
||||
unsigned int read_permission_0; /* 0x50 */
|
||||
unsigned char res3[0x4];
|
||||
unsigned int wirte_permission_0; /* 0x58 */
|
||||
unsigned char res4[0x4];
|
||||
unsigned int addr_match_1; /* 0x58 */
|
||||
unsigned char res5[0x4];
|
||||
unsigned int req_info_permission_1; /* 0x68 */
|
||||
unsigned char res6[0x14];
|
||||
unsigned int addr_match_2; /* 0x80 */
|
||||
} pm_t;
|
||||
#endif /*__ASSEMBLY__ */
|
||||
|
||||
/* Permission values for registers -Full fledged permissions to all */
|
||||
#define UNLOCK_1 0xFFFFFFFF
|
||||
#define UNLOCK_2 0x00000000
|
||||
#define UNLOCK_3 0x0000FFFF
|
||||
|
||||
#define NOT_EARLY 0
|
||||
|
||||
/* I2C base */
|
||||
#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
|
||||
#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
|
||||
#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
|
||||
|
||||
#endif /* _CPU_H */
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _I2C_H_
|
||||
#define _I2C_H_
|
||||
|
||||
#define I2C_DEFAULT_BASE I2C_BASE1
|
||||
|
||||
#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
|
||||
#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
|
||||
#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
|
||||
#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
|
||||
#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
|
||||
#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
|
||||
#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
|
||||
#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
|
||||
#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
|
||||
#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
|
||||
#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
|
||||
#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
|
||||
#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
|
||||
#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
|
||||
#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
|
||||
|
||||
/* I2C masks */
|
||||
|
||||
/* I2C Interrupt Enable Register (I2C_IE): */
|
||||
#define I2C_IE_GC_IE (1 << 5)
|
||||
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
|
||||
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
|
||||
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
|
||||
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
|
||||
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
|
||||
|
||||
/* I2C Status Register (I2C_STAT): */
|
||||
|
||||
#define I2C_STAT_SBD (1 << 15) /* Single byte data */
|
||||
#define I2C_STAT_BB (1 << 12) /* Bus busy */
|
||||
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
|
||||
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
|
||||
#define I2C_STAT_AAS (1 << 9) /* Address as slave */
|
||||
#define I2C_STAT_GC (1 << 5)
|
||||
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
|
||||
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
|
||||
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
|
||||
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
|
||||
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
|
||||
|
||||
/* I2C Interrupt Code Register (I2C_INTCODE): */
|
||||
|
||||
#define I2C_INTCODE_MASK 7
|
||||
#define I2C_INTCODE_NONE 0
|
||||
#define I2C_INTCODE_AL 1 /* Arbitration lost */
|
||||
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
|
||||
#define I2C_INTCODE_ARDY 3 /* Register access ready */
|
||||
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
|
||||
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
|
||||
|
||||
/* I2C Buffer Configuration Register (I2C_BUF): */
|
||||
|
||||
#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
|
||||
#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
|
||||
|
||||
/* I2C Configuration Register (I2C_CON): */
|
||||
|
||||
#define I2C_CON_EN (1 << 15) /* I2C module enable */
|
||||
#define I2C_CON_BE (1 << 14) /* Big endian mode */
|
||||
#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
|
||||
#define I2C_CON_MST (1 << 10) /* Master/slave mode */
|
||||
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
|
||||
/* (master mode only) */
|
||||
#define I2C_CON_XA (1 << 8) /* Expand address */
|
||||
#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
|
||||
#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
|
||||
|
||||
/* I2C System Test Register (I2C_SYSTEST): */
|
||||
|
||||
#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
|
||||
#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
|
||||
#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
|
||||
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
|
||||
#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
|
||||
#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
|
||||
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
|
||||
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
|
||||
|
||||
#define I2C_SCLL_SCLL 0
|
||||
#define I2C_SCLL_SCLL_M 0xFF
|
||||
#define I2C_SCLL_HSSCLL 8
|
||||
#define I2C_SCLH_HSSCLL_M 0xFF
|
||||
#define I2C_SCLH_SCLH 0
|
||||
#define I2C_SCLH_SCLH_M 0xFF
|
||||
#define I2C_SCLH_HSSCLH 8
|
||||
#define I2C_SCLH_HSSCLH_M 0xFF
|
||||
|
||||
#define OMAP_I2C_STANDARD 100
|
||||
#define OMAP_I2C_FAST_MODE 400
|
||||
#define OMAP_I2C_HIGH_SPEED 3400
|
||||
|
||||
#define SYSTEM_CLOCK_12 12000
|
||||
#define SYSTEM_CLOCK_13 13000
|
||||
#define SYSTEM_CLOCK_192 19200
|
||||
#define SYSTEM_CLOCK_96 96000
|
||||
|
||||
#define I2C_IP_CLK SYSTEM_CLOCK_96
|
||||
#define I2C_PSC_MAX 0x0f
|
||||
#define I2C_PSC_MIN 0x00
|
||||
|
||||
#endif /* _I2C_H_ */
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
#define CS0 0x0
|
||||
#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef enum {
|
||||
STACKED = 0,
|
||||
IP_DDR = 1,
|
||||
COMBO_DDR = 2,
|
||||
IP_SDR = 3,
|
||||
} mem_t;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define EARLY_INIT 1
|
||||
|
||||
/* Slower full frequency range default timings for x32 operation*/
|
||||
#define SDP_SDRC_SHARING 0x00000100
|
||||
#define SDP_SDRC_MR_0_SDR 0x00000031
|
||||
|
||||
/* optimized timings good for current shipping parts */
|
||||
#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
|
||||
|
||||
#define DLL_OFFSET 0
|
||||
#define DLL_WRITEDDRCLKX2DIS 1
|
||||
#define DLL_ENADLL 1
|
||||
#define DLL_LOCKDLL 0
|
||||
#define DLL_DLLPHASE_72 0
|
||||
#define DLL_DLLPHASE_90 1
|
||||
|
||||
/* rkw - need to find of 90/72 degree recommendation for speed like before */
|
||||
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
|
||||
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
|
||||
|
||||
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
|
||||
* ACTIMA
|
||||
* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
|
||||
* TDPL (Twr) = 15/6 = 2.5 -> 3
|
||||
* TRRD = 12/6 = 2
|
||||
* TRCD = 18/6 = 3
|
||||
* TRP = 18/6 = 3
|
||||
* TRAS = 42/6 = 7
|
||||
* TRC = 60/6 = 10
|
||||
* TRFC = 72/6 = 12
|
||||
* ACTIMB
|
||||
* TCKE = 2
|
||||
* XSR = 120/6 = 20
|
||||
*/
|
||||
#define TDAL_165 6
|
||||
#define TDPL_165 3
|
||||
#define TRRD_165 2
|
||||
#define TRCD_165 3
|
||||
#define TRP_165 3
|
||||
#define TRAS_165 7
|
||||
#define TRC_165 10
|
||||
#define TRFC_165 21
|
||||
#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
|
||||
(TRAS_165 << 18) | (TRP_165 << 15) | \
|
||||
(TRCD_165 << 12) | (TRRD_165 << 9) | \
|
||||
(TDPL_165 << 6) | (TDAL_165))
|
||||
|
||||
#define TWTR_165 1
|
||||
#define TCKE_165 1
|
||||
#define TXP_165 5
|
||||
#define XSR_165 23
|
||||
#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
|
||||
(TXP_165 << 8) | (TWTR_165 << 16))
|
||||
|
||||
#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
|
||||
#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
|
||||
#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* STNOR - Intel Strata Flash
|
||||
* SMNAND - Samsung NAND
|
||||
* MPDB - H4 MPDB board
|
||||
* SBNOR - Sibley NOR
|
||||
* MNAND - Micron Large page x16 NAND
|
||||
* ONNAND - Samsung One NAND
|
||||
*
|
||||
* include/configs/file.h contains the defn - for all CS we are interested
|
||||
* #define OMAP34XX_GPMC_CSx PART
|
||||
* #define OMAP34XX_GPMC_CSx_SIZE Size
|
||||
* #define OMAP34XX_GPMC_CSx_MAP Map
|
||||
* Where:
|
||||
* x - CS number
|
||||
* PART - Part Name as defined above
|
||||
* SIZE - how big is the mapping to be
|
||||
* GPMC_SIZE_128M - 0x8
|
||||
* GPMC_SIZE_64M - 0xC
|
||||
* GPMC_SIZE_32M - 0xE
|
||||
* GPMC_SIZE_16M - 0xF
|
||||
* MAP - Map this CS to which address(GPMC address space)- Absolute address
|
||||
* >>24 before being used.
|
||||
*/
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define SMNAND_GPMC_CONFIG1 0x00000800
|
||||
#define SMNAND_GPMC_CONFIG2 0x00141400
|
||||
#define SMNAND_GPMC_CONFIG3 0x00141400
|
||||
#define SMNAND_GPMC_CONFIG4 0x0F010F01
|
||||
#define SMNAND_GPMC_CONFIG5 0x010C1414
|
||||
#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
|
||||
#define SMNAND_GPMC_CONFIG7 0x00000C44
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00001800
|
||||
#define M_NAND_GPMC_CONFIG2 0x00141400
|
||||
#define M_NAND_GPMC_CONFIG3 0x00141400
|
||||
#define M_NAND_GPMC_CONFIG4 0x0F010F01
|
||||
#define M_NAND_GPMC_CONFIG5 0x010C1414
|
||||
#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000C44
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x3
|
||||
#define STNOR_GPMC_CONFIG2 0x00151501
|
||||
#define STNOR_GPMC_CONFIG3 0x00060602
|
||||
#define STNOR_GPMC_CONFIG4 0x11091109
|
||||
#define STNOR_GPMC_CONFIG5 0x01141F1F
|
||||
#define STNOR_GPMC_CONFIG6 0x000004c4
|
||||
|
||||
#define SIBNOR_GPMC_CONFIG1 0x1200
|
||||
#define SIBNOR_GPMC_CONFIG2 0x001f1f00
|
||||
#define SIBNOR_GPMC_CONFIG3 0x00080802
|
||||
#define SIBNOR_GPMC_CONFIG4 0x1C091C09
|
||||
#define SIBNOR_GPMC_CONFIG5 0x01131F1F
|
||||
#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
|
||||
|
||||
#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
|
||||
#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
|
||||
#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
|
||||
#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
|
||||
#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
|
||||
#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
|
||||
|
||||
#define MPDB_GPMC_CONFIG1 0x00011000
|
||||
#define MPDB_GPMC_CONFIG2 0x001f1f01
|
||||
#define MPDB_GPMC_CONFIG3 0x00080803
|
||||
#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
|
||||
#define MPDB_GPMC_CONFIG5 0x041f1F1F
|
||||
#define MPDB_GPMC_CONFIG6 0x1F0F04C4
|
||||
|
||||
#define P2_GPMC_CONFIG1 0x0
|
||||
#define P2_GPMC_CONFIG2 0x0
|
||||
#define P2_GPMC_CONFIG3 0x0
|
||||
#define P2_GPMC_CONFIG4 0x0
|
||||
#define P2_GPMC_CONFIG5 0x0
|
||||
#define P2_GPMC_CONFIG6 0x0
|
||||
|
||||
#define ONENAND_GPMC_CONFIG1 0x00001200
|
||||
#define ONENAND_GPMC_CONFIG2 0x000F0F01
|
||||
#define ONENAND_GPMC_CONFIG3 0x00030301
|
||||
#define ONENAND_GPMC_CONFIG4 0x0F040F04
|
||||
#define ONENAND_GPMC_CONFIG5 0x010F1010
|
||||
#define ONENAND_GPMC_CONFIG6 0x1F060000
|
||||
|
||||
#define NET_GPMC_CONFIG1 0x00001000
|
||||
#define NET_GPMC_CONFIG2 0x001e1e01
|
||||
#define NET_GPMC_CONFIG3 0x00080300
|
||||
#define NET_GPMC_CONFIG4 0x1c091c09
|
||||
#define NET_GPMC_CONFIG5 0x04181f1f
|
||||
#define NET_GPMC_CONFIG6 0x00000FCF
|
||||
#define NET_GPMC_CONFIG7 0x00000f6c
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define PISMO1_NOR 1
|
||||
#define PISMO1_NAND 2
|
||||
#define PISMO2_CS0 3
|
||||
#define PISMO2_CS1 4
|
||||
#define PISMO1_ONENAND 5
|
||||
#define DBG_MPDB 6
|
||||
#define PISMO2_NAND_CS0 7
|
||||
#define PISMO2_NAND_CS1 8
|
||||
|
||||
/* make it readable for the gpmc_init */
|
||||
#define PISMO1_NOR_BASE FLASH_BASE
|
||||
#define PISMO1_NAND_BASE NAND_BASE
|
||||
#define PISMO2_CS0_BASE PISMO2_MAP1
|
||||
#define PISMO1_ONEN_BASE ONENAND_MAP
|
||||
#define DBG_MPDB_BASE DEBUG_BASE
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue