Nand boot: Add nand boot support for MPC8569mds board
This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu <yu.liu@freescale.com>
This commit is contained in:
Liu Yu
Scott Wood
parent
9b208ece0a
commit
674ef7bd02
1
MAKEALL
1
MAKEALL
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@ -404,6 +404,7 @@ LIST_85xx=" \
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MPC8568MDS \
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MPC8569MDS \
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MPC8569MDS_ATM \
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MPC8569MDS_NAND \
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MPC8572DS \
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MPC8572DS_36BIT \
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P2020DS \
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1
Makefile
1
Makefile
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@ -2490,6 +2490,7 @@ MPC8568MDS_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
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MPC8569MDS_ATM_config \
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MPC8569MDS_NAND_config \
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MPC8569MDS_config: unconfig
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@$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
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@ -23,4 +23,13 @@
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#
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# mpc8569mds board
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#
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ifndef NAND_SPL
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ifeq ($(CONFIG_MK_NAND), y)
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TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
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LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
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endif
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endif
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ifndef TEXT_BASE
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TEXT_BASE = 0xfff80000
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endif
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@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_64M, 1),
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256K, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#ifdef CONFIG_MK_NAND
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#define CONFIG_NAND_U_BOOT 1
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#define CONFIG_RAMBOOT_NAND 1
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#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
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#endif
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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@ -73,17 +79,30 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
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/* physical addr of CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
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/* PQII uses CONFIG_SYS_IMMR */
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#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
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#else
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#endif
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#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
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@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
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/*Chip select 0 - Flash*/
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#define CONFIG_SYS_BR0_PRELIM 0xfe000801
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#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7
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#define CONFIG_FLASH_BR_PRELIM 0xfe000801
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#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
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/*Chip select 1 - BCSR*/
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#define CONFIG_SYS_BR1_PRELIM 0xf8000801
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@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Chip select 3 - NAND */
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#ifndef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xFC000000
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#else
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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#endif
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/* NAND boot: 4K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
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#define CONFIG_SYS_NAND_U_BOOT_START \
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(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void);
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_RAMBOOT_NAND
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#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#endif
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/*
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* SDRAM on the LocalBus
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@ -437,10 +487,18 @@ extern unsigned long get_clock_freq(void);
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/*
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* Environment
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*/
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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@ -0,0 +1,133 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# Copyright 2009 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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NAND_SPL := y
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TEXT_BASE := 0xfff00000
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PAD_TO := 0xfff01000
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include $(TOPDIR)/config.mk
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LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
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LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
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AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
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nandobj := $(OBJTREE)/nand_spl/
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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all: $(obj).depend $(ALL)
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS)
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map \
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-o $(nandobj)u-boot-spl
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# create symbolic links for common files
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$(obj)cache.c:
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@rm -f $(obj)cache.c
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ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
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$(obj)cpu_init_early.c:
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@rm -f $(obj)cpu_init_early.c
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ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
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$(obj)cpu_init_nand.c:
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@rm -f $(obj)cpu_init_nand.c
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ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
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$(obj)fsl_law.c:
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@rm -f $(obj)fsl_law.c
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ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
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$(obj)law.c:
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@rm -f $(obj)law.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
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$(obj)nand_boot_fsl_elbc.c:
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@rm -f $(obj)nand_boot_fsl_elbc.c
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ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
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$(obj)nand_boot_fsl_elbc.c
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$(obj)ns16550.c:
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@rm -f $(obj)ns16550.c
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)resetvec.S:
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@rm -f $(obj)resetvec.S
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ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
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$(obj)fixed_ivor.S:
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@rm -f $(obj)fixed_ivor.S
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ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
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$(obj)start.S: $(obj)fixed_ivor.S
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@rm -f $(obj)start.S
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ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
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$(obj)tlb.c:
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@rm -f $(obj)tlb.c
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ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
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$(obj)tlb_table.c:
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@rm -f $(obj)tlb_table.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
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ifneq ($(OBJTREE), $(SRCTREE))
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$(obj)nand_boot.c:
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@rm -f $(obj)nand_boot.c
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ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
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endif
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#########################################################################
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$(obj)%.o: $(obj)%.S
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$(CC) $(AFLAGS) -c -o $@ $<
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$(obj)%.o: $(obj)%.c
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$(CC) $(CFLAGS) -c -o $@ $<
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,75 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <mpc85xx.h>
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#include <asm-ppc/io.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#define SYSCLK_66 66666666
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DECLARE_GLOBAL_DATA_PTR;
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void board_init_f(ulong bootflag)
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{
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uint plat_ratio, bus_clk, sys_clk;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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sys_clk = SYSCLK_66;
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plat_ratio = gur->porpllsr & 0x0000003e;
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plat_ratio >>= 1;
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bus_clk = plat_ratio * sys_clk;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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/* copy code to DDR and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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