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Add support for multiple PHYs.

This commit is contained in:
Marian Balakowicz 2005-10-28 22:30:33 +02:00
parent fe93483a0a
commit 63ff004c4f
60 changed files with 909 additions and 288 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
board/csb272/csb272.c
View File

@ -164,10 +164,15 @@ long initdram (int board_type)
int last_stage_init(void)
{
/* initialize the PHY */
miiphy_reset(CONFIG_PHY_ADDR);
miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
/* AUTO neg */
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* LEDs */
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
return 0; /* success */
}

12
board/csb472/csb472.c
View File

@ -132,10 +132,14 @@ long initdram (int board_type)
int last_stage_init(void)
{
/* initialize the PHY */
miiphy_reset(CONFIG_PHY_ADDR);
miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
/* AUTO neg */
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* LEDs */
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
return 0; /* success */
}

4
board/esd/common/misc.c
View File

@ -33,8 +33,8 @@ void lxt971_no_sleep(void)
{
unsigned short reg;
miiphy_read(CONFIG_PHY_ADDR, 0x10, &reg);
miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
reg &= ~0x0040; /* disable sleep mode */
miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
}
#endif /* CONFIG_LXT971_NO_SLEEP */

24
board/evb64260/eth.c
View File

@ -85,12 +85,17 @@ static const char ether_port_phy_addr[3]={0,1,2};
static const char ether_port_phy_addr[3]={4,5,6};
#endif
/* MII PHY access routines are common for all i/f, use gal_ent0 */
#define GT6426x_MII_DEVNAME "gal_enet0"
int gt6426x_miiphy_read(char *devname, unsigned char phy,
unsigned char reg, unsigned short *val);
static inline unsigned short
miiphy_read_ret(unsigned short phy, unsigned short reg)
{
unsigned short val;
miiphy_read(phy,reg,&val);
gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
return val;
}
@ -339,8 +344,8 @@ gt6426x_eth_disable(void *v)
MII utilities - write: write to an MII register via SMI
***************************************************************************/
int
miiphy_write(unsigned char phy, unsigned char reg,
unsigned short data)
gt6426x_miiphy_write(char *devname, unsigned char phy,
unsigned char reg, unsigned short data)
{
unsigned int temp= (reg<<21) | (phy<<16) | data;
@ -354,8 +359,8 @@ miiphy_write(unsigned char phy, unsigned char reg,
MII utilities - read: read from an MII register via SMI
***************************************************************************/
int
miiphy_read(unsigned char phy, unsigned char reg,
unsigned short *val)
gt6426x_miiphy_read(char *devname, unsigned char phy,
unsigned char reg, unsigned short *val)
{
unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
@ -444,7 +449,7 @@ check_phy_state(struct eth_dev_s *p)
if ((psr & 0x3) != want) {
printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
psr & 0x3, want);
miiphy_write(ether_port_phy_addr[p->dev],0,
miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
udelay(10000); /* the EVB's GT takes a while to notice phy
went down and up */
@ -490,7 +495,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
led 2: 0xc=link/rxact
led 3: 0x2=rxact (N/C)
strch: 0,2=30 ms, enable */
miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
/* 2.7ns port rise time */
/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
@ -792,6 +797,11 @@ gt6426x_eth_initialize(bd_t *bis)
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev->name,
gt6426x_miiphy_read, gt6426x_miiphy_write);
#endif
}
}
#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */

30
board/funkwerk/vovpn-gw/m88e6060.c
View File

@ -160,12 +160,12 @@ m88e6060_initialize( int devAddr )
/*** reset all phys into powerdown ************************************/
for (i=0, err=0; i<M88X_PHY_CNT; i++) {
err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
/* keep SpeedLSB, Duplex */
val &= 0x2100;
/* set SWReset, AnegEn, PwrDwn, RestartAneg */
val |= 0x9a00;
err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
}
if (err) {
printf( "%s [ERR] reset phys\n",_f );
@ -174,9 +174,9 @@ m88e6060_initialize( int devAddr )
/*** disable all ports ************************************************/
for (i=0, err=0; i<M88X_PRT_CNT; i++) {
err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
val &= 0xfffc;
err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
}
if (err) {
printf( "%s [ERR] disable ports\n",_f );
@ -187,33 +187,33 @@ m88e6060_initialize( int devAddr )
/* set switch mac addr */
#define ea eth_get_dev()->enetaddr
val = (ea[4] << 8) | ea[5];
err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
val = (ea[2] << 8) | ea[3];
err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
val = (ea[0] << 8) | ea[1];
#undef ea
val &= 0xfeff; /* clear DiffAddr */
err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
if (err) {
printf( "%s [ERR] switch mac address register\n",_f );
return( -1 );
}
/* !DiscardExcessive, MaxFrameSize, CtrMode */
err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
val &= 0xd870;
val |= 0x0500;
err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
if (err) {
printf( "%s [ERR] switch global control register\n",_f );
return( -1 );
}
/* LernDis off, ATUSize 1024, AgeTime 5min */
err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
val &= 0x000f;
val |= 0x2130;
err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
if (err) {
printf( "%s [ERR] atu control register\n",_f );
return( -1 );
@ -226,10 +226,10 @@ m88e6060_initialize( int devAddr )
}
while (p->reg != -1) {
err = 0;
err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
err += miiphy_write( devAddr+prtTab[i],p->reg,val );
err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
/* XXX what todo */
@ -245,10 +245,10 @@ m88e6060_initialize( int devAddr )
}
while (p->reg != -1) {
err = 0;
err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
val &= p->msk;
val |= p->val;
err += miiphy_write( devAddr+phyTab[i],p->reg,val );
err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
if (err) {
printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
/* XXX what todo */

2
board/funkwerk/vovpn-gw/vovpn-gw.c
View File

@ -198,7 +198,7 @@ void reset_phy (void)
iop->pdat |= 0x00080000;
for (i=0; i<100; i++) {
udelay(20000);
if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
break;
}
}

17
board/mpc8260ads/mpc8260ads.c
View File

@ -238,8 +238,9 @@ void reset_phy (void)
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
miiphy_write(CFG_PHY_ADDR, 16, 0x610);
miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
* Ethernet PHY is configured (by means of configuration pins)
@ -247,9 +248,15 @@ void reset_phy (void)
* to advertise all capabilities, including 100Mb/s, and
* restart autonegotiation.
*/
miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* Advertise all capabilities */
bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
/* Do not bypass Rx/Tx (de)scrambler */
bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}

11
board/mpc8560ads/mpc8560ads.c
View File

@ -237,9 +237,14 @@ void reset_phy (void)
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
miiphy_reset(0x0); /* reset PHY */
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* reset PHY */
miiphy_reset("FCC1 ETHERNET", 0x0);
/* change PHY address to 0x02 */
bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
bb_miiphy_write(NULL, 0x02, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}

4
board/mpl/mip405/mip405.c
View File

@ -731,12 +731,12 @@ int last_stage_init (void)
char *s;
mem_test_reloc();
/* write correct LED configuration */
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
printf ("Error writing to the PHY\n");
}
/* since LED/CFG2 is not connected on the -2,
* write to correct capability information */
if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
printf ("Error writing to the PHY\n");
}
print_mip405_rev ();

12
board/netphone/netphone.c
View File

@ -38,6 +38,11 @@
#include <watchdog.h>
#endif
int fec8xx_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/****************************************************************/
/* some sane bit macros */
@ -483,12 +488,13 @@ void reset_phys(void)
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}

12
board/netta/netta.c
View File

@ -35,6 +35,11 @@
#include <watchdog.h>
#endif
int fec8xx_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/****************************************************************/
/* some sane bit macros */
@ -431,12 +436,13 @@ void reset_phys(void)
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}

12
board/netta2/netta2.c
View File

@ -36,6 +36,11 @@
#include <watchdog.h>
#endif
int fec8xx_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/****************************************************************/
/* some sane bit macros */
@ -481,12 +486,13 @@ void reset_phys(void)
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}

11
board/sbc8560/sbc8560.c
View File

@ -223,9 +223,14 @@ void reset_phy (void)
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
miiphy_reset(0x0); /* reset PHY */
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* reset PHY */
miiphy_reset("FCC1 ETHERNET", 0x0);
/* change PHY address to 0x02 */
bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
bb_miiphy_write(NULL, 0x02, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}

11
board/stxgp3/stxgp3.c
View File

@ -239,9 +239,14 @@ reset_phy(void)
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
miiphy_reset(0x0); /* reset PHY */
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
/* reset PHY */
miiphy_reset("FCC1 ETHERNET", 0x0);
/* change PHY address to 0x02 */
bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
bb_miiphy_write(NULL, 0x02, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
#endif
}

6
board/stxxtc/stxxtc.c
View File

@ -481,12 +481,12 @@ void reset_phys(void)
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}

9
board/uc100/uc100.c
View File

@ -30,6 +30,8 @@
#include <i2c.h>
#include <miiphy.h>
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/*********************************************************************/
/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
@ -258,8 +260,11 @@ int misc_init_r (void)
*/
mii_init();
miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */
miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */
/* disable auto-negotiation, 100mbit, full-duplex */
fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
/* set LED's to Link, Transmit, Receive */
fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
return 0;
}

109
common/cmd_mii.c
View File

@ -41,19 +41,21 @@ uint last_data;
uint last_reg;
/*
* MII read/write
* MII device/info/read/write
*
* Syntax:
* mii read {addr} {reg}
* mii write {addr} {reg} {data}
* mii device {devname}
* mii info {addr}
* mii read {addr} {reg}
* mii write {addr} {reg} {data}
*/
int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
unsigned char addr, reg;
unsigned short data;
int rcode = 0;
char *devname;
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
@ -78,8 +80,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
data = simple_strtoul (argv[4], NULL, 16);
}
/* use current device */
devname = miiphy_get_current_dev();
/*
* check info/read/write.
* check device/read/write/list.
*/
if (op == 'i') {
unsigned char j, start, end;
@ -91,34 +96,43 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
start = addrlo; end = addrhi + 1;
start = addr; end = addr + 1;
} else {
start = 0; end = 32;
start = 0; end = 31;
}
for (j = start; j < end; j++) {
if (miiphy_info (j, &oui, &model, &rev) == 0) {
if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
printf ("PHY 0x%02X: "
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
j, oui, model, rev,
miiphy_speed (j),
miiphy_duplex (j) == FULL ? "FDX" : "HDX");
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
} else {
puts ("Error reading info from the PHY\n");
}
}
} else if (op == 'r') {
if (miiphy_read (addr, reg, &data) != 0) {
if (miiphy_read (devname, addr, reg, &data) != 0) {
puts ("Error reading from the PHY\n");
rcode = 1;
} else {
printf ("%04X\n", data & 0x0000FFFF);
}
printf ("%04X\n", data & 0x0000FFFF);
} else if (op == 'w') {
if (miiphy_write (addr, reg, data) != 0) {
if (miiphy_write (devname, addr, reg, data) != 0) {
puts ("Error writing to the PHY\n");
rcode = 1;
}
} else if (op == 'd') {
if (argc == 2)
miiphy_listdev ();
else
miiphy_set_current_dev (argv[2]);
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
@ -140,9 +154,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
mii, 5, 1, do_mii,
"mii - MII utility commands\n",
"info <addr> - display MII PHY info\n"
"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
"device - list available devices\n"
"mii device <devname> - set current device\n"
"mii info <addr> - display MII PHY info\n"
"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
);
#else /* ! CONFIG_TERSE_MII ================================================= */
@ -386,7 +402,7 @@ static int special_field(
return 0;
}
uint last_op;
char last_op[2];
uint last_data;
uint last_addr_lo;
uint last_addr_hi;
@ -412,11 +428,12 @@ static void extract_range(
/* ---------------------------------------------------------------- */
int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
char op[2];
unsigned char addrlo, addrhi, reglo, reghi;
unsigned char addr, reg;
unsigned short data;
int rcode = 0;
char *devname;
#ifdef CONFIG_8xx
mii_init ();
@ -426,7 +443,8 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* We use the last specified parameters, unless new ones are
* entered.
*/
op = last_op;
op[0] = last_op[0];
op[1] = last_op[1];
addrlo = last_addr_lo;
addrhi = last_addr_hi;
reglo = last_reg_lo;
@ -434,7 +452,12 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
data = last_data;
if ((flag & CMD_FLAG_REPEAT) == 0) {
op = argv[1][0];
op[0] = argv[1][0];
if (strlen(argv[1]) > 1)
op[1] = argv[1][1];
else
op[1] = '\0';
if (argc >= 3)
extract_range(argv[2], &addrlo, &addrhi);
if (argc >= 4)
@ -443,10 +466,13 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
data = simple_strtoul (argv[4], NULL, 16);
}
/* use current device */
devname = miiphy_get_current_dev();
/*
* check info/read/write.
*/
if (op == 'i') {
if (op[0] == 'i') {
unsigned char j, start, end;
unsigned int oui;
unsigned char model;
@ -462,22 +488,25 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
for (j = start; j <= end; j++) {
if (miiphy_info (j, &oui, &model, &rev) == 0) {
if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
printf("PHY 0x%02X: "
"OUI = 0x%04X, "
"Model = 0x%02X, "
"Rev = 0x%02X, "
"%3dbaseT, %s\n",
j, oui, model, rev,
miiphy_speed (j),
miiphy_duplex (j) == FULL ? "FDX" : "HDX");
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
} else {
puts ("Error reading info from the PHY\n");
}
}
} else if (op == 'r') {
} else if (op[0] == 'r') {
for (addr = addrlo; addr <= addrhi; addr++) {
for (reg = reglo; reg <= reghi; reg++) {
data = 0xffff;
if (miiphy_read (addr, reg, &data) != 0) {
if (miiphy_read (devname, addr, reg, &data) != 0) {
printf(
"Error reading from the PHY addr=%02x reg=%02x\n",
addr, reg);
@ -492,17 +521,17 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
if ((addrlo != addrhi) && (reglo != reghi))
printf("\n");
}
} else if (op == 'w') {
} else if (op[0] == 'w') {
for (addr = addrlo; addr <= addrhi; addr++) {
for (reg = reglo; reg <= reghi; reg++) {
if (miiphy_write (addr, reg, data) != 0) {
if (miiphy_write (devname, addr, reg, data) != 0) {
printf("Error writing to the PHY addr=%02x reg=%02x\n",
addr, reg);
rcode = 1;
}
}
}
} else if (op == 'd') {
} else if (strncmp(op, "du", 2) == 0) {
ushort regs[6];
int ok = 1;
if ((reglo > 5) || (reghi > 5)) {
@ -512,8 +541,8 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
return 1;
}
for (addr = addrlo; addr <= addrhi; addr++) {
for (reg = 0; reg < 6; reg++) {
if (miiphy_read(addr, reg, &regs[reg]) != 0) {
for (reg = reglo; reg < reghi + 1; reg++) {
if (miiphy_read(devname, addr, reg, &regs[reg]) != 0) {
ok = 0;
printf(
"Error reading from the PHY addr=%02x reg=%02x\n",
@ -525,6 +554,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
MII_dump_0_to_5(regs, reglo, reghi);
printf("\n");
}
} else if (strncmp(op, "de", 2) == 0) {
if (argc == 2)
miiphy_listdev ();
else
miiphy_set_current_dev (argv[2]);
} else {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
@ -533,7 +567,8 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
/*
* Save the parameters for repeats.
*/
last_op = op;
last_op[0] = op[0];
last_op[1] = op[1];
last_addr_lo = addrlo;
last_addr_hi = addrhi;
last_reg_lo = reglo;
@ -548,10 +583,12 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
mii, 5, 1, do_mii,
"mii - MII utility commands\n",
"info <addr> - display MII PHY info\n"
"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
"device - list available devices\n"
"mii device <devname> - set current device\n"
"mii info <addr> - display MII PHY info\n"
"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
"Addr and/or reg may be ranges, e.g. 2-7.\n"
);

6
common/miiphybb.c
View File

@ -121,7 +121,8 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
* Returns:
* 0 on success
*/
int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int j; /* counter */
@ -188,7 +189,8 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
* Returns:
* 0 on success
*/
int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
#ifndef CONFIG_EP8248

246
common/miiphyutil.c
View File

@ -30,6 +30,215 @@
#include <miiphy.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>
/* local debug macro */
#define MII_DEBUG
#undef MII_DEBUG
#undef debug
#ifdef MII_DEBUG
#define debug(fmt,args...) printf (fmt ,##args)
#else
#define debug(fmt,args...)
#endif /* MII_DEBUG */
struct mii_dev {
struct list_head link;
char *name;
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
};
static struct list_head mii_devs;
static struct mii_dev *current_mii;
/*****************************************************************************
*
* Register read and write MII access routines for the device <name>.
*/
void miiphy_register(char *name,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value))
{
struct list_head *entry;
struct mii_dev *new_dev;
struct mii_dev *miidev;
static int head_initialized = 0;
unsigned int name_len;
if (head_initialized == 0) {
INIT_LIST_HEAD(&mii_devs);
current_mii = NULL;
head_initialized = 1;
}
/* check if we have unique name */
list_for_each(entry, &mii_devs) {
miidev = list_entry(entry, struct mii_dev, link);
if (strcmp(miidev->name, name) == 0) {
printf("miiphy_register: non unique device name '%s'\n",
name);
return;
}
}
/* allocate memory */
name_len = strlen(name);
new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1);
if(new_dev == NULL) {
printf("miiphy_register: cannot allocate memory for '%s'\n",
name);
return;
}
memset(new_dev, 0, sizeof(struct mii_dev) + name_len);
/* initalize mii_dev struct fields */
INIT_LIST_HEAD(&new_dev->link);
new_dev->read = read;
new_dev->write = write;
new_dev->name = (char *)(new_dev + 1);
strncpy(new_dev->name, name, name_len);
new_dev->name[name_len] = '\0';
debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
new_dev->name, new_dev->read, new_dev->write);
/* add it to the list */
list_add_tail(&new_dev->link, &mii_devs);
if (!current_mii)
current_mii = new_dev;
}
int miiphy_set_current_dev(char *devname)
{
struct list_head *entry;
struct mii_dev *dev;
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
current_mii = dev;
return 0;
}
}
printf("No such device: %s\n", devname);
return 1;
}
char *miiphy_get_current_dev()
{
if (current_mii)
return current_mii->name;
return NULL;
}
/*****************************************************************************
*
* Read to variable <value> from the PHY attached to device <devname>,
* use PHY address <addr> and register <reg>.
*
* Returns:
* 0 on success
*/
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
struct list_head *entry;
struct mii_dev *dev;
int found_dev = 0;
int read_ret = 0;
if (!devname) {
printf("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
found_dev = 1;
read_ret = dev->read(devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
return ((found_dev) ? read_ret : 1);
}
/*****************************************************************************
*
* Write <value> to the PHY attached to device <devname>,
* use PHY address <addr> and register <reg>.
*
* Returns:
* 0 on success
*/
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
struct list_head *entry;
struct mii_dev *dev;
int found_dev = 0;
int write_ret = 0;
if (!devname) {
printf("NULL device name!\n");
return 1;
}
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
if (strcmp(devname, dev->name) == 0) {
found_dev = 1;
write_ret = dev->write(devname, addr, reg, value);
break;
}
}
if (found_dev == 0)
printf("No such device: %s\n", devname);
return ((found_dev) ? write_ret : 1);
}
/*****************************************************************************
*
* Print out list of registered MII capable devices.
*/
void miiphy_listdev(void)
{
struct list_head *entry;
struct mii_dev *dev;
puts("MII devices: ");
list_for_each(entry, &mii_devs) {
dev = list_entry(entry, struct mii_dev, link);
printf("'%s' ", dev->name);
}
puts("\n");
if (current_mii)
printf("Current device: '%s'\n", current_mii->name);
}
/*****************************************************************************
*
@ -42,14 +251,15 @@
* Returns:
* 0 on success
*/
int miiphy_info (unsigned char addr,
int miiphy_info (char *devname,
unsigned char addr,
unsigned int *oui,
unsigned char *model, unsigned char *rev)
{
unsigned int reg = 0;
unsigned short tmp;
if (miiphy_read (addr, PHY_PHYIDR2, &tmp) != 0) {
if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
#ifdef DEBUG
puts ("PHY ID register 2 read failed\n");
#endif
@ -65,7 +275,7 @@ int miiphy_info (unsigned char addr,
return (-1);
}
if (miiphy_read (addr, PHY_PHYIDR1, &tmp) != 0) {
if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
#ifdef DEBUG
puts ("PHY ID register 1 read failed\n");
#endif
@ -88,18 +298,18 @@ int miiphy_info (unsigned char addr,
* Returns:
* 0 on success
*/
int miiphy_reset (unsigned char addr)
int miiphy_reset (char *devname, unsigned char addr)
{
unsigned short reg;
int loop_cnt;
if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
#ifdef DEBUG
printf ("PHY status read failed\n");
#endif
return (-1);
}
if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) {
if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
#ifdef DEBUG
puts ("PHY reset failed\n");
#endif
@ -116,7 +326,7 @@ int miiphy_reset (unsigned char addr)
loop_cnt = 0;
reg = 0x8000;
while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
if (miiphy_read (addr, PHY_BMCR, &reg) != 0) {
if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
# ifdef DEBUG
puts ("PHY status read failed\n");
# endif
@ -137,12 +347,12 @@ int miiphy_reset (unsigned char addr)
*
* Determine the ethernet speed (10/100).
*/
int miiphy_speed (unsigned char addr)
int miiphy_speed (char *devname, unsigned char addr)
{
unsigned short reg;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if (reg != 0xFFFF) {
@ -154,14 +364,14 @@ int miiphy_speed (unsigned char addr)
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (addr, PHY_BMCR, &reg)) {
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY speed read failed, assuming 10bT\n");
return (_10BASET);
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
/* Get auto-negotiation results. */
if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN speed read failed, assuming 10bT\n");
return (_10BASET);
}
@ -185,12 +395,12 @@ int miiphy_speed (unsigned char addr)
*
* Determine full/half duplex.
*/
int miiphy_duplex (unsigned char addr)
int miiphy_duplex (char *devname, unsigned char addr)
{
unsigned short reg;
#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
if ( (reg != 0xFFFF) &&
@ -205,14 +415,14 @@ int miiphy_duplex (unsigned char addr)
#endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
if (miiphy_read (addr, PHY_BMCR, &reg)) {
if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
puts ("PHY duplex read failed, assuming half duplex\n");
return (HALF);
}
/* Check if auto-negotiation is on. */
if ((reg & PHY_BMCR_AUTON) != 0) {
/* Get auto-negotiation results. */
if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
puts ("PHY AN duplex read failed, assuming half duplex\n");
return (HALF);
}
@ -237,13 +447,13 @@ int miiphy_duplex (unsigned char addr)
*
* Determine link status
*/
int miiphy_link (unsigned char addr)
int miiphy_link (char *devname, unsigned char addr)
{
unsigned short reg;
/* dummy read; needed to latch some phys */
(void)miiphy_read(addr, PHY_BMSR, &reg);
if (miiphy_read (addr, PHY_BMSR, &reg)) {
(void)miiphy_read(devname, addr, PHY_BMSR, &reg);
if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
puts ("PHY_BMSR read failed, assuming no link\n");
return (0);
}

21
cpu/arm920t/at91rm9200/ether.c
View File

@ -23,6 +23,7 @@
#include <at91rm9200_net.h>
#include <net.h>
#include <miiphy.h>
/* ----- Ethernet Buffer definitions ----- */
@ -150,7 +151,6 @@ UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
return TRUE;
}
int eth_init (bd_t * bd)
{
int ret;
@ -265,8 +265,9 @@ void eth_halt (void)
{
};
#if (CONFIG_COMMANDS & CFG_CMD_MII)
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
int at91rm9200_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, reg, value);
@ -274,14 +275,24 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
return 0;
}
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
int at91rm9200_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacWritePhy (p_mac, reg, &value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
int at91rm9200_miiphy_initialize(bd_t *bis)
{
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
#endif
return 0;
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */

18
cpu/mcf52x2/fec.c
View File

@ -519,7 +519,8 @@ void mii_init (void)
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
int mcf52x2_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
@ -537,7 +538,8 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
return 0;
}
int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
int mcf52x2_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
@ -554,5 +556,15 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
#endif /* CFG_CMD_NET, FEC_ENET */
int mcf52x2_miiphy_initialize(bd_t *bis)
{
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
#endif
#endif
return 0;
}

15
cpu/mips/au1x00_eth.c
View File

@ -63,6 +63,10 @@
#include <asm/io.h>
#include <asm/au1x00.h>
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#include <miiphy.h>
#endif
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
@ -233,11 +237,17 @@ int au1x00_enet_initialize(bd_t *bis){
eth_register(dev);
#if (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev->name,
au1x00_miiphy_read, au1x00_miiphy_write);
#endif
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
int au1x00_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
@ -269,7 +279,8 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
return 0;
}
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
int au1x00_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);

61
cpu/mpc5xxx/fec.c
View File

@ -19,9 +19,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC5xxx_FEC)
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#if (DEBUG & 0x60)
static void tfifo_print(mpc5xxx_fec_priv *fec);
static void rfifo_print(mpc5xxx_fec_priv *fec);
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
#endif /* DEBUG */
#if (DEBUG & 0x40)
@ -35,9 +39,12 @@ typedef struct {
uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc5xxx_fec_phydump (void)
static void mpc5xxx_fec_phydump (char *devname)
{
uint16 phyStatus, i;
uint8 phyAddr = CONFIG_PHY_ADDR;
@ -55,7 +62,7 @@ static void mpc5xxx_fec_phydump (void)
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
miiphy_read(phyAddr, i, &phyStatus);
miiphy_read(devname, phyAddr, i, &phyStatus);
printf("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
@ -457,7 +464,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
/*
* Reset PHY, then delay 300ns
*/
miiphy_write(phyAddr, 0x0, 0x8000);
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
if (fec->xcv_type == MII10) {
@ -467,11 +474,11 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2)
printf("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read(phyAddr, 0x1, &phyStatus);
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
/*
miiphy_write(fec, phyAddr, 0x0, 0x0100);
miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
*/
miiphy_write(phyAddr, 0x0, 0x0180);
miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
@ -482,7 +489,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
#endif
break;
}
miiphy_read(phyAddr, 0x1, &phyStatus);
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("=");
#endif
@ -495,7 +502,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
printf("failed. Link is down.\n");
break;
}
miiphy_read(phyAddr, 0x1, &phyStatus);
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("+");
#endif
@ -508,12 +515,12 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write(phyAddr, 0x4, 0x01e1);
miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
miiphy_write(phyAddr, 0x0, 0x1200);
miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
@ -529,7 +536,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
return -1;
}
if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
@ -546,7 +553,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump ();
mpc5xxx_fec_phydump (dev->name);
#endif
@ -631,7 +638,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
#if (DEBUG & 0x60)
/********************************************************************/
static void tfifo_print(mpc5xxx_fec_priv *fec)
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
@ -639,7 +646,7 @@ static void tfifo_print(mpc5xxx_fec_priv *fec)
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
miiphy_read(phyAddr, 0x1, &phyStatus);
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
@ -655,7 +662,7 @@ static void tfifo_print(mpc5xxx_fec_priv *fec)
}
}
static void rfifo_print(mpc5xxx_fec_priv *fec)
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
@ -663,7 +670,7 @@ static void rfifo_print(mpc5xxx_fec_priv *fec)
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
miiphy_read(phyAddr, 0x1, &phyStatus);
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
@ -694,7 +701,7 @@ static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
tfifo_print(fec);
tfifo_print(dev->name, fec);
#endif
/*
@ -737,7 +744,7 @@ static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
*/
if (fec->xcv_type != SEVENWIRE) {
uint16 phyStatus;
miiphy_read(0, 0x1, &phyStatus);
miiphy_read(dev->name, 0, 0x1, &phyStatus);
}
/*
@ -745,11 +752,11 @@ static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
*/
#if (DEBUG & 0x20)
tfifo_print(fec);
tfifo_print(dev->name, fec);
#endif
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#if (DEBUG & 0x20)
tfifo_print(fec);
tfifo_print(dev->name, fec);
#endif
#if (DEBUG & 0x8)
printf( "+" );
@ -896,6 +903,11 @@ int mpc5xxx_fec_initialize(bd_t * bis)
sprintf(dev->name, "FEC ETHERNET");
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
fec5xxx_miiphy_read, fec5xxx_miiphy_write);
#endif
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
@ -912,12 +924,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
}
mpc5xxx_fec_init_phy(dev, bis);
return 1;
}
/* MII-interface related functions */
/********************************************************************/
int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
@ -959,7 +972,7 @@ int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
}
/********************************************************************/
int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */

60
cpu/mpc8220/fec.c
View File

@ -18,11 +18,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC8220_FEC)
/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#ifdef DEBUG
static void tfifo_print (mpc8220_fec_priv * fec);
static void rfifo_print (mpc8220_fec_priv * fec);
static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
#endif /* DEBUG */
#ifdef DEBUG
@ -36,9 +38,12 @@ typedef struct {
u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data);
/********************************************************************/
#ifdef DEBUG
static void mpc8220_fec_phydump (void)
static void mpc8220_fec_phydump (char *devname)
{
u16 phyStatus, i;
u8 phyAddr = CONFIG_PHY_ADDR;
@ -56,7 +61,7 @@ static void mpc8220_fec_phydump (void)
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
miiphy_read (phyAddr, i, &phyStatus);
miiphy_read (devname, phyAddr, i, &phyStatus);
printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
@ -400,7 +405,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
/*
* Reset PHY, then delay 300ns
*/
miiphy_write (phyAddr, 0x0, 0x8000);
miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
udelay (1000);
if (fec->xcv_type == MII10) {
@ -410,11 +415,11 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
#ifdef DEBUG
printf ("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read (phyAddr, 0x1, &phyStatus);
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
/*
miiphy_write(fec, phyAddr, 0x0, 0x0100);
*/
miiphy_write (phyAddr, 0x0, 0x0180);
miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
@ -425,7 +430,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
#endif
break;
}
miiphy_read (phyAddr, 0x1, &phyStatus);
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("=");
#endif
@ -438,7 +443,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
printf ("failed. Link is down.\n");
break;
}
miiphy_read (phyAddr, 0x1, &phyStatus);
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("+");
#endif
@ -451,12 +456,12 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write (phyAddr, 0x4, 0x01e1);
miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
miiphy_write (phyAddr, 0x0, 0x1200);
miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
@ -472,7 +477,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
return -1;
}
if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) !=
0) {
#ifdef DEBUG
printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
@ -495,7 +500,7 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
mpc8220_fec_phydump ();
mpc8220_fec_phydump (dev->name);
#endif
/*
@ -518,7 +523,7 @@ static void mpc8220_fec_halt (struct eth_device *dev)
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
mpc8220_fec_phydump ();
mpc8220_fec_phydump (dev->name);
#endif
/*
@ -573,7 +578,7 @@ static void mpc8220_fec_halt (struct eth_device *dev)
#ifdef DEBUG
/********************************************************************/
static void tfifo_print (mpc8220_fec_priv * fec)
static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
@ -581,7 +586,7 @@ static void tfifo_print (mpc8220_fec_priv * fec)
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
miiphy_read (phyAddr, 0x1, &phyStatus);
miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
@ -597,7 +602,7 @@ static void tfifo_print (mpc8220_fec_priv * fec)
}
}
static void rfifo_print (mpc8220_fec_priv * fec)
static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
@ -605,7 +610,7 @@ static void rfifo_print (mpc8220_fec_priv * fec)
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
miiphy_read (phyAddr, 0x1, &phyStatus);
miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
@ -636,7 +641,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
#ifdef DEBUG
printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
tfifo_print (fec);
tfifo_print (dev->name, fec);
#endif
/*
@ -680,7 +685,7 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
if (fec->xcv_type != SEVENWIRE) {
u16 phyStatus;
miiphy_read (0, 0x1, &phyStatus);
miiphy_read (dev->name, 0, 0x1, &phyStatus);
}
/*
@ -688,13 +693,13 @@ static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
*/
#ifdef DEBUG
tfifo_print (fec);
tfifo_print (dev->name, fec);
#endif
DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#ifdef DEBUG
tfifo_print (fec);
tfifo_print (dev->name, fec);
#endif
#ifdef DEBUG
@ -842,6 +847,11 @@ int mpc8220_fec_initialize (bd_t * bis)
sprintf (dev->name, "FEC ETHERNET");
eth_register (dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
fec8220_miiphy_read, fec8220_miiphy_write);
#endif
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
@ -875,7 +885,7 @@ int mpc8220_fec_initialize (bd_t * bis)
/* MII-interface related functions */
/********************************************************************/
int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */
@ -919,7 +929,7 @@ int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
}
/********************************************************************/
int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */

10
cpu/mpc8260/ether_fcc.c
View File

@ -47,6 +47,10 @@
#include <config.h>
#include <net.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#include <miiphy.h>
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
@ -386,6 +390,12 @@ int fec_initialize(bd_t *bis)
dev->recv = fec_recv;
eth_register(dev);
#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
&& defined(CONFIG_BITBANGMII)
miiphy_register(dev->name,
bb_miiphy_read, bb_miiphy_write);
#endif
}
return 1;

10
cpu/mpc85xx/ether_fcc.c
View File

@ -48,6 +48,10 @@
#include <config.h>
#include <net.h>
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#include <miiphy.h>
#endif
#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
@ -451,6 +455,12 @@ int fec_initialize(bd_t *bis)
dev->recv = fec_recv;
eth_register(dev);
#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
&& defined(CONFIG_BITBANGMII)
miiphy_register(dev->name,
bb_miiphy_read, bb_miiphy_write);
#endif
}
return 1;

25
cpu/mpc8xx/fec.c
View File

@ -46,6 +46,11 @@
#if defined(WANT_MII)
#include <miiphy.h>
#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#endif
#if defined(CONFIG_RMII) && !defined(WANT_MII)
@ -56,6 +61,11 @@
static int mii_discover_phy(struct eth_device *dev);
#endif
int fec8xx_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
static struct ether_fcc_info_s
{
int ether_index;
@ -169,6 +179,11 @@ int fec_initialize(bd_t *bis)
dev->recv = fec_recv;
eth_register(dev);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev->name,
fec8xx_miiphy_read, fec8xx_miiphy_write);
#endif
}
return 1;
}
@ -712,7 +727,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* adapt the RMII speed to the speed of the phy
*/
if (miiphy_speed (efis->actual_phy_addr) == _100BASET) {
if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
fec_100Mbps (dev);
} else {
fec_10Mbps (dev);
@ -723,7 +738,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* adapt to the half/full speed settings
*/
if (miiphy_duplex (efis->actual_phy_addr) == FULL) {
if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
fec_full_duplex (dev);
} else {
fec_half_duplex (dev);
@ -969,7 +984,8 @@ void mii_init (void)
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
int fec8xx_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
@ -985,7 +1001,8 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
return 0;
}
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
int fec8xx_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG

57
cpu/ppc4xx/4xx_enet.c
View File

@ -142,7 +142,6 @@ static uint32_t mal_ier;
struct eth_device *emac0_dev = NULL;
#endif
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@ -154,6 +153,11 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
extern int phy_setup_aneg (char *devname, unsigned char addr);
extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/*-----------------------------------------------------------------------------+
| ppc_4xx_eth_halt
@ -191,9 +195,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
return;
}
extern int phy_setup_aneg (unsigned char addr);
extern int miiphy_reset (unsigned char addr);
#if defined (CONFIG_440GX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
@ -447,7 +448,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
miiphy_reset (reg);
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX)
#if defined(CONFIG_CIS8201_PHY)
@ -457,9 +458,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
*/
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
miiphy_write (reg, 23, 0x1300);
miiphy_write (dev->name, reg, 23, 0x1300);
#else
miiphy_write (reg, 23, 0x1000);
miiphy_write (dev->name, reg, 23, 0x1000);
#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
@ -467,26 +468,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
* This work around (provided by Vitesse) changes
* the default timer convergence from 8ms to 12ms
*/
miiphy_write (reg, 0x1f, 0x2a30);
miiphy_write (reg, 0x08, 0x0200);
miiphy_write (reg, 0x1f, 0x52b5);
miiphy_write (reg, 0x02, 0x0004);
miiphy_write (reg, 0x01, 0x0671);
miiphy_write (reg, 0x00, 0x8fae);
miiphy_write (reg, 0x1f, 0x2a30);
miiphy_write (reg, 0x08, 0x0000);
miiphy_write (reg, 0x1f, 0x0000);
miiphy_write (dev->name, reg, 0x1f, 0x2a30);
miiphy_write (dev->name, reg, 0x08, 0x0200);
miiphy_write (dev->name, reg, 0x1f, 0x52b5);
miiphy_write (dev->name, reg, 0x02, 0x0004);
miiphy_write (dev->name, reg, 0x01, 0x0671);
miiphy_write (dev->name, reg, 0x00, 0x8fae);
miiphy_write (dev->name, reg, 0x1f, 0x2a30);
miiphy_write (dev->name, reg, 0x08, 0x0000);
miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (reg);
phy_setup_aneg (dev->name, reg);
udelay (1000);
}
#endif /* defined(CONFIG_PHY_RESET) */
miiphy_read (reg, PHY_BMSR, &reg_short);
miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
@ -508,7 +509,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
putc ('.');
}
udelay (1000); /* 1 ms */
miiphy_read (reg, PHY_BMSR, &reg_short);
miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
}
puts (" done\n");
@ -516,8 +517,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
}
#endif /* #ifndef CONFIG_CS8952_PHY */
speed = miiphy_speed (reg);
duplex = miiphy_duplex (reg);
speed = miiphy_speed (dev->name, reg);
duplex = miiphy_duplex (dev->name, reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
@ -1470,6 +1471,10 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#else
emac0_dev = dev;
#endif
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register (dev->name,
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
} /* end for each supported device */
return (1);
@ -1505,6 +1510,16 @@ int eth_rx(void)
{
return (ppc_4xx_eth_rx(emac0_dev));
}
int emac4xx_miiphy_initialize (bd_t * bis)
{
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register ("ppc_4xx_eth0",
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
return 0;
}
#endif /* !defined(CONFIG_NET_MULTI) */
#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */

20
cpu/ppc4xx/miiphy.c
View File

@ -55,14 +55,14 @@
/* Dump out to the screen PHY regs */
/***********************************************************/
void miiphy_dump (unsigned char addr)
void miiphy_dump (char *devname, unsigned char addr)
{
unsigned long i;
unsigned short data;
for (i = 0; i < 0x1A; i++) {
if (miiphy_read (addr, i, &data)) {
if (miiphy_read (devname, addr, i, &data)) {
printf ("read error for reg %lx\n", i);
return;
}
@ -79,21 +79,21 @@ void miiphy_dump (unsigned char addr)
/***********************************************************/
/* (Re)start autonegotiation */
/***********************************************************/
int phy_setup_aneg (unsigned char addr)
int phy_setup_aneg (char *devname, unsigned char addr)
{
unsigned short ctl, adv;
/* Setup standard advertise */
miiphy_read (addr, PHY_ANAR, &adv);
miiphy_read (devname, addr, PHY_ANAR, &adv);
adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
PHY_ANLPAR_10);
miiphy_write (addr, PHY_ANAR, adv);
miiphy_write (devname, addr, PHY_ANAR, adv);
/* Start/Restart aneg */
miiphy_read (addr, PHY_BMCR, &ctl);
miiphy_read (devname, addr, PHY_BMCR, &ctl);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
miiphy_write (addr, PHY_BMCR, ctl);
miiphy_write (devname, addr, PHY_BMCR, ctl);
return 0;
}
@ -142,7 +142,8 @@ unsigned int miiphy_getemac_offset (void)
}
int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
int emac4xx_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;
@ -207,7 +208,8 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
/* write a phy reg and return the value with a rc */
/***********************************************************/
int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
int emac4xx_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;

118
drivers/eepro100.c
View File

@ -26,6 +26,7 @@
#include <net.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#undef DEBUG
@ -271,49 +272,124 @@ static inline void OUTL (struct eth_device *dev, int command, u_long addr)
*(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
}
#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
static inline int INL (struct eth_device *dev, u_long addr)
{
return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
}
int miiphy_read (unsigned char addr,
unsigned char reg,
unsigned short *value)
static int get_phyreg (struct eth_device *dev, unsigned char addr,
unsigned char reg, unsigned short *value)
{
int cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
struct eth_device *dev = eth_get_dev ();
int cmd;
int timeout = 50;
/* read requested data */
cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
OUTL (dev, cmd, SCBCtrlMDI);
do {
udelay(1000);
cmd = INL (dev, SCBCtrlMDI);
} while (!(cmd & (1 << 28)));
} while (!(cmd & (1 << 28)) && (--timeout));
if (timeout == 0)
return -1;
*value = (unsigned short) (cmd & 0xffff);
return 0;
}
int miiphy_write (unsigned char addr,
unsigned char reg,
unsigned short value)
static int set_phyreg (struct eth_device *dev, unsigned char addr,
unsigned char reg, unsigned short value)
{
int cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
struct eth_device *dev = eth_get_dev ();
int cmd;
int timeout = 50;
/* write requested data */
cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
OUTL (dev, cmd | value, SCBCtrlMDI);
while (!(INL (dev, SCBCtrlMDI) & (1 << 28)));
while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
udelay(1000);
if (timeout == 0)
return -1;
return 0;
}
#endif /* (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
/* Wait for the chip get the command.
*/
/* Check if given phyaddr is valid, i.e. there is a PHY connected.
* Do this by checking model value field from ID2 register.
*/
static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
{
struct eth_device *dev;
unsigned short value;
unsigned char model;
dev = eth_get_dev_by_name(devname);
if (dev == NULL) {
printf("%s: no such device\n", devname);
return NULL;
}
/* read id2 register */
if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) {
printf("%s: mii read timeout!\n", devname);
return NULL;
}
/* get model */
model = (unsigned char)((value >> 4) & 0x003f);
if (model == 0) {
printf("%s: no PHY at address %d\n", devname, addr);
return NULL;
}
return dev;
}
static int eepro100_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
struct eth_device *dev;
dev = verify_phyaddr(devname, addr);
if (dev == NULL)
return -1;
if (get_phyreg(dev, addr, reg, value) != 0) {
printf("%s: mii read timeout!\n", devname);
return -1;
}
return 0;
}
static int eepro100_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct eth_device *dev;
dev = verify_phyaddr(devname, addr);
if (dev == NULL)
return -1;
if (set_phyreg(dev, addr, reg, value) != 0) {
printf("%s: mii write timeout!\n", devname);
return -1;
}
return 0;
}
#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
/* Wait for the chip get the command.
*/
static int wait_for_eepro100 (struct eth_device *dev)
{
int i;
@ -386,6 +462,12 @@ int eepro100_initialize (bd_t * bis)
eth_register (dev);
#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
/* register mii command access routines */
miiphy_register(dev->name,
eepro100_miiphy_read, eepro100_miiphy_write);
#endif
card_number++;
/* Set the latency timer for value.

18
drivers/ns7520_eth.c
View File

@ -767,8 +767,8 @@ enum mii_status {
/**
* Read a 16-bit value from an MII register.
*/
extern int miiphy_read(unsigned char const addr, unsigned char const reg,
unsigned short *const value)
extern int ns7520_miiphy_read(char *devname, unsigned char const addr,
unsigned char const reg, unsigned short *const value)
{
int ret = MII_STATUS_FAILURE;
@ -813,8 +813,8 @@ extern int miiphy_read(unsigned char const addr, unsigned char const reg,
/**
* Write a 16-bit value to an MII register.
*/
extern int miiphy_write(unsigned char const addr, unsigned char const reg,
unsigned short const value)
extern int ns7520_miiphy_write(char *devname, unsigned char const addr,
unsigned char const reg, unsigned short const value)
{
int ret = MII_STATUS_FAILURE;
@ -847,3 +847,13 @@ extern int miiphy_write(unsigned char const addr, unsigned char const reg,
}
#endif /* defined(CONFIG_MII) */
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
int ns7520_miiphy_initialize(bd_t *bis)
{
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
#if defined(CONFIG_MII)
miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
#endif
#endif
return 0;
}

24
drivers/tsec.c
View File

@ -21,8 +21,9 @@
#if defined(CONFIG_TSEC_ENET)
#include "tsec.h"
#include "miiphy.h"
#define TX_BUF_CNT 2
#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
@ -120,6 +121,10 @@ struct phy_info * get_phy_info(struct eth_device *dev);
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
static int tsec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
@ -169,6 +174,11 @@ int tsec_initialize(bd_t *bis, int index, char *devname)
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
&& !defined(BITBANGMII)
miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
#endif
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
@ -1058,7 +1068,8 @@ static void relocate_cmds(void)
}
#ifndef CONFIG_BITBANGMII
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
&& !defined(BITBANGMII)
struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
{
@ -1078,7 +1089,8 @@ struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
* Returns:
* 0 on success
*/
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
unsigned short ret;
struct tsec_private *priv = get_priv_for_phy(addr);
@ -1100,7 +1112,8 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
* Returns:
* 0 on success
*/
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
static int tsec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct tsec_private *priv = get_priv_for_phy(addr);
@ -1114,6 +1127,7 @@ int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
return 0;
}
#endif /* CONFIG_BITBANGMII */
#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
&& !defined(BITBANGMII) */
#endif /* CONFIG_TSEC_ENET */

1
include/configs/Alaska8220.h
View File

@ -90,6 +90,7 @@
CFG_CMD_SNTP )
#define CONFIG_NET_MULTI
#define CONFIG_MII
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

1
include/configs/IAD210.h
View File

@ -88,6 +88,7 @@
# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY 1
# define CONFIG_FEC_UTOPIA 1
# define CONFIG_ETHADDR 08:00:06:26:A2:6D

1
include/configs/ICU862.h
View File

@ -85,6 +85,7 @@
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define CONFIG_MII 1
#if 1
#define CFG_DISCOVER_PHY 1
#else

2
include/configs/IceCube.h
View File

@ -71,6 +71,7 @@
#define CFG_XLB_PIPELINING 1
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
@ -79,6 +80,7 @@
#else /* MPC5100 */
#define CONFIG_MII 1
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif

1
include/configs/KUP4K.h
View File

@ -141,6 +141,7 @@
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
#define CFG_DISCOVER_PHY
#define CONFIG_MII
#if 0
#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */

1
include/configs/KUP4X.h
View File

@ -150,6 +150,7 @@
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
#define CFG_DISCOVER_PHY
#define CONFIG_MII
#if 0
#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */

2
include/configs/MPC8560ADS.h
View File

@ -43,7 +43,9 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */

1
include/configs/PM520.h
View File

@ -72,6 +72,7 @@
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X

2
include/configs/PM854.h
View File

@ -235,7 +235,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_EEPRO100
#define CONFIG_E1000
#undef CONFIG_TULIP

1
include/configs/QS860T.h
View File

@ -56,6 +56,7 @@
#define CONFIG_QS860T 1 /* ...on a QS860T module */
#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
#define CONFIG_MII
#define FEC_INTERRUPT SIU_LEVEL1
#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
#define CFG_DISCOVER_PHY

1
include/configs/SXNI855T.h
View File

@ -142,6 +142,7 @@
# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
#define CONFIG_MII 1
#define CFG_DISCOVER_PHY

2
include/configs/TQM5200.h
View File

@ -83,7 +83,7 @@
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */

1
include/configs/TQM834x.h
View File

@ -280,6 +280,7 @@ extern int tqm834x_num_flash_banks;
#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)

2
include/configs/TQM8560.h
View File

@ -283,7 +283,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)

2
include/configs/Total5200.h
View File

@ -100,6 +100,7 @@
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
@ -108,6 +109,7 @@
#else /* MGT5100 */
#define CONFIG_MII 1
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
#endif

1
include/configs/Yukon8220.h
View File

@ -90,6 +90,7 @@
CFG_CMD_SNTP )
#define CONFIG_NET_MULTI
#define CONFIG_MII
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

2
include/configs/at91rm9200dk.h
View File

@ -98,7 +98,7 @@
/* #define CONFIG_ENV_OVERWRITE 1 */
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL | \
((CONFIG_CMD_DFL | CFG_CMD_MII |\
CFG_CMD_DHCP ) & \
~(CFG_CMD_BDI | \
CFG_CMD_IMI | \

2
include/configs/cpci5200.h
View File

@ -83,6 +83,8 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#endif
#define CONFIG_MII
#if 0 /* test-only !!! */
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1

2
include/configs/o2dnt.h
View File

@ -69,7 +69,7 @@
#define CFG_XLB_PIPELINING 1
#define CONFIG_NET_MULTI 1
/* #define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1

1
include/configs/pf5200.h
View File

@ -83,6 +83,7 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_MII 1
#if 0 /* test-only !!! */
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1

36
include/miiphy.h
View File

@ -38,18 +38,38 @@
#ifndef _miiphy_h_
#define _miiphy_h_
#include <net.h>
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value);
int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value);
int miiphy_info(unsigned char addr, unsigned int *oui, unsigned char *model,
unsigned char *rev);
int miiphy_reset(unsigned char addr);
int miiphy_speed(unsigned char addr);
int miiphy_duplex(unsigned char addr);
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset(char *devname, unsigned char addr);
int miiphy_speed(char *devname, unsigned char addr);
int miiphy_duplex(char *devname, unsigned char addr);
#ifdef CFG_FAULT_ECHO_LINK_DOWN
int miiphy_link(unsigned char addr);
int miiphy_link(char *devname, unsigned char addr);
#endif
void miiphy_register(char *devname,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
int miiphy_set_current_dev(char *devname);
char *miiphy_get_current_dev(void);
void miiphy_listdev(void);
#define BB_MII_DEVNAME "bbmii"
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
/* phy seed setup */
#define AUTO 99

1
include/net.h
View File

@ -114,6 +114,7 @@ extern void eth_try_another(int first_restart); /* Change the device */
extern void eth_set_current(void); /* set nterface to ethcur var. */
#endif
extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */
extern int eth_get_dev_index (void); /* get the device index */
extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */

4
lib_arm/board.c
View File

@ -345,8 +345,10 @@ void start_armboot (void)
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
#endif
eth_initialize(gd->bd);
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */

21
lib_i386/board.c
View File

@ -317,15 +317,6 @@ void start_i386boot (void)
misc_init_r();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
WATCHDOG_RESET();
# ifdef DEBUG
puts ("Reset Ethernet PHY\n");
# endif
reset_phy();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
WATCHDOG_RESET();
puts ("PCMCIA:");
@ -387,12 +378,22 @@ void start_i386boot (void)
doc_init();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET();
puts("Net: ");
#endif
eth_initialize(gd->bd);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0)
WATCHDOG_RESET();
# ifdef DEBUG
puts ("Reset Ethernet PHY\n");
# endif
reset_phy();
#endif
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*

4
lib_mips/board.c
View File

@ -414,8 +414,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
misc_init_r ();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
#endif
eth_initialize(gd->bd);
#endif

46
lib_ppc/board.c
View File

@ -899,27 +899,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
hermes_start_lxt980 ((int) bd->bi_ethspeed);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
defined(CONFIG_CCM) || \
defined(CONFIG_ELPT860) || \
defined(CONFIG_EP8260) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_MPC8266ADS) || \
defined(CONFIG_MPC8560ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_STXGP3) || \
defined(CONFIG_SPD823TS) || \
defined(CONFIG_RESET_PHY_R) )
WATCHDOG_RESET ();
debug ("Reset Ethernet PHY\n");
reset_phy ();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
WATCHDOG_RESET ();
puts ("KGDB: ");
@ -978,12 +957,35 @@ void board_init_r (gd_t *id, ulong dest_addr)
nand_init(); /* go init the NAND */
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET ();
puts ("Net: ");
#endif
eth_initialize (bd);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
defined(CONFIG_CCM) || \
defined(CONFIG_ELPT860) || \
defined(CONFIG_EP8260) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_MPC8266ADS) || \
defined(CONFIG_MPC8560ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_STXGP3) || \
defined(CONFIG_SPD823TS) || \
defined(CONFIG_RESET_PHY_R) )
WATCHDOG_RESET ();
debug ("Reset Ethernet PHY\n");
reset_phy ();
#endif
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif

44
net/eth.c
View File

@ -60,6 +60,26 @@ struct eth_device *eth_get_dev(void)
return eth_current;
}
struct eth_device *eth_get_dev_by_name(char *devname)
{
struct eth_device *dev, *target_dev;
if (!eth_devices)
return NULL;
dev = eth_devices;
target_dev = NULL;
do {
if (strcmp(devname, dev->name) == 0) {
target_dev = dev;
break;
}
dev = dev->next;
} while (dev != eth_devices);
return target_dev;
}
int eth_get_dev_index (void)
{
struct eth_device *dev;
@ -413,4 +433,28 @@ char *eth_get_name (void)
{
return (eth_current ? eth_current->name : "unknown");
}
#elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI)
extern int at91rm9200_miiphy_initialize(bd_t *bis);
extern int emac4xx_miiphy_initialize(bd_t *bis);
extern int mcf52x2_miiphy_initialize(bd_t *bis);
extern int ns7520_miiphy_initialize(bd_t *bis);
int eth_initialize(bd_t *bis)
{
#if defined(CONFIG_AT91RM9200)
at91rm9200_miiphy_initialize(bis);
#endif
#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \
&& !defined(CONFIG_AP1000) && !defined(CONFIG_405)
emac4xx_miiphy_initialize(bis);
#endif
#if defined(CONFIG_MCF52x2)
mcf52x2_miiphy_initialize(bis);
#endif
#if defined(CONFIG_NETARM)
ns7520_miiphy_initialize(bis);
#endif
return 0;
}
#endif

4
net/net.c
View File

@ -461,7 +461,7 @@ restart:
/*
* Echo the inverted link state to the fault LED.
*/
if(miiphy_link(CFG_FAULT_MII_ADDR)) {
if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
} else {
status_led_set (STATUS_LED_RED, STATUS_LED_ON);
@ -512,7 +512,7 @@ restart:
/*
* Echo the inverted link state to the fault LED.
*/
if(miiphy_link(CFG_FAULT_MII_ADDR)) {
if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
} else {
status_led_set (STATUS_LED_RED, STATUS_LED_ON);