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mpc83xx: Add MPC8360EMDS basic board support 

Add support for the Freescale MPC8360EMDS board.
Includes DDR, DUART, Local Bus, PCI.
This commit is contained in:
Dave Liu 2006-11-03 19:33:44 -06:00 committed by Kim Phillips
parent 23892e4935
commit 5f8204394e
14 changed files with 2092 additions and 276 deletions
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2
MAKEALL
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@ -130,7 +130,7 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
TQM834x MPC8349EMDS MPC8349ITX \
TQM834x MPC8349EMDS MPC8349ITX MPC8360EMDS \
"

27
Makefile
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@ -1582,15 +1582,36 @@ r5200_config : unconfig
## MPC83xx Systems
#########################################################################
MPC8349ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349ads
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x
MPC8349EMDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
MPC8360EMDS_HOST_66_config \
MPC8360EMDS_SLAVE_config: unconfig
@echo "" >include/config.h ; \
if [ "$(findstring _HOST_,$@)" ] ; then \
echo -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>include/config.h ; \
fi ; \
if [ "$(findstring _SLAVE_,$@)" ] ; then \
echo "...PCI SLAVE 66M" ; \
echo "#define CONFIG_PCI" >>include/config.h ; \
echo "#define CONFIG_PCISLAVE" >>include/config.h ; \
fi ; \
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "...33M ..." ; \
echo "#define PCI_33M" >>include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
echo -n "...66M..." ; \
echo "#define PCI_66M" >>include/config.h ; \
fi ;
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
MPC8349ITX_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx

50
board/mpc8360emds/Makefile Normal file
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@ -0,0 +1,50 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o pci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/mpc8360emds/config.mk Normal file
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@ -0,0 +1,28 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MPC8360EMDS
#
TEXT_BASE = 0xFE000000

574
board/mpc8360emds/mpc8360emds.c Normal file
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@ -0,0 +1,574 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on board/mpc8349emds/mpc8349emds.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#else
#include <asm/mmu.h>
#endif
int board_early_init_f(void)
{
volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
/* Enable flash write */
bcsr[0xa] &= ~0x04;
return 0;
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
void sdram_init(void);
long int initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
msize = fixed_sdram();
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/*
* Initialize DDR ECC byte
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/*
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CFG_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1) {
return -1;
}
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
im->ddr.csbnds[0].csbnds = 0x00000007;
im->ddr.csbnds[1].csbnds = 0x0008000f;
im->ddr.cs_config[0] = CFG_DDR_CONFIG;
im->ddr.cs_config[1] = CFG_DDR_CONFIG;
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
im->ddr.sdram_cfg = CFG_DDR_CONTROL;
im->ddr.sdram_mode = CFG_DDR_MODE;
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
udelay(200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
#endif /*!CFG_SPD_EEPROM */
int checkboard(void)
{
puts("Board: Freescale MPC8360EMDS\n");
return 0;
}
/*
* if MPC8360EMDS is soldered with SDRAM
*/
#if defined(CFG_BR2_PRELIM) \
&& defined(CFG_OR2_PRELIM) \
&& defined(CFG_LBLAWBAR2_PRELIM) \
&& defined(CFG_LBLAWAR2_PRELIM)
/*
* Initialize SDRAM memory on the Local Bus.
*/
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
volatile lbus83xx_t *lbc = &immap->lbus;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/*setup mtrpt, lsrt and lbcr for LB bus */
lbc->lbcr = CFG_LBC_LBCR;
lbc->mrtpr = CFG_LBC_MRTPR;
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
asm("sync");
*sdram_addr = 0xff;
udelay(100);
/*
* We need do 8 times auto refresh operation.
*/
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
*sdram_addr = 0xff; /* 1 times */
udelay(100);
*sdram_addr = 0xff; /* 2 times */
udelay(100);
*sdram_addr = 0xff; /* 3 times */
udelay(100);
*sdram_addr = 0xff; /* 4 times */
udelay(100);
*sdram_addr = 0xff; /* 5 times */
udelay(100);
*sdram_addr = 0xff; /* 6 times */
udelay(100);
*sdram_addr = 0xff; /* 7 times */
udelay(100);
*sdram_addr = 0xff; /* 8 times */
udelay(100);
/* Mode register write operation */
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
*(sdram_addr + 0xcc) = 0xff;
udelay(100);
/* Normal operation */
lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
}
#else
void sdram_init(void)
{
puts("SDRAM on Local Bus is NOT available!\n");
}
#endif
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
/*
* ECC user commands
*/
void ecc_print_status(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n",
(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
/* Interrupts */
printf("Memory Error Interrupt Enable:\n");
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
printf(" Single-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
printf(" Memory Select Error Interrupt Enable: %d\n\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
/* Error disable */
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
printf(" Sinle-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
/* Error injection */
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
printf("Memory Data Path Error Injection Mask ECC:\n");
printf(" ECC Mirror Byte: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
printf(" ECC Injection Enable: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
printf(" ECC Error Injection Mask: 0x%02x\n\n",
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
/* SBE counter/threshold */
printf("Memory Single-Bit Error Management (0..255):\n");
printf(" Single-Bit Error Threshold: %d\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
printf(" Single-Bit Error Counter: %d\n\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
/* Error detect */
printf("Memory Error Detect:\n");
printf(" Multiple Memory Errors: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
printf(" Multiple-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
printf(" Single-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
printf(" Memory Select Error: %d\n\n",
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
/* Capture data */
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
ddr->capture_data_hi, ddr->capture_data_lo);
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
ddr->capture_ecc & CAPTURE_ECC_ECE);
printf("Memory Error Attributes Capture:\n");
printf(" Data Beat Number: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
ECC_CAPT_ATTR_BNUM_SHIFT);
printf(" Transaction Size: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
ECC_CAPT_ATTR_TSIZ_SHIFT);
printf(" Transaction Source: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
ECC_CAPT_ATTR_TSRC_SHIFT);
printf(" Transaction Type: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
ECC_CAPT_ATTR_TTYP_SHIFT);
printf(" Error Information Valid: %d\n\n",
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
}
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr;
u32 count;
register u64 *i;
u32 ret[2];
u32 pattern[2];
u32 writeback[2];
/* The pattern is written into memory to generate error */
pattern[0] = 0xfedcba98UL;
pattern[1] = 0x76543210UL;
/* After injecting error, re-initialize the memory with the value */
writeback[0] = 0x01234567UL;
writeback[1] = 0x89abcdefUL;
if (argc > 4) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
ecc_print_status();
return 0;
} else if (strcmp(argv[1], "captureclear") == 0) {
ddr->capture_address = 0;
ddr->capture_data_hi = 0;
ddr->capture_data_lo = 0;
ddr->capture_ecc = 0;
ddr->capture_attributes = 0;
return 0;
}
}
if (argc == 3) {
if (strcmp(argv[1], "sbecnt") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, "
"should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "sbethr") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, "
"should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "errdisable") == 0) {
val = ddr->err_disable;
if (strcmp(argv[2], "+sbe") == 0) {
val |= ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "+mbe") == 0) {
val |= ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "+mse") == 0) {
val |= ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "+all") == 0) {
val |= (ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else if (strcmp(argv[2], "-sbe") == 0) {
val &= ~ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "-mbe") == 0) {
val &= ~ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "-mse") == 0) {
val &= ~ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "-all") == 0) {
val &= ~(ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else {
printf("Incorrect err_disable field\n");
return 1;
}
ddr->err_disable = val;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
if (strcmp(argv[2], "mme") == 0) {
val |= ECC_ERROR_DETECT_MME;
} else if (strcmp(argv[2], "sbe") == 0) {
val |= ECC_ERROR_DETECT_SBE;
} else if (strcmp(argv[2], "mbe") == 0) {
val |= ECC_ERROR_DETECT_MBE;
} else if (strcmp(argv[2], "mse") == 0) {
val |= ECC_ERROR_DETECT_MSE;
} else if (strcmp(argv[2], "all") == 0) {
val |= (ECC_ERROR_DETECT_MME |
ECC_ERROR_DETECT_MBE |
ECC_ERROR_DETECT_SBE |
ECC_ERROR_DETECT_MSE);
} else {
printf("Incorrect err_detect field\n");
return 1;
}
ddr->err_detect = val;
return 0;
} else if (strcmp(argv[1], "injectdatahi") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_hi = val;
return 0;
} else if (strcmp(argv[1], "injectdatalo") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_lo = val;
return 0;
} else if (strcmp(argv[1], "injectecc") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
if (val > 0xff) {
printf("Incorrect ECC inject mask, "
"should be 0x00..0xff\n");
return 1;
}
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
ddr->ecc_err_inject = val;
return 0;
} else if (strcmp(argv[1], "inject") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EIEN;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EIEN;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EMB;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EMB;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
return 0;
}
}
if (argc == 4) {
if (strcmp(argv[1], "testdw") == 0) {
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
printf("Address not alligned on "
"double word boundary\n");
return 1;
}
disable_interrupts();
for (i = addr; i < addr + count; i++) {
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
/* write memory location injecting errors */
ppcDWstore((u32 *) i, pattern);
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
/* read data, this generates ECC error */
ppcDWload((u32 *) i, ret);
/* re-initialize memory, double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
}
enable_interrupts();
return 0;
}
if (strcmp(argv[1], "testword") == 0) {
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
printf("Address not alligned on "
"double word boundary\n");
return 1;
}
disable_interrupts();
for (i = addr; i < addr + count; i++) {
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
/* write memory location injecting errors */
*(u32 *) i = 0xfedcba98UL;
__asm__ __volatile__("sync");
/* sub double word write,
* bus will read-modify-write,
* generates ECC error */
*((u32 *) i + 1) = 0x76543210UL;
__asm__ __volatile__("sync");
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
__asm__ __volatile__("sync");
__asm__ __volatile__("isync");
/* re-initialize memory,
* double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
}
enable_interrupts();
return 0;
}
}
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(ecc, 4, 0, do_ecc,
"ecc - support for DDR ECC features\n",
"status - print out status info\n"
"ecc captureclear - clear capture regs data\n"
"ecc sbecnt <val> - set Single-Bit Error counter\n"
"ecc sbethr <val> - set Single-Bit Threshold\n"
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
" [-|+]sbe - Single-Bit Error\n"
" [-|+]mbe - Multiple-Bit Error\n"
" [-|+]mse - Memory Select Error\n"
" [-|+]all - all errors\n"
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
" mme - Multiple Memory Errors\n"
" sbe - Single-Bit Error\n"
" mbe - Multiple-Bit Error\n"
" mse - Memory Select Error\n"
" all - all errors\n"
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
"ecc inject <en|dis> - enable/disable error injection\n"
"ecc mirror <en|dis> - enable/disable mirror byte\n"
"ecc testdw <addr> <cnt> - test mem region with double word access:\n"
" - enables injects\n"
" - writes pattern injecting errors with double word access\n"
" - disables injects\n"
" - reads pattern back with double word access, generates error\n"
" - re-inits memory\n"
"ecc testword <addr> <cnt> - test mem region with word access:\n"
" - enables injects\n"
" - writes pattern injecting errors with word access\n"
" - writes pattern with word access, generates error\n"
" - disables injects\n" " - re-inits memory");
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */

294
board/mpc8360emds/pci.c Normal file
View File

@ -0,0 +1,294 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* PCI Configuration space access support for MPC83xx PCI Bridge
*/
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <pci.h>
#include <i2c.h>
#include <asm/i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PCI)
#define PCI_FUNCTION_CONFIG 0x44
#define PCI_FUNCTION_CFG_LOCK 0x20
/*
* Initialize PCI Devices, report devices found
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc83xxemds_config_table[] = {
{
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
pci_cfgfunc_config_device,
{PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
},
{}
}
#endif
static struct pci_controller hose[] = {
{
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc83xxemds_config_table,
#endif
},
};
/**********************************************************************
* pci_init_board()
*********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
u16 reg16;
volatile immap_t *immr;
volatile law83xx_t *pci_law;
volatile pot83xx_t *pci_pot;
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
immr = (immap_t *) CFG_IMMRBAR;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
pci_conf = immr->pci_conf;
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].pitar0 = 0x0;
pci_ctrl[0].pibar0 = 0x0;
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 &= ~PIWAR_EN;
pci_ctrl[0].pitar2 = 0x0;
pci_ctrl[0].pibar2 = 0x0;
pci_ctrl[0].piebar2 = 0x0;
pci_ctrl[0].piwar2 &= ~PIWAR_EN;
hose[0].first_busno = 0;
hose[0].last_busno = 0xff;
pci_setup_indirect(&hose[0],
(CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
reg16 = 0xff;
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
PCI_STATUS, 0xffff);
pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
PCI_LATENCY_TIMER, 0x80);
/*
* Unlock configuration lock in PCI function configuration register.
*/
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
PCI_FUNCTION_CONFIG, &reg16);
reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
PCI_FUNCTION_CONFIG, reg16);
printf("Enabled PCI 32bit Agent Mode\n");
}
#else
{
volatile immap_t *immr;
volatile clk83xx_t *clk;
volatile law83xx_t *pci_law;
volatile pot83xx_t *pci_pot;
volatile pcictrl83xx_t *pci_ctrl;
volatile pciconf83xx_t *pci_conf;
u8 val8, orig_i2c_bus;
u16 reg16;
u32 val32;
u32 dev;
immr = (immap_t *) CFG_IMMRBAR;
clk = (clk83xx_t *) & immr->clk;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = immr->pci_ctrl;
pci_conf = immr->pci_conf;
/*
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
*/
val32 = clk->occr;
udelay(2000);
#if defined(PCI_66M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#elif defined(PCI_33M)
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
printf("PCI clock is 33MHz\n");
#else
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
printf("PCI clock is 66MHz\n");
#endif
udelay(2000);
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
/*
* Configure PCI Outbound Translation Windows
*/
/* PCI mem space - prefetch */
pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr =
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI mmio - non-prefetch mem space */
pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
/* PCI IO space */
pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 =
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
PIWAR_IWS_2G;
/*
* Assign PIB PMC slot to desired PCI bus
*/
mpc83xx_i2c = (i2c_t *) (CFG_IMMRBAR + CFG_I2C2_OFFSET);
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
/*
* Release PCI RST Output signal
*/
udelay(2000);
pci_ctrl[0].gcr = 1;
udelay(2000);
hose[0].first_busno = 0;
hose[0].last_busno = 0xff;
/* PCI memory prefetch space */
pci_set_region(hose[0].regions + 0,
CFG_PCI_MEM_BASE,
CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose[0].regions + 1,
CFG_PCI_MMIO_BASE,
CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose[0].regions + 2,
CFG_PCI_IO_BASE,
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
/* System memory space */
pci_set_region(hose[0].regions + 3,
CFG_PCI_SLV_MEM_LOCAL,
CFG_PCI_SLV_MEM_BUS,
CFG_PCI_SLV_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
hose[0].region_count = 4;
pci_setup_indirect(&hose[0],
(CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304));
pci_register_hose(hose);
/*
* Write command register
*/
reg16 = 0xff;
dev = PCI_BDF(0, 0, 0);
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCISLAVE */
#endif /* CONFIG_PCI */

123
board/mpc8360emds/u-boot.lds Normal file
View File

@ -0,0 +1,123 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc83xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

54
cpu/mpc83xx/cpu.c
View File

@ -43,28 +43,70 @@ DECLARE_GLOBAL_DATA_PTR;
int checkcpu(void)
{
volatile immap_t *immr;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr();
u32 spridr;
char buf[32];
immr = (immap_t *)CFG_IMMRBAR;
if ((pvr & 0xFFFF0000) != PVR_83xx) {
puts("Not MPC83xx Family!!!\n");
return -1;
}
puts("CPU: MPC83xx, ");
switch(pvr) {
case PVR_8349_REV10:
spridr = immr->sysconf.spridr;
puts("CPU: ");
switch(spridr) {
case SPR_8349E_REV10:
case SPR_8349E_REV11:
puts("MPC8349E, ");
break;
case PVR_8349_REV11:
case SPR_8349_REV10:
case SPR_8349_REV11:
puts("MPC8349, ");
break;
case SPR_8347E_REV10_TBGA:
case SPR_8347E_REV11_TBGA:
case SPR_8347E_REV10_PBGA:
case SPR_8347E_REV11_PBGA:
puts("MPC8347E, ");
break;
case SPR_8347_REV10_TBGA:
case SPR_8347_REV11_TBGA:
case SPR_8347_REV10_PBGA:
case SPR_8347_REV11_PBGA:
puts("MPC8347, ");
break;
case SPR_8343E_REV10:
case SPR_8343E_REV11:
puts("MPC8343E, ");
break;
case SPR_8343_REV10:
case SPR_8343_REV11:
puts("MPC8343, ");
break;
case SPR_8360E_REV10:
case SPR_8360E_REV11:
case SPR_8360E_REV12:
puts("MPC8360E, ");
break;
case SPR_8360_REV10:
case SPR_8360_REV11:
case SPR_8360_REV12:
puts("MPC8360, ");
break;
default:
puts("Rev: Unknown\n");
return -1; /* Not sure what this is */
}
printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
(pvr & 0x0f), strmhz(buf, clock));
#if defined(CONFIG_MPC8349)
printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
#else
printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
#endif
return 0;
}

304
cpu/mpc83xx/spd_sdram.c
View File

@ -4,7 +4,7 @@
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@ -112,14 +112,10 @@ static void spd_debug(spd_eeprom_t *spd)
long int spd_sdram()
{
#ifdef CONFIG_MPC834X
int caslat_83xx; /* For Errata DDR6 */
#endif
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
spd_eeprom_t spd;
unsigned int tmp, tmp1;
unsigned int memsize;
unsigned int law_size;
unsigned char caslat, caslat_ctrl;
@ -131,28 +127,7 @@ long int spd_sdram()
unsigned sdram_cfg;
unsigned int ddrc_ecc_enable;
/* Read SPD parameters with I2C */
#ifdef CFG_83XX_DDR_USES_CS0
ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[0] = ( 1 << 31
| (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) );
debug("\n");
debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
if (spd.nrows == 2) {
ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
| ((banksize(spd.row_dens) >> 23) - 1) );
ddr->cs_config[1] = ( 1<<31
| (spd.nrow_addr-12) << 8
| (spd.ncol_addr-8) );
debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
}
#else
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
@ -183,6 +158,26 @@ long int spd_sdram()
return 0;
}
/* Setup DDR chip select register */
#ifdef CFG_83XX_DDR_USES_CS0
ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[0] = ( 1 << 31
| (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) );
debug("\n");
debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
if (spd.nrows == 2) {
ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
| ((banksize(spd.row_dens) >> 23) - 1) );
ddr->cs_config[1] = ( 1<<31
| (spd.nrow_addr-12) << 8
| (spd.ncol_addr-8) );
debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
}
#else
ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[2] = ( 1 << 31
| (spd.nrow_addr - 12) << 8
@ -243,8 +238,9 @@ long int spd_sdram()
*/
caslat = __ilog2(spd.cas_lat);
if (caslat > 4 ) {
printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat);
if (caslat > 6 ) {
printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
spd.cas_lat);
return 0;
}
max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
@ -256,89 +252,110 @@ long int spd_sdram()
ddrc_clk = get_ddr_clk(0) / 1000000;
if (max_data_rate >= 390) { /* it is DDR 400 */
printf("DDR: platform not support DDR 400\n");
return 0;
if (ddrc_clk <= 410 && ddrc_clk > 350) {
/* DDR controller clk at 350~410 */
effective_data_rate = 400; /* 5ns */
caslat = caslat;
} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
/* DDR controller clk at 280~350 */
effective_data_rate = 333; /* 6ns */
if (spd.clk_cycle2 == 0x60) {
caslat = caslat - 1;
} else {
caslat = caslat;
}
} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
/* DDR controller clk at 230~280 */
effective_data_rate = 266; /* 7.5ns */
if (spd.clk_cycle3 == 0x75) {
caslat = caslat - 2;
} else if (spd.clk_cycle2 == 0x60) {
caslat = caslat - 1;
} else {
caslat = caslat;
}
} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
/* DDR controller clk at 90~230 */
effective_data_rate = 200; /* 10ns */
if (spd.clk_cycle3 == 0x75) {
caslat = caslat - 2;
} else if (spd.clk_cycle2 == 0x60) {
caslat = caslat - 1;
} else {
caslat = caslat;
}
}
} else if (max_data_rate >= 323) { /* it is DDR 333 */
if (ddrc_clk <= 350 && ddrc_clk > 280) {
/* DDRC clk at 280~350 */
/* DDR controller clk at 280~350 */
effective_data_rate = 333; /* 6ns */
caslat = caslat;
} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
/* DDRC clk at 230~280 */
/* DDR controller clk at 230~280 */
effective_data_rate = 266; /* 7.5ns */
if (spd.clk_cycle2 == 0x75) {
effective_data_rate = 266; /* 7.5ns */
caslat = caslat - 1;
} else {
caslat = caslat;
}
} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
/* DDRC clk at 90~230 */
/* DDR controller clk at 90~230 */
effective_data_rate = 200; /* 10ns */
if (spd.clk_cycle3 == 0xa0) {
effective_data_rate = 200; /* 10ns */
caslat = caslat - 2;
} else if (spd.clk_cycle2 == 0x75) {
caslat = caslat - 1;
} else {
caslat = caslat;
}
}
} else if (max_data_rate >= 256) { /* it is DDR 266 */
if (ddrc_clk <= 350 && ddrc_clk > 280) {
/* DDRC clk at 280~350 */
/* DDR controller clk at 280~350 */
printf("DDR: DDR controller freq is more than "
"max data rate of the module\n");
return 0;
} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
/* DDRC clk at 230~280 */
/* DDR controller clk at 230~280 */
effective_data_rate = 266; /* 7.5ns */
caslat = caslat;
} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
/* DDRC clk at 90~230 */
/* DDR controller clk at 90~230 */
effective_data_rate = 200; /* 10ns */
if (spd.clk_cycle2 == 0xa0) {
effective_data_rate = 200; /* 10ns */
caslat = caslat - 1;
}
}
} else if (max_data_rate >= 190) { /* it is DDR 200 */
if (ddrc_clk <= 350 && ddrc_clk > 230) {
/* DDRC clk at 230~350 */
/* DDR controller clk at 230~350 */
printf("DDR: DDR controller freq is more than "
"max data rate of the module\n");
return 0;
} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
/* DDRC clk at 90~230 */
/* DDR controller clk at 90~230 */
effective_data_rate = 200; /* 10ns */
caslat = caslat;
}
}
#ifdef CONFIG_MPC834X
/* Errata DDR6
This errata affects all MPC8349E, MPC8343E and MPC8347E processors.
*/
if ((tmp1 >= 280) && (tmp1 < 350)) /* CSB=333 */
{
if (spd.mid[0] == 0x2c) {
/* Micron memory running at 333 MHz */
/* Chances are, U-Boot will crash before we get here,
but just in case, display a message and return error. */
printf("Micron DDR not supported at 333MHz CSB\n");
return 0;
} else if (spd.mid[0] == 0xad) {
printf("Hynix DDR does not require Errata DDR6\n");
} else {
/* enable 2 cycle Earlier for CL=2.5 or 3 */
ddr->debug_reg = 0x202c0000;
printf("Errata DDR6 (debug_reg=0x%x)\n", ddr->debug_reg);
}
caslat_83xx = caslat;
}
if ((tmp1 >= 230) && (tmp1 < 280)) { /* CSB=266 */
if (spd.mid[0] != 0x2c) /* non-Micron */
caslat_83xx = caslat - 1;
debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
/*
* Errata DDR6 work around: input enable 2 cycles earlier.
* including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
*/
if (caslat == 2) {
ddr->debug_reg = 0x201c0000; /* CL=2 */
} else if (caslat == 3) {
ddr->debug_reg = 0x202c0000; /* CL=2.5 */
} else if (caslat == 4) {
ddr->debug_reg = 0x202c0000; /* CL=3.0 */
}
__asm__ __volatile__ ("sync");
if ((tmp1 >= 90) && (tmp1 < 230)) { /* CSB=200 */
caslat = 3;
caslat_83xx = 2;
}
#endif
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
/*
* note: caslat must also be programmed into ddr->sdram_mode
@ -353,11 +370,7 @@ long int spd_sdram()
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
#ifdef CONFIG_MPC834x
((caslat_83xx & 0x07) << 16 ) |
#else
((caslat_ctrl & 0x07) << 16 ) |
#endif
(((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
( 0x300 ) |
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
@ -370,13 +383,10 @@ long int spd_sdram()
ddr->sdram_cfg = 0x42000000;
/* Check DIMM data bus width */
if (spd.dataw_lsb == 0x20)
{
if (spd.dataw_lsb == 0x20) {
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
printf("\n DDR DIMM: data bus width is 32 bit");
}
else
{
} else {
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
printf("\n DDR DIMM: data bus width is 64 bit");
}
@ -384,68 +394,67 @@ long int spd_sdram()
/* Is this an ECC DDR chip? */
if (spd.config == 0x02) {
printf(" with ECC\n");
}
else
} else {
printf(" without ECC\n");
}
/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
Burst type is sequential
*/
switch(caslat) {
case 1:
ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
break;
case 2:
ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
break;
case 3:
ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
break;
case 4:
ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
break;
default:
printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 "
"is supported.\n");
return 0;
switch (caslat) {
case 1:
ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
break;
case 2:
ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
break;
case 3:
ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
break;
case 4:
ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
break;
default:
printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
return 0;
}
debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
switch(spd.refresh) {
case 0x00:
case 0x80:
tmp = picos_to_clk(15625000);
break;
case 0x01:
case 0x81:
tmp = picos_to_clk(3900000);
break;
case 0x02:
case 0x82:
tmp = picos_to_clk(7800000);
break;
case 0x03:
case 0x83:
tmp = picos_to_clk(31300000);
break;
case 0x04:
case 0x84:
tmp = picos_to_clk(62500000);
break;
case 0x05:
case 0x85:
tmp = picos_to_clk(125000000);
break;
default:
tmp = 0x512;
break;
switch (spd.refresh) {
case 0x00:
case 0x80:
refresh_clk = picos_to_clk(15625000);
break;
case 0x01:
case 0x81:
refresh_clk = picos_to_clk(3900000);
break;
case 0x02:
case 0x82:
refresh_clk = picos_to_clk(7800000);
break;
case 0x03:
case 0x83:
refresh_clk = picos_to_clk(31300000);
break;
case 0x04:
case 0x84:
refresh_clk = picos_to_clk(62500000);
break;
case 0x05:
case 0x85:
refresh_clk = picos_to_clk(125000000);
break;
default:
refresh_clk = 0x512;
break;
}
/*
* Set BSTOPRE to 0x100 for page mode
* If auto-charge is used, set BSTOPRE = 0
*/
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
/* SS_EN = 0, source synchronous disable
@ -459,8 +468,8 @@ long int spd_sdram()
udelay(600);
/*
* Figure out the settings for the sdram_cfg register. Build up
* the entire register in 'tmp' before writing since the write into
* Figure out the settings for the sdram_cfg register. Build up
* the value in 'sdram_cfg' before writing since the write into
* the register will actually enable the memory controller, and all
* settings must be done before enabling.
*
@ -493,13 +502,13 @@ long int spd_sdram()
/* set single bit error threshold to maximum value,
* reset counter to zero */
ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
(0 << ECC_ERROR_MAN_SBEC_SHIFT);
(0 << ECC_ERROR_MAN_SBEC_SHIFT);
}
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
printf(" DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");
printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
@ -517,7 +526,6 @@ long int spd_sdram()
}
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/*
* Use timebase counter, get_timer() is not availabe
@ -602,26 +610,16 @@ void ddr_enable_ecc(unsigned int dram_size)
}
}
/* 8K */
dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
/* 16K */
dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
/* 32K */
dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
/* 64K */
dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
/* 128k */
dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
/* 256k */
dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
/* 512k */
dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
/* 1M */
dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
/* 2M */
dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
/* 4M */
dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);

209
cpu/mpc83xx/speed.c
View File

@ -2,7 +2,7 @@
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright 2004 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -104,79 +104,52 @@ int get_clocks (void)
u32 lcrr;
u32 csb_clk;
#if defined(CONFIG_MPC8349)
u32 tsec1_clk;
u32 tsec2_clk;
u32 core_clk;
u32 usbmph_clk;
u32 usbdr_clk;
u32 i2c_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
#if defined (CONFIG_MPC8360)
u32 qepmf;
u32 qepdf;
u32 ddr_sec_clk;
u32 qe_clk;
u32 brg_clk;
#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
#ifndef CFG_HRCW_HIGH
# error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
# ifndef CONFIG_83XX_CLKIN
# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK
# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */
/* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) {
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
* the im->reset.rcwhr PCI Host Mode is disabled
* FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
/* PCI Clock is half CONFIG_83XX_CLKIN */
pci_sync_in = CONFIG_83XX_CLKIN / 2;
}
else {
pci_sync_in = CONFIG_83XX_CLKIN;
}
#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
# ifdef CONFIG_83XX_CLKIN
# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK
# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */
/* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) {
/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
* the im->reset.rcwhr PCI Host Mode is enabled */
return -3;
}
pci_sync_in = CONFIG_83XX_PCICLK;
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
}
else {
csb_clk = pci_sync_in * spmf * (1 + clkin_div);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_83XX_CLKIN)
pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
} else {
#if defined(CONFIG_83XX_PCICLK)
pci_sync_in = CONFIG_83XX_PCICLK;
#else
pci_sync_in = 0xDEADBEEF;
#endif
}
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
sccr = im->clk.sccr;
#if defined(CONFIG_MPC8349)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@ -212,25 +185,8 @@ int get_clocks (void)
/* unkown SCCR_TSEC2CM value */
return -5;
}
i2c_clk = tsec2_clk;
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
break;
case 1:
enc_clk = csb_clk;
break;
case 2:
enc_clk = csb_clk / 2;
break;
case 3:
enc_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_ENCCM value */
return -6;
}
i2c1_clk = tsec2_clk;
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
@ -274,8 +230,34 @@ int get_clocks (void)
/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
return -9;
}
#endif
#if defined (CONFIG_MPC8360)
i2c1_clk = csb_clk;
#endif
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
break;
case 1:
enc_clk = csb_clk;
break;
case 2:
enc_clk = csb_clk / 2;
break;
case 3:
enc_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_ENCCM value */
return -6;
}
#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
#else
#error Unknown MPC83xx chip
#endif
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
@ -287,10 +269,16 @@ int get_clocks (void)
/* unknown lcrr */
return -10;
}
#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
#if defined (CONFIG_MPC8360)
ddr_sec_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
#endif
#else
#error Unknown MPC83xx chip
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
/* corecnf_tab_index is too high, possibly worng value */
@ -319,22 +307,36 @@ int get_clocks (void)
return -12;
}
gd->csb_clk = csb_clk ;
gd->tsec1_clk = tsec1_clk ;
gd->tsec2_clk = tsec2_clk ;
gd->core_clk = core_clk ;
gd->usbmph_clk = usbmph_clk;
gd->usbdr_clk = usbdr_clk ;
gd->i2c_clk = i2c_clk ;
gd->enc_clk = enc_clk ;
gd->lbiu_clk = lbiu_clk ;
gd->lclk_clk = lclk_clk ;
gd->ddr_clk = ddr_clk ;
gd->pci_clk = pci_sync_in;
#if defined (CONFIG_MPC8360)
qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf)/(1+qepdf);
brg_clk = qe_clk / 2;
#endif
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->lbiu_clk;
gd->csb_clk = csb_clk;
#if defined(CONFIG_MPC8349)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbmph_clk = usbmph_clk;
gd->usbdr_clk = usbdr_clk;
#endif
gd->core_clk = core_clk;
gd->i2c1_clk = i2c1_clk;
gd->i2c2_clk = i2c2_clk;
gd->enc_clk = enc_clk;
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
gd->ddr_clk = ddr_clk;
#if defined (CONFIG_MPC8360)
gd->ddr_sec_clk = ddr_sec_clk;
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->csb_clk;
return 0;
}
ulong get_ddr_clk(ulong dummy)
@ -357,14 +359,23 @@ int print_clock_conf (void)
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000);
debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
#if defined (CONFIG_MPC8360)
printf(" QE: %4d MHz\n",gd->qe_clk/1000000);
#endif
printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
#if defined (CONFIG_MPC8360)
printf(" DDR Secondary: %4d MHz\n",gd->ddr_sec_clk/1000000);
#endif
printf(" SEC: %4d MHz\n",gd->enc_clk/1000000);
printf(" I2C1: %4d MHz\n",gd->i2c1_clk/1000000);
printf(" I2C2: %4d MHz\n",gd->i2c2_clk/1000000);
#if defined(CONFIG_MPC8349)
printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
#endif
return 0;
}

2
include/asm-ppc/e300.h
View File

@ -12,6 +12,8 @@
#define PVR_83xx 0x80830000
#define PVR_8349_REV10 (PVR_83xx | 0x0010)
#define PVR_8349_REV11 (PVR_83xx | 0x0011)
#define PVR_8360_REV10 (PVR_83xx | 0x0020)
#define PVR_8360_REV11 (PVR_83xx | 0x0020)
/*
* Hardware Implementation-Dependent Register 0 (HID0)

14
include/asm-ppc/global_data.h
View File

@ -52,17 +52,27 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
#if defined (CONFIG_MPC8349)
u32 tsec1_clk;
u32 tsec2_clk;
u32 core_clk;
u32 usbmph_clk;
u32 usbdr_clk;
u32 i2c_clk;
#endif /* CONFIG_MPC8349 */
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
#endif /* CONFIG_QE */
#if defined (CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;

585
include/configs/MPC8360EMDS.h Normal file
View File

@ -0,0 +1,585 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
/*
* System Clock Setup
*/
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66000000
#endif
/*
* Hardware Reset Configuration Word
*/
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_4X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CE_PLL_VCO_DIV_4 |\
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X6 |\
HRCWL_CORE_TO_CSB_2X1)
#ifdef CONFIG_PCISLAVE
#define CFG_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_PCICKDRV_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT)
#else
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCICKDRV_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT)
#endif
/*
* System IO Config
*/
#define CFG_SICRH 0x00000000
#define CFG_SICRL 0x40000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
/*
* IMMR new address
*/
#define CFG_IMMRBAR 0xE0000000
/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* MB */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
/*
* Memory test
*/
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000
/*
* The reserved memory
*/
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
/*
* BCSR on the Local Bus
*/
#define CFG_BCSR 0xF8000000
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/*
* SDRAM on the Local Bus
*/
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
#ifdef CFG_LB_SDRAM
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* port size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* the top 17 bits of BR2.
*/
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON 0x0063b723
/*
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL)
#endif
/*
* Windows to access PIB via local bus
*/
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
/*
* CS4 on Local Bus, to PIB
*/
#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS5 on Local Bus, to PIB
*/
#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI_MEM_BASE 0x80000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI_IO_BASE 0xE0300000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
#define CFG_PCI_SLV_MEM_BUS 0x00000000
#define CFG_PCI_SLV_MEM_SIZE 0x80000000
#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_PCI \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C )
#endif
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2 HID2_HBE
/*
* Cache Config
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
/*
* MMU Setup
*/
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CFG_IBAT1L (CFG_IMMRBAR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT1U (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
/* BCSR: cache-inhibit and guarded */
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U CFG_IBAT3U
/* Local bus SDRAM: cacheable */
#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT4L CFG_IBAT4L
#define CFG_DBAT4U CFG_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT5L CFG_IBAT5L
#define CFG_DBAT5U CFG_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
#else
#define CFG_IBAT6L (0)
#define CFG_IBAT6U (0)
#define CFG_IBAT7L (0)
#define CFG_IBAT7U (0)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_ETHADDR 00:04:9f:ef:01:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=400000\0" \
"ramdiskfile=ramfs.83xx\0" \
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"bootm $loadaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

102
include/mpc83xx.h
View File

@ -8,16 +8,6 @@
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
@ -89,8 +79,30 @@
/*
* The device ID and revision numbers
*/
#define SPR_8349E_REV10 0x80300100
#define SPR_8349E_REV11 0x80300101
#define SPR_8349E_REV10 0x80300100
#define SPR_8349_REV10 0x80310100
#define SPR_8347E_REV10_TBGA 0x80320100
#define SPR_8347_REV10_TBGA 0x80330100
#define SPR_8347E_REV10_PBGA 0x80340100
#define SPR_8347_REV10_PBGA 0x80350100
#define SPR_8343E_REV10 0x80360100
#define SPR_8343_REV10 0x80370100
#define SPR_8349E_REV11 0x80300101
#define SPR_8349_REV11 0x80310101
#define SPR_8347E_REV11_TBGA 0x80320101
#define SPR_8347_REV11_TBGA 0x80330101
#define SPR_8347E_REV11_PBGA 0x80340101
#define SPR_8347_REV11_PBGA 0x80350101
#define SPR_8343E_REV11 0x80360101
#define SPR_8343_REV11 0x80370101
#define SPR_8360E_REV10 0x80480010
#define SPR_8360_REV10 0x80490010
#define SPR_8360E_REV11 0x80480011
#define SPR_8360_REV11 0x80490011
#define SPR_8360E_REV12 0x80480012
#define SPR_8360_REV12 0x80490012
/*
* Base Registers & Option Registers
@ -122,9 +134,17 @@
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#if defined (CONFIG_MPC8360)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#if defined (CONFIG_MPC8349)
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#elif defined (CONFIG_MPC8360)
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
#endif
#define OR0 0x5004
#define OR1 0x500C
@ -207,14 +227,21 @@
#define HRCWH_PCI_AGENT 0x00000000
#define HRCWH_PCI_HOST 0x80000000
#if defined (CONFIG_MPC8349)
#define HRCWH_32_BIT_PCI 0x00000000
#define HRCWH_64_BIT_PCI 0x40000000
#endif
#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
#if defined (CONFIG_MPC8349)
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
#elif defined (CONFIG_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
#define HRCWH_CORE_DISABLE 0x08000000
#define HRCWH_CORE_ENABLE 0x00000000
@ -231,11 +258,14 @@
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
#if defined (CONFIG_MPC8349)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined (CONFIG_MPC8349)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
#define HRCWH_TSEC1M_IN_GMII 0x00008000
@ -245,6 +275,12 @@
#define HRCWH_TSEC2M_IN_RTBI 0x00001000
#define HRCWH_TSEC2M_IN_GMII 0x00002000
#define HRCWH_TSEC2M_IN_TBI 0x00003000
#endif
#if defined (CONFIG_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
#define HRCWH_BIG_ENDIAN 0x00000000
#define HRCWH_LITTLE_ENDIAN 0x00000008
@ -293,6 +329,47 @@
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
#if defined (CONFIG_MPC8360)
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
#define HRCWL_CE_PLL_DIV_1X1 0x00000000
#define HRCWL_CE_PLL_DIV_2X1 0x00000020
#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
#define HRCWL_CE_TO_PLL_1X2 0x00000002
#define HRCWL_CE_TO_PLL_1X3 0x00000003
#define HRCWL_CE_TO_PLL_1X4 0x00000004
#define HRCWL_CE_TO_PLL_1X5 0x00000005
#define HRCWL_CE_TO_PLL_1X6 0x00000006
#define HRCWL_CE_TO_PLL_1X7 0x00000007
#define HRCWL_CE_TO_PLL_1X8 0x00000008
#define HRCWL_CE_TO_PLL_1X9 0x00000009
#define HRCWL_CE_TO_PLL_1X10 0x0000000A
#define HRCWL_CE_TO_PLL_1X11 0x0000000B
#define HRCWL_CE_TO_PLL_1X12 0x0000000C
#define HRCWL_CE_TO_PLL_1X13 0x0000000D
#define HRCWL_CE_TO_PLL_1X14 0x0000000E
#define HRCWL_CE_TO_PLL_1X15 0x0000000F
#define HRCWL_CE_TO_PLL_1X16 0x00000010
#define HRCWL_CE_TO_PLL_1X17 0x00000011
#define HRCWL_CE_TO_PLL_1X18 0x00000012
#define HRCWL_CE_TO_PLL_1X19 0x00000013
#define HRCWL_CE_TO_PLL_1X20 0x00000014
#define HRCWL_CE_TO_PLL_1X21 0x00000015
#define HRCWL_CE_TO_PLL_1X22 0x00000016
#define HRCWL_CE_TO_PLL_1X23 0x00000017
#define HRCWL_CE_TO_PLL_1X24 0x00000018
#define HRCWL_CE_TO_PLL_1X25 0x00000019
#define HRCWL_CE_TO_PLL_1X26 0x0000001A
#define HRCWL_CE_TO_PLL_1X27 0x0000001B
#define HRCWL_CE_TO_PLL_1X28 0x0000001C
#define HRCWL_CE_TO_PLL_1X29 0x0000001D
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#endif
/*
* LCRR - Clock Ratio Register (10.3.1.16)
*/
@ -346,6 +423,7 @@
| SCCR_TSEC2CM_3 \
| SCCR_ENCCM_3 \
| SCCR_USBCM_3 )
#define SCCR_DEFAULT 0xFFFFFFFF
#endif /* __MPC83XX_H__ */