Add support for the MPC837xERDB
MPC837xERDB board support includes: * DDR2 330MHz hardcoded (soldered on the board) * Local Bus NOR Flash * I2C, UART and RTC * eTSEC RGMII (TSEC0 - RTL8211B with MII; * TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware * load) Signed-off-by: Kevin Lam <kevin.lam@freescale.com> Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Kim Phillips
parent
9e89647889
commit
5e918a98c2
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@ -58,6 +58,10 @@ Conn Clark <clark@esteem.com>
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ESTEEM192E MPC8xx
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Joe D'Abbraccio <ljd015@freescale.com>
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MPC837xERDB MPC837x
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Kári Davíðsson <kd@flaga.is>
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FLAGADM MPC823
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1
MAKEALL
1
MAKEALL
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@ -321,6 +321,7 @@ LIST_83xx=" \
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MPC8360ERDK_33 \
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MPC8360ERDK_66 \
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MPC837XEMDS \
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MPC837XERDB \
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sbc8349 \
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TQM834x \
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"
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3
Makefile
3
Makefile
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@ -1971,6 +1971,9 @@ MPC837XEMDS_HOST_config: unconfig
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fi ;
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@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
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MPC837XERDB_config: unconfig
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@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
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sbc8349_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,28 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC837xERDB
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#
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,150 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spd.h>
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#include <asm/io.h>
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#if defined(CONFIG_SPD_EEPROM)
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#include <spd_sdram.h>
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#endif
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CFG_MEMTEST_START,
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CFG_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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long int initdram(int board_type)
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{
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immap_t *im = (immap_t *) CFG_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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immap_t *im = (immap_t *) CFG_IMMR;
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u32 msize = CFG_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
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udelay(1000);
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_mode2 = CFG_DDR_MODE2;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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sync();
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udelay(1000);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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udelay(2000);
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return CFG_DDR_SIZE;
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}
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#endif /*!CFG_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC837xERDB\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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@ -0,0 +1,59 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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{
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bus_start: CFG_PCI_MEM_BASE,
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phys_start: CFG_PCI_MEM_PHYS,
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size: CFG_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CFG_PCI_MMIO_BASE,
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phys_start: CFG_PCI_MMIO_PHYS,
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size: CFG_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CFG_PCI_IO_BASE,
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phys_start: CFG_PCI_IO_PHYS,
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size: CFG_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg, 0);
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}
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#endif /* CONFIG_PCI */
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@ -0,0 +1,98 @@
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Freescale MPC837xEMDS Board
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-----------------------------------------
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1. Board Description
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The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
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MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
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The MPC837xE-RDB's have the following common features:
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A) 256-MBytes on-board DDR2 unbuffered SDRAM
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B) 8-Mbytes NOR Flash
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C) 32-MBytes NAND Flash
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D) 1 Secure Digital High Speed Card (SDHC) Interface
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E) 1 Gigabit Ethernet
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F) 5-port Ethernet switch (Vitesse 7385)
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G) 1 32-bit, 3.3 V, PCI slot
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H) 1 32-bit, 3.3 V, Mini-PCI slot
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I) 4-port USB 2.0 Hub
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J) 1-port OTG USB
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K) 2 serial ports (top main console)
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L) on board Oscillator: 66M
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The MPC837xE-RDB's have the following differences:
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MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
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SATA controllers 2 0 4
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PCI-Express (mini) 2 2 0
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SGMII Ports 0 2 0
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2. Memory Map
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2.1. The memory map should look pretty much like this:
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Address Range Device Size Port Size
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(Bytes) (Bits)
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=========================== ================= ======= =========
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0x0000_0000 0x0fff_ffff DDR 256M 64
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0x1000_0000 0x7fff_ffff Empty 1.75G -
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0x8000_0000 0x9fff_ffff PCI1 memory space 512M 32
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0xa000_0000 0xbfff_ffff PCI2 memory space 512M 32
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0xc200_0000 0xc2ff_ffff PCI1 I/O space 16M 32
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0xc300_0000 0xc3ff_ffff PCI2 I/O space 16M 32
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0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
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0xe280_0000 0xe47f_ffff NAND Flash 32M 8
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0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
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3. Definitions
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3.1 Explanation of NEW definitions in:
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include/configs/MPC837XERDB.h
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CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360
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CONFIG_MPC837X MPC837x specific
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CONFIG_MPC837XERDB MPC837XEMDS board specific
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4. Compilation
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Assuming you're using BASH shell:
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export CROSS_COMPILE=your-cross-compile-prefix
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cd u-boot
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make distclean
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make MPC837XERDB_config
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make
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5. Downloading and Flashing Images
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5.0 Download over serial line using Kermit:
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loadb $loadaddr
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[Drop to kermit:
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^\c
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send <u-boot-bin-image>
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c
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]
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Or via tftp:
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tftp $loadaddr u-boot.bin
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5.1 Reflash U-boot Image using U-boot
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tftp $loadaddr u-boot.bin
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protect off fe000000 fe0fffff
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erase fe000000 fe0fffff
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cp.b $loadaddr fe000000 $filesize
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6. Additional Notes:
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1) The console is connected to the top RS-232 connector and the
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baudrate for MPC837XE-RDB is 115200bps.
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@ -0,0 +1,596 @@
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
|
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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||||
*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
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#define CONFIG_MPC837XERDB 1
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#define CONFIG_PCI 1
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/*
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* System Clock Setup
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||||
*/
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
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#else
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#define CONFIG_83XX_GENERIC_PCI 1
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#endif
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|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
*/
|
||||
#define CFG_HRCW_LOW (\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_5X1 |\
|
||||
HRCWL_CORE_TO_CSB_2X1)
|
||||
|
||||
#ifdef CONFIG_PCISLAVE
|
||||
#define CFG_HRCW_HIGH (\
|
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LDP_CLEAR)
|
||||
#else
|
||||
#define CFG_HRCW_HIGH (\
|
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LDP_CLEAR)
|
||||
#endif
|
||||
|
||||
/* System performance - define the value i.e. CFG_XXX
|
||||
*/
|
||||
|
||||
/* Arbiter Configuration Register */
|
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
|
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
|
||||
|
||||
/* System Priority Control Regsiter */
|
||||
#define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
|
||||
|
||||
/* System Clock Configuration Register */
|
||||
#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
|
||||
#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
|
||||
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CFG_SICRH 0x08200000
|
||||
#define CFG_SICRL 0x00000000
|
||||
|
||||
/*
|
||||
* Output Buffer Impedance
|
||||
*/
|
||||
#define CFG_OBIR 0x30100000
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
*/
|
||||
#define CFG_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_CLK_CNTL 0x03000000
|
||||
#define CFG_83XX_DDR_USES_CS0
|
||||
|
||||
#define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
|
||||
|
||||
#undef CONFIG_DDR_ECC /* support DDR ECC function */
|
||||
#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
|
||||
|
||||
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_DDR_SIZE 256 /* MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x0000000f
|
||||
#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
|
||||
|
||||
#define CFG_DDR_TIMING_3 0x00000000
|
||||
#define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00220802 */
|
||||
/* 0x00260802 */ /* DDR400 */
|
||||
#define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (13 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (3 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x3935d322 */
|
||||
/* 0x3937d322 */
|
||||
#define CFG_DDR_TIMING_2 0x02984cc8
|
||||
|
||||
#define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x06090100 */
|
||||
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_2T_EN \
|
||||
| SDRAM_CFG_DBW_32)
|
||||
#else
|
||||
#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
|
||||
/* 0x43000000 */
|
||||
#endif
|
||||
#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
|
||||
#define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x0442 << SDRAM_MODE_SD_SHIFT))
|
||||
/* 0x04400442 */ /* DDR400 */
|
||||
#define CFG_DDR_MODE2 0x00000000;
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00040000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x0ef70010
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
|
||||
#define CFG_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
|
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
|
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */
|
||||
#define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFF806FF7 TODO SLOW 8 MB flash size */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_VSC7385_BASE 0xF0000000
|
||||
|
||||
/* VSC7385 Gigabit Switch support */
|
||||
#define CONFIG_VSC7385_ENET
|
||||
#define CFG_BR2_PRELIM 0xf0000801 /* Base address */
|
||||
#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
|
||||
#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CFG_I2C_OFFSET 0x3000
|
||||
#define CFG_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI_MEM_BASE 0x80000000
|
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
|
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_MMIO_BASE 0x90000000
|
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
|
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_IO_BASE 0xE0300000
|
||||
#define CFG_PCI_IO_PHYS 0xE0300000
|
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
|
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000
|
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
#define CFG_TSEC1_OFFSET 0x24000
|
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
|
||||
#define CFG_TSEC2_OFFSET 0x25000
|
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_GMII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 0x1c
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
#undef CONFIG_CMD_ENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CFG_HID0_INIT 0x000000000
|
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
|
||||
#define CFG_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
|
||||
#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
|
||||
|
||||
#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT0L CFG_IBAT0L
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
|
||||
#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
||||
#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT2L CFG_IBAT2L
|
||||
#define CFG_DBAT2U CFG_IBAT2U
|
||||
|
||||
/* L2 Switch: cache-inhibit and guarded */
|
||||
#define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT3L CFG_IBAT3L
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT4U CFG_IBAT4U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT5L CFG_IBAT5L
|
||||
#define CFG_DBAT5U CFG_IBAT5U
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI MEM space: cacheable */
|
||||
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
/* PCI MMIO space: cache-inhibit and guarded */
|
||||
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#else
|
||||
#define CFG_IBAT6L (0)
|
||||
#define CFG_IBAT6U (0)
|
||||
#define CFG_IBAT7L (0)
|
||||
#define CFG_IBAT7U (0)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
||||
#define CONFIG_ETHADDR 00:04:9f:ef:04:01
|
||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
|
||||
|
||||
#define CONFIG_IPADDR 10.0.0.2
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#define CONFIG_GATEWAYIP 10.0.0.1
|
||||
#define CONFIG_NETMASK 255.0.0.0
|
||||
#define CONFIG_NETDEV eth1
|
||||
|
||||
#define CONFIG_HOSTNAME mpc837x_rdb
|
||||
#define CONFIG_ROOTPATH /nfsroot
|
||||
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
#define CONFIG_FDTFILE mpc837x_rdb.dtb
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define XMK_STR(x) #x
|
||||
#define MK_STR(x) XMK_STR(x)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftp $loadaddr $uboot;" \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#undef MK_STR
|
||||
#undef XMK_STR
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue