Remove the deleted files for the SMN42 patch
This commit is contained in:
Peter Pearse
parent
b0d8f5bf0d
commit
5c6d2b5a50
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@ -1,885 +0,0 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <asm/arch/hardware.h>
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#include "spi.h"
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/*
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* Control Registers in Bank 0
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*/
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#define CTL_REG_ERDPTL 0x00
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#define CTL_REG_ERDPTH 0x01
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#define CTL_REG_EWRPTL 0x02
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#define CTL_REG_EWRPTH 0x03
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#define CTL_REG_ETXSTL 0x04
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#define CTL_REG_ETXSTH 0x05
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#define CTL_REG_ETXNDL 0x06
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#define CTL_REG_ETXNDH 0x07
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#define CTL_REG_ERXSTL 0x08
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#define CTL_REG_ERXSTH 0x09
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#define CTL_REG_ERXNDL 0x0A
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#define CTL_REG_ERXNDA 0x0B
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#define CTL_REG_ERXRDPTL 0x0C
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#define CTL_REG_ERXRDPTH 0x0D
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#define CTL_REG_ERXWRPTL 0x0E
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#define CTL_REG_ERXWRPTH 0x0F
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#define CTL_REG_EDMASTL 0x10
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#define CTL_REG_EDMASTH 0x11
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#define CTL_REG_EDMANDL 0x12
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#define CTL_REG_EDMANDH 0x13
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#define CTL_REG_EDMADSTL 0x14
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#define CTL_REG_EDMADSTH 0x15
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#define CTL_REG_EDMACSL 0x16
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#define CTL_REG_EDMACSH 0x17
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/* these are common in all banks */
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#define CTL_REG_EIE 0x1B
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#define CTL_REG_EIR 0x1C
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#define CTL_REG_ESTAT 0x1D
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#define CTL_REG_ECON2 0x1E
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#define CTL_REG_ECON1 0x1F
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/*
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* Control Registers in Bank 1
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*/
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#define CTL_REG_EHT0 0x00
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#define CTL_REG_EHT1 0x01
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#define CTL_REG_EHT2 0x02
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#define CTL_REG_EHT3 0x03
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#define CTL_REG_EHT4 0x04
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#define CTL_REG_EHT5 0x05
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#define CTL_REG_EHT6 0x06
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#define CTL_REG_EHT7 0x07
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#define CTL_REG_EPMM0 0x08
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#define CTL_REG_EPMM1 0x09
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#define CTL_REG_EPMM2 0x0A
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#define CTL_REG_EPMM3 0x0B
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#define CTL_REG_EPMM4 0x0C
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#define CTL_REG_EPMM5 0x0D
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#define CTL_REG_EPMM6 0x0E
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#define CTL_REG_EPMM7 0x0F
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#define CTL_REG_EPMCSL 0x10
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#define CTL_REG_EPMCSH 0x11
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#define CTL_REG_EPMOL 0x14
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#define CTL_REG_EPMOH 0x15
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#define CTL_REG_EWOLIE 0x16
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#define CTL_REG_EWOLIR 0x17
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#define CTL_REG_ERXFCON 0x18
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#define CTL_REG_EPKTCNT 0x19
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/*
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* Control Registers in Bank 2
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*/
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#define CTL_REG_MACON1 0x00
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#define CTL_REG_MACON2 0x01
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#define CTL_REG_MACON3 0x02
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#define CTL_REG_MACON4 0x03
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#define CTL_REG_MABBIPG 0x04
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#define CTL_REG_MAIPGL 0x06
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#define CTL_REG_MAIPGH 0x07
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#define CTL_REG_MACLCON1 0x08
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#define CTL_REG_MACLCON2 0x09
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#define CTL_REG_MAMXFLL 0x0A
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#define CTL_REG_MAMXFLH 0x0B
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#define CTL_REG_MAPHSUP 0x0D
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#define CTL_REG_MICON 0x11
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#define CTL_REG_MICMD 0x12
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#define CTL_REG_MIREGADR 0x14
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#define CTL_REG_MIWRL 0x16
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#define CTL_REG_MIWRH 0x17
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#define CTL_REG_MIRDL 0x18
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#define CTL_REG_MIRDH 0x19
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/*
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* Control Registers in Bank 3
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*/
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#define CTL_REG_MAADR1 0x00
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#define CTL_REG_MAADR0 0x01
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#define CTL_REG_MAADR3 0x02
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#define CTL_REG_MAADR2 0x03
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#define CTL_REG_MAADR5 0x04
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#define CTL_REG_MAADR4 0x05
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#define CTL_REG_EBSTSD 0x06
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#define CTL_REG_EBSTCON 0x07
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#define CTL_REG_EBSTCSL 0x08
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#define CTL_REG_EBSTCSH 0x09
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#define CTL_REG_MISTAT 0x0A
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#define CTL_REG_EREVID 0x12
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#define CTL_REG_ECOCON 0x15
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#define CTL_REG_EFLOCON 0x17
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#define CTL_REG_EPAUSL 0x18
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#define CTL_REG_EPAUSH 0x19
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/*
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* PHY Register
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*/
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#define PHY_REG_PHID1 0x02
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#define PHY_REG_PHID2 0x03
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/*
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* Receive Filter Register (ERXFCON) bits
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*/
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#define ENC_RFR_UCEN 0x80
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#define ENC_RFR_ANDOR 0x40
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#define ENC_RFR_CRCEN 0x20
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#define ENC_RFR_PMEN 0x10
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#define ENC_RFR_MPEN 0x08
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#define ENC_RFR_HTEN 0x04
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#define ENC_RFR_MCEN 0x02
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#define ENC_RFR_BCEN 0x01
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/*
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* ECON1 Register Bits
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*/
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#define ENC_ECON1_TXRST 0x80
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#define ENC_ECON1_RXRST 0x40
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#define ENC_ECON1_DMAST 0x20
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#define ENC_ECON1_CSUMEN 0x10
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#define ENC_ECON1_TXRTS 0x08
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#define ENC_ECON1_RXEN 0x04
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#define ENC_ECON1_BSEL1 0x02
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#define ENC_ECON1_BSEL0 0x01
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/*
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* ECON2 Register Bits
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*/
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#define ENC_ECON2_AUTOINC 0x80
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#define ENC_ECON2_PKTDEC 0x40
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#define ENC_ECON2_PWRSV 0x20
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#define ENC_ECON2_VRPS 0x08
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/*
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* EIR Register Bits
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*/
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#define ENC_EIR_PKTIF 0x40
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#define ENC_EIR_DMAIF 0x20
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#define ENC_EIR_LINKIF 0x10
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#define ENC_EIR_TXIF 0x08
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#define ENC_EIR_WOLIF 0x04
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#define ENC_EIR_TXERIF 0x02
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#define ENC_EIR_RXERIF 0x01
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/*
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* ESTAT Register Bits
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*/
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#define ENC_ESTAT_INT 0x80
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#define ENC_ESTAT_LATECOL 0x10
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#define ENC_ESTAT_RXBUSY 0x04
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#define ENC_ESTAT_TXABRT 0x02
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#define ENC_ESTAT_CLKRDY 0x01
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/*
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* EIE Register Bits
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*/
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#define ENC_EIE_INTIE 0x80
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#define ENC_EIE_PKTIE 0x40
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#define ENC_EIE_DMAIE 0x20
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#define ENC_EIE_LINKIE 0x10
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#define ENC_EIE_TXIE 0x08
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#define ENC_EIE_WOLIE 0x04
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#define ENC_EIE_TXERIE 0x02
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#define ENC_EIE_RXERIE 0x01
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/*
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* MACON1 Register Bits
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*/
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#define ENC_MACON1_LOOPBK 0x10
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#define ENC_MACON1_TXPAUS 0x08
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#define ENC_MACON1_RXPAUS 0x04
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#define ENC_MACON1_PASSALL 0x02
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#define ENC_MACON1_MARXEN 0x01
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/*
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* MACON2 Register Bits
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*/
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#define ENC_MACON2_MARST 0x80
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#define ENC_MACON2_RNDRST 0x40
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#define ENC_MACON2_MARXRST 0x08
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#define ENC_MACON2_RFUNRST 0x04
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#define ENC_MACON2_MATXRST 0x02
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#define ENC_MACON2_TFUNRST 0x01
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/*
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* MACON3 Register Bits
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*/
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#define ENC_MACON3_PADCFG2 0x80
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#define ENC_MACON3_PADCFG1 0x40
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#define ENC_MACON3_PADCFG0 0x20
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#define ENC_MACON3_TXCRCEN 0x10
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#define ENC_MACON3_PHDRLEN 0x08
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#define ENC_MACON3_HFRMEN 0x04
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#define ENC_MACON3_FRMLNEN 0x02
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#define ENC_MACON3_FULDPX 0x01
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/*
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* MICMD Register Bits
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*/
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#define ENC_MICMD_MIISCAN 0x02
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#define ENC_MICMD_MIIRD 0x01
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/*
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* MISTAT Register Bits
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*/
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#define ENC_MISTAT_NVALID 0x04
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#define ENC_MISTAT_SCAN 0x02
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#define ENC_MISTAT_BUSY 0x01
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/*
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* PHID1 and PHID2 values
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*/
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#define ENC_PHID1_VALUE 0x0083
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#define ENC_PHID2_VALUE 0x1400
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#define ENC_PHID2_MASK 0xFC00
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#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
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#define ENC_RESET 0x00020000 /* pin P1.17 */
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#define FAILSAFE_VALUE 5000
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/*
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* Controller memory layout:
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*
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* 0x0000 - 0x17ff 6k bytes receive buffer
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* 0x1800 - 0x1fff 2k bytes transmit buffer
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*/
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/* Use the lower memory for receiver buffer. See errata pt. 5 */
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#define ENC_RX_BUF_START 0x0000
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#define ENC_TX_BUF_START 0x1800
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/* maximum frame length */
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#define ENC_MAX_FRM_LEN 1518
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#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
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#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
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#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
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static unsigned char encReadReg (unsigned char regNo);
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static void encWriteReg (unsigned char regNo, unsigned char data);
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static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
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static void encReadBuff (unsigned short length, unsigned char *pBuff);
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static void encWriteBuff (unsigned short length, unsigned char *pBuff);
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static void encBitSet (unsigned char regNo, unsigned char data);
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static void encBitClr (unsigned char regNo, unsigned char data);
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static void encReset (void);
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static void encInit (unsigned char *pEthAddr);
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static unsigned short phyRead (unsigned char addr);
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static void encPoll (void);
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static void encRx (void);
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#define m_nic_read(reg) encReadReg(reg)
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#define m_nic_write(reg, data) encWriteReg(reg, data)
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#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
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#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
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#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
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/* bit field set */
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#define m_nic_bfs(reg, data) encBitSet(reg, data)
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/* bit field clear */
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#define m_nic_bfc(reg, data) encBitClr(reg, data)
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static unsigned char bank = 0; /* current bank in enc28j60 */
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static unsigned char next_pointer_lsb;
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static unsigned char next_pointer_msb;
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static unsigned char buffer[ENC_MAX_FRM_LEN];
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static int rxResetCounter = 0;
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#define RX_RESET_COUNTER 1000;
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/*-----------------------------------------------------------------------------
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* Returns 0 when failes otherwize 1
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*/
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int eth_init (bd_t * bis)
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{
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/* configure GPIO */
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(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
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(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
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/* CS and RESET active low */
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PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
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PUT32 (IO1SET, ENC_RESET);
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spi_init ();
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/* initialize controller */
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encReset ();
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encInit (bis->bi_enetaddr);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
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return 0;
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}
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int eth_send (volatile void *packet, int length)
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{
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/* check frame length, etc. */
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/* TODO: */
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/* switch to bank 0 */
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m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
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/* set EWRPT */
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m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
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m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
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/* set ETXST */
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m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
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m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
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/* write packet */
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m_nic_write_data (length, (unsigned char *) packet);
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/* set ETXND */
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m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
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m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
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/* set ECON1.TXRTS */
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
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return 0;
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}
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/*****************************************************************************
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* This function resets the receiver only. This function may be called from
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* interrupt-context.
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*/
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static void encReceiverReset (void)
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{
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unsigned char econ1;
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econ1 = m_nic_read (CTL_REG_ECON1);
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if ((econ1 & ENC_ECON1_RXRST) == 0) {
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
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rxResetCounter = RX_RESET_COUNTER;
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}
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}
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/*****************************************************************************
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* receiver reset timer
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*/
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static void encReceiverResetCallback (void)
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{
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
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}
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/*-----------------------------------------------------------------------------
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* Check for received packets. Call NetReceive for each packet. The return
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* value is ignored by the caller.
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*/
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int eth_rx (void)
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{
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if (rxResetCounter > 0 && --rxResetCounter == 0) {
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encReceiverResetCallback ();
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}
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encPoll ();
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return 0;
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}
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void eth_halt (void)
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{
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
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}
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/*****************************************************************************/
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static void encPoll (void)
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{
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unsigned char eir_reg;
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volatile unsigned char estat_reg;
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unsigned char pkt_cnt;
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/* clear global interrupt enable bit in enc28j60 */
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m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
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estat_reg = m_nic_read (CTL_REG_ESTAT);
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eir_reg = m_nic_read (CTL_REG_EIR);
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if (eir_reg & ENC_EIR_TXIF) {
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/* clear TXIF bit in EIR */
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m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
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}
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/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
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/* move to bank 1 */
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
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/* read pktcnt */
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pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
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if (pkt_cnt > 0) {
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if ((eir_reg & ENC_EIR_PKTIF) == 0) {
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/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
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}
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encRx ();
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/* clear PKTIF bit in EIR, this should not need to be done but it
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seems like we get problems if we do not */
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
|
||||
}
|
||||
|
||||
if (eir_reg & ENC_EIR_RXERIF) {
|
||||
printf ("encPoll: rx error\n");
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
|
||||
}
|
||||
if (eir_reg & ENC_EIR_TXERIF) {
|
||||
printf ("encPoll: tx error\n");
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
|
||||
}
|
||||
|
||||
/* set global interrupt enable bit in enc28j60 */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
}
|
||||
|
||||
static void encRx (void)
|
||||
{
|
||||
unsigned short pkt_len;
|
||||
unsigned short copy_len;
|
||||
unsigned short status;
|
||||
unsigned char eir_reg;
|
||||
unsigned char pkt_cnt = 0;
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||
|
||||
do {
|
||||
m_nic_read_data (6, buffer);
|
||||
next_pointer_lsb = buffer[0];
|
||||
next_pointer_msb = buffer[1];
|
||||
pkt_len = buffer[2];
|
||||
pkt_len |= (unsigned short) buffer[3] << 8;
|
||||
status = buffer[4];
|
||||
status |= (unsigned short) buffer[5] << 8;
|
||||
|
||||
if (pkt_len <= ENC_MAX_FRM_LEN) {
|
||||
copy_len = pkt_len;
|
||||
} else {
|
||||
copy_len = 0;
|
||||
/* p_priv->stats.rx_dropped++; */
|
||||
/* we will drop this packet */
|
||||
}
|
||||
|
||||
if ((status & (1L << 7)) == 0) { /* check Received Ok bit */
|
||||
copy_len = 0;
|
||||
/* p_priv->stats.rx_errors++; */
|
||||
}
|
||||
|
||||
if (copy_len > 0) {
|
||||
m_nic_read_data (copy_len, buffer);
|
||||
}
|
||||
|
||||
/* advance read pointer to next pointer */
|
||||
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||
|
||||
/* decrease packet counter */
|
||||
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
||||
/* read pktcnt */
|
||||
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1,
|
||||
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
if (copy_len == 0) {
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
encReceiverReset ();
|
||||
printf ("eth_rx: copy_len=0\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
NetReceive ((unsigned char *) buffer, pkt_len);
|
||||
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
||||
m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
|
||||
}
|
||||
|
||||
static void encWriteReg (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x40 | regNo); /* write in regNo */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* write reg 0x1f */
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
|
||||
{
|
||||
unsigned char readback;
|
||||
int i;
|
||||
|
||||
spi_lock ();
|
||||
|
||||
for (i = 0; i < c; i++) {
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x40 | regNo); /* write in regNo */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* write reg 0x1f */
|
||||
|
||||
enc_disable ();
|
||||
|
||||
spi_unlock (); /* we must unlock spi first */
|
||||
|
||||
readback = encReadReg (regNo);
|
||||
|
||||
spi_lock ();
|
||||
|
||||
if (readback == data)
|
||||
break;
|
||||
}
|
||||
spi_unlock ();
|
||||
|
||||
if (i == c) {
|
||||
printf ("enc28j60: write reg %d failed\n", regNo);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned char encReadReg (unsigned char regNo)
|
||||
{
|
||||
unsigned char rxByte;
|
||||
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* read reg 0x1f */
|
||||
|
||||
bank = spi_read () & 0x3;
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (regNo);
|
||||
rxByte = spi_read ();
|
||||
|
||||
/* check if MAC or MII register */
|
||||
if (((bank == 2) && (regNo <= 0x1a)) ||
|
||||
((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
|
||||
/* ignore first byte and read another byte */
|
||||
rxByte = spi_read ();
|
||||
}
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
|
||||
return rxByte;
|
||||
}
|
||||
|
||||
static void encReadBuff (unsigned short length, unsigned char *pBuff)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x20 | 0x1a); /* read buffer memory */
|
||||
|
||||
while (length--) {
|
||||
if (pBuff != NULL)
|
||||
*pBuff++ = spi_read ();
|
||||
else
|
||||
spi_write (0);
|
||||
}
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x60 | 0x1a); /* write buffer memory */
|
||||
|
||||
spi_write (0x00); /* control byte */
|
||||
|
||||
while (length--)
|
||||
spi_write (*pBuff++);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encBitSet (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x80 | regNo); /* bit field set */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encBitClr (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0xA0 | regNo); /* bit field clear */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encReset (void)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0xff); /* soft reset */
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
|
||||
/* sleep 1 ms. See errata pt. 2 */
|
||||
udelay (1000);
|
||||
|
||||
#if 0
|
||||
(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
|
||||
mdelay (5);
|
||||
(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void encInit (unsigned char *pEthAddr)
|
||||
{
|
||||
unsigned short phid1 = 0;
|
||||
unsigned short phid2 = 0;
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
/*
|
||||
* Setup the buffer space. The reset values are valid for the
|
||||
* other pointers.
|
||||
*/
|
||||
#if 0
|
||||
/* We shall not write to ERXST, see errata pt. 5. Instead we
|
||||
have to make sure that ENC_RX_BUS_START is 0. */
|
||||
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
#endif
|
||||
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
|
||||
next_pointer_msb = (ENC_RX_BUF_START >> 8);
|
||||
|
||||
/*
|
||||
* For tracking purposes, the ERXRDPT registers should be programmed with
|
||||
* the same value. This is the read pointer.
|
||||
*/
|
||||
m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
|
||||
m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
/* Setup receive filters. */
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
||||
/* OR-filtering, Unicast, CRC-check and broadcast */
|
||||
m_nic_write_retry (CTL_REG_ERXFCON,
|
||||
(ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
|
||||
|
||||
/* Wait for Oscillator Start-up Timer (OST). */
|
||||
while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if (cnt++ >= 1000) {
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* verify identification */
|
||||
phid1 = phyRead (PHY_REG_PHID1);
|
||||
phid2 = phyRead (PHY_REG_PHID2);
|
||||
|
||||
if (phid1 != ENC_PHID1_VALUE
|
||||
|| (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
|
||||
printf ("ERROR: failed to identify controller\n");
|
||||
printf ("phid1 = %x, phid2 = %x\n",
|
||||
phid1, (phid2 & ENC_PHID2_MASK));
|
||||
printf ("should be phid1 = %x, phid2 = %x\n",
|
||||
ENC_PHID1_VALUE, ENC_PHID2_VALUE);
|
||||
}
|
||||
|
||||
/*
|
||||
* --- MAC Initialization ---
|
||||
*/
|
||||
|
||||
/* Pull MAC out of Reset */
|
||||
|
||||
/* switch to bank 2 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
/* clear MAC reset bits */
|
||||
m_nic_write_retry (CTL_REG_MACON2, 0, 1);
|
||||
|
||||
/* enable MAC to receive frames */
|
||||
m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
|
||||
|
||||
/* configure pad, tx-crc and duplex */
|
||||
/* TODO maybe enable FRMLNEN */
|
||||
m_nic_write_retry (CTL_REG_MACON3,
|
||||
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
|
||||
|
||||
/* set maximum frame length */
|
||||
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
|
||||
m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
|
||||
|
||||
/*
|
||||
* Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
|
||||
* and 0x15 for full duplex.
|
||||
*/
|
||||
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
|
||||
|
||||
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
||||
m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
|
||||
|
||||
/*
|
||||
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
||||
* 0x0c for half-duplex. Nothing for full-duplex
|
||||
*/
|
||||
m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
|
||||
|
||||
/* set MAC address */
|
||||
|
||||
/* switch to bank 3 */
|
||||
m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
|
||||
|
||||
m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
|
||||
|
||||
/*
|
||||
* Receive settings
|
||||
*/
|
||||
|
||||
/* auto-increment RX-pointer when reading a received packet */
|
||||
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
|
||||
|
||||
/* enable interrupts */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read PHY registers.
|
||||
*
|
||||
* NOTE! This function will change to Bank 2.
|
||||
*
|
||||
* Params:
|
||||
* [in] addr address of the register to read
|
||||
*
|
||||
* Returns:
|
||||
* The value in the register
|
||||
*/
|
||||
static unsigned short phyRead (unsigned char addr)
|
||||
{
|
||||
unsigned short ret = 0;
|
||||
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* write address to MIREGADR */
|
||||
m_nic_write (CTL_REG_MIREGADR, addr);
|
||||
|
||||
/* set MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
|
||||
|
||||
/* poll MISTAT.BUSY bit until operation is complete */
|
||||
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if (cnt++ >= 1000) {
|
||||
/* GJ - this seems extremely dangerous! */
|
||||
/* printf("#"); */
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, 0);
|
||||
|
||||
ret = (m_nic_read (CTL_REG_MIRDH) << 8);
|
||||
ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
IAP_ADDRESS: .word 0x7FFFFFF1
|
||||
|
||||
.globl iap_entry
|
||||
iap_entry:
|
||||
ldr r2, IAP_ADDRESS
|
||||
bx r2
|
||||
mov pc, lr
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <part.h>
|
||||
#include <fat.h>
|
||||
#include "mmc_hw.h"
|
||||
#include "spi.h"
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
|
||||
#undef MMC_DEBUG
|
||||
|
||||
static block_dev_desc_t mmc_dev;
|
||||
|
||||
/* these are filled out by a call to mmc_hw_get_parameters */
|
||||
static int hw_size; /* in kbytes */
|
||||
static int hw_nr_sects;
|
||||
static int hw_sect_size; /* in bytes */
|
||||
|
||||
block_dev_desc_t * mmc_get_dev(int dev)
|
||||
{
|
||||
return (block_dev_desc_t *)(&mmc_dev);
|
||||
}
|
||||
|
||||
unsigned long mmc_block_read(int dev,
|
||||
unsigned long start,
|
||||
lbaint_t blkcnt,
|
||||
unsigned long *buffer)
|
||||
{
|
||||
unsigned long rc = 0;
|
||||
unsigned char *p = (unsigned char *)buffer;
|
||||
unsigned long i;
|
||||
unsigned long addr = start;
|
||||
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
|
||||
(unsigned long)blkcnt);
|
||||
#endif
|
||||
|
||||
for(i = 0; i < (unsigned long)blkcnt; i++) {
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
|
||||
#endif
|
||||
(void)mmc_read_sector(addr, p);
|
||||
rc++;
|
||||
addr++;
|
||||
p += hw_sect_size;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Read hardware paramterers (sector size, size, number of sectors)
|
||||
*/
|
||||
static int mmc_hw_get_parameters(void)
|
||||
{
|
||||
unsigned char csddata[16];
|
||||
unsigned int sizemult;
|
||||
unsigned int size;
|
||||
|
||||
mmc_read_csd(csddata);
|
||||
hw_sect_size = 1<<(csddata[5] & 0x0f);
|
||||
size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
|
||||
sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
|
||||
hw_nr_sects = (size+1)*(1<<(sizemult+2));
|
||||
hw_size = hw_nr_sects*hw_sect_size/1024;
|
||||
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
|
||||
"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
if (verbose)
|
||||
printf("mmc_init\n");
|
||||
|
||||
spi_init();
|
||||
mmc_hw_init();
|
||||
|
||||
mmc_hw_get_parameters();
|
||||
|
||||
mmc_dev.if_type = IF_TYPE_MMC;
|
||||
mmc_dev.part_type = PART_TYPE_DOS;
|
||||
mmc_dev.dev = 0;
|
||||
mmc_dev.lun = 0;
|
||||
mmc_dev.type = 0;
|
||||
mmc_dev.blksz = hw_sect_size;
|
||||
mmc_dev.lba = hw_nr_sects;
|
||||
sprintf((char*)mmc_dev.vendor, "Unknown vendor");
|
||||
sprintf((char*)mmc_dev.product, "Unknown product");
|
||||
sprintf((char*)mmc_dev.revision, "N/A");
|
||||
mmc_dev.removable = 0; /* should be true??? */
|
||||
mmc_dev.block_read = mmc_block_read;
|
||||
|
||||
fat_register_device(&mmc_dev, 1);
|
||||
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mmc_write(uchar * src, ulong dst, int size)
|
||||
{
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
|
||||
#endif
|
||||
/* Since mmc2info always returns 0 this function will never be called */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar * dst, int size)
|
||||
{
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
|
||||
#endif
|
||||
/* Since mmc2info always returns 0 this function will never be called */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
/* This function is used by cmd_cp to determine if source or destination
|
||||
address resides on MMC-card or not. We do not support copy to and from
|
||||
MMC-card so we always return 0. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMC */
|
||||
|
|
@ -1,233 +0,0 @@
|
|||
/*
|
||||
This code was original written by Ulrich Radig and modified by
|
||||
Embedded Artists AB (www.embeddedartists.com).
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "spi.h"
|
||||
|
||||
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
|
||||
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
|
||||
#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
|
||||
|
||||
static unsigned char Write_Command_MMC (unsigned char *CMD);
|
||||
static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
|
||||
unsigned short int Bytes);
|
||||
|
||||
/* initialize the hardware */
|
||||
int mmc_hw_init(void)
|
||||
{
|
||||
unsigned long a;
|
||||
unsigned short int Timeout = 0;
|
||||
unsigned char b;
|
||||
unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
|
||||
|
||||
/* set-up GPIO and SPI */
|
||||
(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
|
||||
(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
|
||||
|
||||
MMC_Disable();
|
||||
|
||||
spi_lock();
|
||||
spi_set_clock(248);
|
||||
spi_set_cfg(0, 1, 0);
|
||||
MMC_Enable();
|
||||
|
||||
/* waste some time */
|
||||
for(a=0; a < 20000; a++)
|
||||
asm("nop");
|
||||
|
||||
/* Put the MMC/SD-card into SPI-mode */
|
||||
for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
|
||||
spi_write(0xff);
|
||||
|
||||
/* Sends command CMD0 to MMC/SD-card */
|
||||
while (Write_Command_MMC(CMD) != 1) {
|
||||
if (Timeout++ > 200) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return(1); /* Abort with command 1 (return 1) */
|
||||
}
|
||||
}
|
||||
/* Sends Command CMD1 an MMC/SD-card */
|
||||
Timeout = 0;
|
||||
CMD[0] = 0x41;/* Command 1 */
|
||||
CMD[5] = 0xFF;
|
||||
|
||||
while (Write_Command_MMC(CMD) != 0) {
|
||||
if (Timeout++ > 200) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return (2); /* Abort with command 2 (return 2) */
|
||||
}
|
||||
}
|
||||
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Sends a command to the MMC/SD-card
|
||||
######################################################################### */
|
||||
static unsigned char Write_Command_MMC (unsigned char *CMD)
|
||||
{
|
||||
unsigned char a, tmp = 0xff;
|
||||
unsigned short int Timeout = 0;
|
||||
|
||||
MMC_Disable();
|
||||
spi_write(0xFF);
|
||||
MMC_Enable();
|
||||
|
||||
for (a = 0; a < 0x06; a++)
|
||||
spi_write(*CMD++);
|
||||
|
||||
while (tmp == 0xff) {
|
||||
tmp = spi_read();
|
||||
if (Timeout++ > 5000)
|
||||
break;
|
||||
}
|
||||
|
||||
return (tmp);
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to read the CID register from the MMC/SD-card (16 bytes)
|
||||
######################################################################### */
|
||||
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
|
||||
int Bytes)
|
||||
{
|
||||
unsigned short int a;
|
||||
|
||||
spi_lock();
|
||||
mmc_spi_cfg();
|
||||
MMC_Enable();
|
||||
|
||||
if (Write_Command_MMC(CMD) != 0) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return;
|
||||
}
|
||||
|
||||
while (spi_read() != 0xfe) {};
|
||||
for (a = 0; a < Bytes; a++)
|
||||
*Buffer++ = spi_read();
|
||||
|
||||
/* Read the CRC-byte */
|
||||
spi_read(); /* CRC - byte is discarded */
|
||||
spi_read(); /* CRC - byte is discarded */
|
||||
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to read a block (512 bytes) from the MMC/SD-card
|
||||
######################################################################### */
|
||||
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
|
||||
{
|
||||
/* Command 16 to read aBlocks from the MMC/SD - caed */
|
||||
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
|
||||
|
||||
/* The addres on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is
|
||||
placed into the command */
|
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */
|
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24);
|
||||
CMD[2] = ((addr & 0x00FF0000) >> 16);
|
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 );
|
||||
|
||||
MMC_Read_Block(CMD, Buffer, 512);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to write a block (512 byte) to the MMC/SD-card
|
||||
######################################################################### */
|
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
|
||||
{
|
||||
unsigned char tmp, a;
|
||||
unsigned short int b;
|
||||
/* Command 24 to write a block to the MMC/SD - card */
|
||||
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
|
||||
|
||||
/* The addres on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is
|
||||
placed into the command */
|
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */
|
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24);
|
||||
CMD[2] = ((addr & 0x00FF0000) >> 16);
|
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 );
|
||||
|
||||
spi_lock();
|
||||
mmc_spi_cfg();
|
||||
MMC_Enable();
|
||||
|
||||
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
|
||||
tmp = Write_Command_MMC(CMD);
|
||||
if (tmp != 0) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return(tmp);
|
||||
}
|
||||
|
||||
/* Do a short delay and send a clock-pulse to the MMC/SD-card */
|
||||
for (a = 0; a < 100; a++)
|
||||
spi_read();
|
||||
|
||||
/* Send a start byte to the MMC/SD-card */
|
||||
spi_write(0xFE);
|
||||
|
||||
/* Write the block (512 bytes) to the MMC/SD-card */
|
||||
for (b = 0; b < 512; b++)
|
||||
spi_write(*Buffer++);
|
||||
|
||||
/* write the CRC-Byte */
|
||||
spi_write(0xFF); /* write a dummy CRC */
|
||||
spi_write(0xFF); /* CRC code is not used */
|
||||
|
||||
/* Wait for MMC/SD-card busy */
|
||||
while (spi_read() != 0xff) {};
|
||||
|
||||
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* #########################################################################
|
||||
Routine to read the CSD register from the MMC/SD-card (16 bytes)
|
||||
######################################################################### */
|
||||
unsigned char mmc_read_csd (unsigned char *Buffer)
|
||||
{
|
||||
/* Command to read the CSD register */
|
||||
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
|
||||
|
||||
MMC_Read_Block(CMD, Buffer, 16);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
This module implements a linux character device driver for the 24c256 chip.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _MMC_HW_
|
||||
#define _MMC_HW_
|
||||
|
||||
unsigned char mmc_read_csd(unsigned char *Buffer);
|
||||
unsigned char mmc_read_sector (unsigned long addr,
|
||||
unsigned char *Buffer);
|
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
|
||||
int mmc_hw_init(void);
|
||||
|
||||
#endif /* _MMC_HW_ */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
This module implements an interface to the SPI on the lpc22xx.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "spi.h"
|
||||
|
||||
unsigned long spi_flags;
|
||||
unsigned char spi_idle = 0x00;
|
||||
|
||||
int spi_init(void)
|
||||
{
|
||||
unsigned long pinsel0_value;
|
||||
|
||||
/* activate spi pins */
|
||||
pinsel0_value = GET32(PINSEL0);
|
||||
pinsel0_value &= ~(0xFFl << 8);
|
||||
pinsel0_value |= (0x55l << 8);
|
||||
PUT32(PINSEL0, pinsel0_value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
This file defines the interface to the lpc22xx SPI module.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This file may be included in software not adhering to the GPL.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef SPI_H
|
||||
#define SPI_H
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define SPIF 0x80
|
||||
|
||||
#define spi_lock() disable_interrupts();
|
||||
#define spi_unlock() enable_interrupts();
|
||||
|
||||
extern unsigned long spi_flags;
|
||||
extern unsigned char spi_idle;
|
||||
|
||||
int spi_init(void);
|
||||
|
||||
static inline unsigned char spi_read(void)
|
||||
{
|
||||
unsigned char b;
|
||||
|
||||
PUT8(S0SPDR, spi_idle);
|
||||
while (!(GET8(S0SPSR) & SPIF));
|
||||
b = GET8(S0SPDR);
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
static inline void spi_write(unsigned char b)
|
||||
{
|
||||
PUT8(S0SPDR, b);
|
||||
while (!(GET8(S0SPSR) & SPIF));
|
||||
GET8(S0SPDR); /* this will clear the SPIF bit */
|
||||
}
|
||||
|
||||
static inline void spi_set_clock(unsigned char clk_value)
|
||||
{
|
||||
PUT8(S0SPCCR, clk_value);
|
||||
}
|
||||
|
||||
static inline void spi_set_cfg(unsigned char phase,
|
||||
unsigned char polarity,
|
||||
unsigned char lsbf)
|
||||
{
|
||||
unsigned char v = 0x20; /* master bit set */
|
||||
|
||||
if (phase)
|
||||
v |= 0x08; /* set phase bit */
|
||||
if (polarity) {
|
||||
v |= 0x10; /* set polarity bit */
|
||||
spi_idle = 0xFF;
|
||||
} else {
|
||||
spi_idle = 0x00;
|
||||
}
|
||||
if (lsbf)
|
||||
v |= 0x40; /* set lsbf bit */
|
||||
|
||||
PUT8(S0SPCR, v);
|
||||
}
|
||||
#endif /* SPI_H */
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
#ifndef __LPC2292_REGISTERS_H
|
||||
#define __LPC2292_REGISTERS_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* Macros for reading/writing registers */
|
||||
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
|
||||
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
|
||||
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
|
||||
#define GET8(reg) (*(volatile unsigned char*)(reg))
|
||||
#define GET16(reg) (*(volatile unsigned short*)(reg))
|
||||
#define GET32(reg) (*(volatile unsigned int*)(reg))
|
||||
|
||||
/* External Memory Controller */
|
||||
|
||||
#define BCFG0 0xFFE00000 /* 32-bits */
|
||||
#define BCFG1 0xFFE00004 /* 32-bits */
|
||||
#define BCFG2 0xFFE00008 /* 32-bits */
|
||||
#define BCFG3 0xFFE0000c /* 32-bits */
|
||||
|
||||
/* System Control Block */
|
||||
|
||||
#define EXTINT 0xE01FC140
|
||||
#define EXTWAKE 0xE01FC144
|
||||
#define EXTMODE 0xE01FC148
|
||||
#define EXTPOLAR 0xE01FC14C
|
||||
#define MEMMAP 0xE01FC040
|
||||
#define PLLCON 0xE01FC080
|
||||
#define PLLCFG 0xE01FC084
|
||||
#define PLLSTAT 0xE01FC088
|
||||
#define PLLFEED 0xE01FC08C
|
||||
#define PCON 0xE01FC0C0
|
||||
#define PCONP 0xE01FC0C4
|
||||
#define VPBDIV 0xE01FC100
|
||||
|
||||
/* Memory Acceleration Module */
|
||||
|
||||
#define MAMCR 0xE01FC000
|
||||
#define MAMTIM 0xE01FC004
|
||||
|
||||
/* Vectored Interrupt Controller */
|
||||
|
||||
#define VICIRQStatus 0xFFFFF000
|
||||
#define VICFIQStatus 0xFFFFF004
|
||||
#define VICRawIntr 0xFFFFF008
|
||||
#define VICIntSelect 0xFFFFF00C
|
||||
#define VICIntEnable 0xFFFFF010
|
||||
#define VICIntEnClr 0xFFFFF014
|
||||
#define VICSoftInt 0xFFFFF018
|
||||
#define VICSoftIntClear 0xFFFFF01C
|
||||
#define VICProtection 0xFFFFF020
|
||||
#define VICVectAddr 0xFFFFF030
|
||||
#define VICDefVectAddr 0xFFFFF034
|
||||
#define VICVectAddr0 0xFFFFF100
|
||||
#define VICVectAddr1 0xFFFFF104
|
||||
#define VICVectAddr2 0xFFFFF108
|
||||
#define VICVectAddr3 0xFFFFF10C
|
||||
#define VICVectAddr4 0xFFFFF110
|
||||
#define VICVectAddr5 0xFFFFF114
|
||||
#define VICVectAddr6 0xFFFFF118
|
||||
#define VICVectAddr7 0xFFFFF11C
|
||||
#define VICVectAddr8 0xFFFFF120
|
||||
#define VICVectAddr9 0xFFFFF124
|
||||
#define VICVectAddr10 0xFFFFF128
|
||||
#define VICVectAddr11 0xFFFFF12C
|
||||
#define VICVectAddr12 0xFFFFF130
|
||||
#define VICVectAddr13 0xFFFFF134
|
||||
#define VICVectAddr14 0xFFFFF138
|
||||
#define VICVectAddr15 0xFFFFF13C
|
||||
#define VICVectCntl0 0xFFFFF200
|
||||
#define VICVectCntl1 0xFFFFF204
|
||||
#define VICVectCntl2 0xFFFFF208
|
||||
#define VICVectCntl3 0xFFFFF20C
|
||||
#define VICVectCntl4 0xFFFFF210
|
||||
#define VICVectCntl5 0xFFFFF214
|
||||
#define VICVectCntl6 0xFFFFF218
|
||||
#define VICVectCntl7 0xFFFFF21C
|
||||
#define VICVectCntl8 0xFFFFF220
|
||||
#define VICVectCntl9 0xFFFFF224
|
||||
#define VICVectCntl10 0xFFFFF228
|
||||
#define VICVectCntl11 0xFFFFF22C
|
||||
#define VICVectCntl12 0xFFFFF230
|
||||
#define VICVectCntl13 0xFFFFF234
|
||||
#define VICVectCntl14 0xFFFFF238
|
||||
#define VICVectCntl15 0xFFFFF23C
|
||||
|
||||
/* Pin connect block */
|
||||
|
||||
#define PINSEL0 0xE002C000 /* 32 bits */
|
||||
#define PINSEL1 0xE002C004 /* 32 bits */
|
||||
#define PINSEL2 0xE002C014 /* 32 bits */
|
||||
|
||||
/* GPIO */
|
||||
|
||||
#define IO0PIN 0xE0028000
|
||||
#define IO0SET 0xE0028004
|
||||
#define IO0DIR 0xE0028008
|
||||
#define IO0CLR 0xE002800C
|
||||
#define IO1PIN 0xE0028010
|
||||
#define IO1SET 0xE0028014
|
||||
#define IO1DIR 0xE0028018
|
||||
#define IO1CLR 0xE002801C
|
||||
#define IO2PIN 0xE0028020
|
||||
#define IO2SET 0xE0028024
|
||||
#define IO2DIR 0xE0028028
|
||||
#define IO2CLR 0xE002802C
|
||||
#define IO3PIN 0xE0028030
|
||||
#define IO3SET 0xE0028034
|
||||
#define IO3DIR 0xE0028038
|
||||
#define IO3CLR 0xE002803C
|
||||
|
||||
/* Uarts */
|
||||
|
||||
#define U0RBR 0xE000C000
|
||||
#define U0THR 0xE000C000
|
||||
#define U0IER 0xE000C004
|
||||
#define U0IIR 0xE000C008
|
||||
#define U0FCR 0xE000C008
|
||||
#define U0LCR 0xE000C00C
|
||||
#define U0LSR 0xE000C014
|
||||
#define U0SCR 0xE000C01C
|
||||
#define U0DLL 0xE000C000
|
||||
#define U0DLM 0xE000C004
|
||||
|
||||
#define U1RBR 0xE0010000
|
||||
#define U1THR 0xE0010000
|
||||
#define U1IER 0xE0010004
|
||||
#define U1IIR 0xE0010008
|
||||
#define U1FCR 0xE0010008
|
||||
#define U1LCR 0xE001000C
|
||||
#define U1MCR 0xE0010010
|
||||
#define U1LSR 0xE0010014
|
||||
#define U1MSR 0xE0010018
|
||||
#define U1SCR 0xE001001C
|
||||
#define U1DLL 0xE0010000
|
||||
#define U1DLM 0xE0010004
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define I2CONSET 0xE001C000
|
||||
#define I2STAT 0xE001C004
|
||||
#define I2DAT 0xE001C008
|
||||
#define I2ADR 0xE001C00C
|
||||
#define I2SCLH 0xE001C010
|
||||
#define I2SCLL 0xE001C014
|
||||
#define I2CONCLR 0xE001C018
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define S0SPCR 0xE0020000
|
||||
#define S0SPSR 0xE0020004
|
||||
#define S0SPDR 0xE0020008
|
||||
#define S0SPCCR 0xE002000C
|
||||
#define S0SPINT 0xE002001C
|
||||
|
||||
#define S1SPCR 0xE0030000
|
||||
#define S1SPSR 0xE0030004
|
||||
#define S1SPDR 0xE0030008
|
||||
#define S1SPCCR 0xE003000C
|
||||
#define S1SPINT 0xE003001C
|
||||
|
||||
/* CAN controller */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define T0IR 0xE0004000
|
||||
#define T0TCR 0xE0004004
|
||||
#define T0TC 0xE0004008
|
||||
#define T0PR 0xE000400C
|
||||
#define T0PC 0xE0004010
|
||||
#define T0MCR 0xE0004014
|
||||
#define T0MR0 0xE0004018
|
||||
#define T0MR1 0xE000401C
|
||||
#define T0MR2 0xE0004020
|
||||
#define T0MR3 0xE0004024
|
||||
#define T0CCR 0xE0004028
|
||||
#define T0CR0 0xE000402C
|
||||
#define T0CR1 0xE0004030
|
||||
#define T0CR2 0xE0004034
|
||||
#define T0CR3 0xE0004038
|
||||
#define T0EMR 0xE000403C
|
||||
|
||||
#define T1IR 0xE0008000
|
||||
#define T1TCR 0xE0008004
|
||||
#define T1TC 0xE0008008
|
||||
#define T1PR 0xE000800C
|
||||
#define T1PC 0xE0008010
|
||||
#define T1MCR 0xE0008014
|
||||
#define T1MR0 0xE0008018
|
||||
#define T1MR1 0xE000801C
|
||||
#define T1MR2 0xE0008020
|
||||
#define T1MR3 0xE0008024
|
||||
#define T1CCR 0xE0008028
|
||||
#define T1CR0 0xE000802C
|
||||
#define T1CR1 0xE0008030
|
||||
#define T1CR2 0xE0008034
|
||||
#define T1CR3 0xE0008038
|
||||
#define T1EMR 0xE000803C
|
||||
|
||||
/* PWM */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* A/D converter */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Real Time Clock */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Watchdog */
|
||||
|
||||
#define WDMOD 0xE0000000
|
||||
#define WDTC 0xE0000004
|
||||
#define WDFEED 0xE0000008
|
||||
#define WDTV 0xE000000C
|
||||
|
||||
/* EmbeddedICE LOGIC */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
#endif
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* A dummy header file for use with the LPC2292 port to keep the
|
||||
* compiler happy.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MMC_ARM_TDM_H_
|
||||
#define _MMC_ARM_TDM_H_
|
||||
#endif /* _MMC_ARM_TDM_H_ */
|
||||
Loading…
Reference in New Issue