Add support for the digsy MTC board.
This is the InterControl custom device based on the MPC5200B chip. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
This commit is contained in:
Grzegorz Bernacki
Wolfgang Denk
parent
ff7dc06736
commit
5c4fa9b474
1
MAKEALL
1
MAKEALL
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@ -47,6 +47,7 @@ LIST_5xxx=" \
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BC3450 \
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cm5200 \
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cpci5200 \
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digsy_mtc \
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EVAL5200 \
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fo300 \
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icecube_5100 \
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16
Makefile
16
Makefile
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@ -527,6 +527,22 @@ cm5200_config: unconfig
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cpci5200_config: unconfig
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@$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
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digsy_mtc_config \
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digsy_mtc_LOWBOOT_config \
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digsy_mtc_RAMBOOT_config: unconfig
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@mkdir -p $(obj)include
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@mkdir -p $(obj)board/digsy_mtc
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@ >$(obj)include/config.h
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@[ -z "$(findstring LOWBOOT_,$@)" ] || \
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{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/digsy_mtc/config.tmp ; \
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echo "... with LOWBOOT configuration" ; \
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}
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@[ -z "$(findstring RAMBOOT_,$@)" ] || \
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{ echo "TEXT_BASE = 0x00100000" >$(obj)board/digsy_mtc/config.tmp ; \
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echo "... with RAMBOOT configuration" ; \
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}
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@$(MKCONFIG) -a digsy_mtc ppc mpc5xxx digsy_mtc
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hmi1001_config: unconfig
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@$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
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@ -0,0 +1,32 @@
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#
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# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,24 @@
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#
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# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
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#
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#
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# digsyMTC board:
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#
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# Valid values for TEXT_BASE are:
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#
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# 0xFFF00000 boot high (standard configuration)
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# 0xFE000000 boot low
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# 0x00100000 boot from RAM (for testing only)
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifndef TEXT_BASE
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## Standard: boot high
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TEXT_BASE = 0xFFF00000
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## For testing: boot from RAM
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# TEXT_BASE = 0x00100000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,307 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2005-2009
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* Modified for InterControl digsyMTC MPC5200 board by
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* Frank Bodammer, GCD Hard- & Software GmbH,
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* frank.bodammer@gcd-solutions.de
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*
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* (C) Copyright 2009
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* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <net.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "eeprom.h"
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#include "is42s16800a-7t.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern int usb_cpu_init(void);
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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long control = SDRAM_CONTROL | hi_addr_bit;
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/* unlock mode register */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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/* auto refresh */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
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/* set mode register */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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/* normal operation */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
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/* setup config registers */
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out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
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(0x13 + __builtin_ffs(dramsize >> 20) - 1));
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} else {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
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/* find RAM size using SDRAM CS1 only */
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test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
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0x08000000);
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dramsize2 = test1;
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20))
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dramsize2 = 0;
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
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(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
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} else {
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
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out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
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return dramsize + dramsize2;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts ("Board: InterControl digsyMTC");
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if (s != NULL) {
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puts(", ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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int board_early_init_r(void)
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{
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/*
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* Now, when we are in RAM, enable flash write access for detection
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* process. Note that CS_BOOT cannot be cleared when executing in
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* flash.
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*/
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/* disable CS_BOOT */
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clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
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/* enable CS1 */
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setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
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/* enable CS0 */
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setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
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/* Low level USB init, required for proper kernel operation */
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usb_cpu_init();
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#endif
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return (0);
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}
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void board_get_enetaddr (uchar * enet)
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{
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ushort read = 0;
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ushort addr_of_eth_addr = 0;
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ushort len_sys = 0;
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ushort len_sys_cfg = 0;
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/* check identification word */
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eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
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if (read != EEPROM_IDENT)
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return;
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/* calculate offset of config area */
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eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
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eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
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(uchar *)&len_sys_cfg, 2);
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addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
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if (addr_of_eth_addr >= EEPROM_LEN)
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return;
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eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
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}
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int misc_init_r(void)
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{
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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board_get_enetaddr(enetaddr);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#ifdef CONFIG_CMD_IDE
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#ifdef CONFIG_IDE_RESET
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void init_ide_reset(void)
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{
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debug ("init_ide_reset\n");
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/* set gpio output value to 1 */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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/* open drain output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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/* direction output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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/* enable gpio */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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}
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void ide_set_reset(int idereset)
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{
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debug ("ide_reset(%d)\n", idereset);
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/* set gpio output value to 0 */
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clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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/* open drain output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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/* direction output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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/* enable gpio */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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udelay(10000);
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/* set gpio output value to 1 */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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/* open drain output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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/* direction output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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/* enable gpio */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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}
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#endif /* CONFIG_IDE_RESET */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#endif /* CONFIG_CMD_IDE */
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@ -0,0 +1,32 @@
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/*
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* (C) Copyright 2009 Semihalf.
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* Written by: Grzegorz Bernacki <gjb@semihalf.com>
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the anty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*
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*/
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#ifndef CMD_EEPROM_H
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#define CMD_EEPROM_H
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#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
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#define EEPROM_LEN 1024 /* eeprom length */
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#define EEPROM_IDENT 2408 /* identification word */
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#define EEPROM_ADDR_IDENT 0 /* identification word offset */
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#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
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#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
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#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */
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#endif
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@ -0,0 +1,28 @@
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/*
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* (C) Copyright 2004-2009
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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#define SDRAM_MODE 0x00CD0000
|
||||
#define SDRAM_CONTROL 0x505F0000
|
||||
#define SDRAM_CONFIG1 0xD2322900
|
||||
#define SDRAM_CONFIG2 0x8AD70000
|
||||
|
||||
|
|
@ -28,6 +28,7 @@
|
|||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <net.h>
|
||||
#include <mpc5xxx.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
|
|
@ -121,7 +122,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
|
||||
char * cpu_path = "/cpus/" OF_CPU;
|
||||
#ifdef CONFIG_MPC5xxx_FEC
|
||||
uchar *enetaddr[6];
|
||||
uchar enetaddr[6];
|
||||
char * eth_path = "/" OF_SOC "/ethernet@3000";
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,346 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2005-2007
|
||||
* Modified for InterControl digsyMTC MPC5200 board by
|
||||
* Frank Bodammer, GCD Hard- & Software GmbH,
|
||||
* frank.bodammer@gcd-solutions.de
|
||||
*
|
||||
* (C) Copyright 2009 Semihalf
|
||||
* Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software\; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation\; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY\; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program\; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
|
||||
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
|
||||
|
||||
#define BOOTFLAG_COLD 0x01
|
||||
#define BOOTFLAG_WARM 0x02
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*
|
||||
* PCI Mapping:
|
||||
* 0x40000000 - 0x4fffffff - PCI Memory
|
||||
* 0x50000000 - 0x50ffffff - PCI IO Space
|
||||
*/
|
||||
#define CONFIG_PCI 1
|
||||
#define CONFIG_PCI_PNP 1
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||
|
||||
/*
|
||||
* Partitions
|
||||
*/
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_BZIP2
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DFL
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
#if (TEXT_BASE == 0xFF000000)
|
||||
#define CONFIG_SYS_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"console=ttyPSC0\0" \
|
||||
"kernel_addr_r=400000\0" \
|
||||
"fdt_addr_r=600000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:"\
|
||||
"${netmask}:${hostname}:${netdev}:off panic=1\0" \
|
||||
"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${fdt_file};" \
|
||||
"run nfsargs addip addcons;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=protect off FFF00000 +${filesize};" \
|
||||
"erase FFF00000 +${filesize};" \
|
||||
"cp.b 200000 FFF00000 ${filesize};" \
|
||||
"protect on FFF00000 +${filesize}\0" \
|
||||
""
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_MODULE 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_FLASH_16BIT
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
|
||||
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_CPU "PowerPC,5200@0"
|
||||
#define OF_SOC "soc5200@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#if defined(CONFIG_LOWBOOT)
|
||||
#define CONFIG_ENV_ADDR 0xFF060000
|
||||
#else /* CONFIG_LOWBOOT */
|
||||
#define CONFIG_ENV_ADDR 0xFFF60000
|
||||
#endif /* CONFIG_LOWBOOT */
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xF0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#if !defined(CONFIG_SYS_LOWBOOT)
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
#else
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Use SRAM until RAM will be available
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 4096
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_PROMPT "=> "
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR " "
|
||||
|
||||
#define CONFIG_LOOPW 1
|
||||
#define CONFIG_MX_CYCLIC 1
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 32
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00010000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x019fffff
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_CS1 1
|
||||
#define CONFIG_SYS_XLB_PIPELINING 1
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#if defined(CONFIG_SYS_LOWBOOT)
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CS4_START 0x60000000
|
||||
#define CONFIG_SYS_CS4_SIZE 0x1000
|
||||
#define CONFIG_SYS_CS4_CFG 0x0008FC00
|
||||
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_CS0_CFG 0x0002DD00
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
|
||||
|
||||
#if !defined(CONFIG_SYS_LOWBOOT)
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
|
||||
#else
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000100
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_OHCI_BE_CONTROLLER
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
#define CONFIG_USB_CLOCK 0x00013333
|
||||
#define CONFIG_USB_CONFIG 0x00002000
|
||||
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
|
||||
/*
|
||||
* IDE/ATA
|
||||
*/
|
||||
#define CONFIG_IDE_RESET
|
||||
#define CONFIG_IDE_PREINIT
|
||||
|
||||
#define CONFIG_SYS_ATA_CS_ON_I2C2
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#define CONFIG_ATAPI 1
|
||||
#define CONFIG_LBA48 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue