Phytec Phycore-i.MX31 support
This patch adds support for the Phytec Phycore-i.MX31 board Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
This commit is contained in:
Sascha Hauer
Wolfgang Denk
parent
caebc95be3
commit
5ad862166a
1
MAKEALL
1
MAKEALL
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@ -508,6 +508,7 @@ LIST_ARM11=" \
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omap2420h4 \
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apollon \
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imx31_litekit \
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imx31_phycore \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -2609,6 +2609,9 @@ apollon_config : unconfig
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imx31_litekit_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
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imx31_phycore_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
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#========================================================================
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# i386
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#========================================================================
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := imx31_phycore.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1 @@
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TEXT_BASE = 0x87f00000
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@ -0,0 +1,73 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/mx31.h>
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#include <asm/arch/mx31-regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int board_init (void)
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{
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__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
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__REG(CSCR_L(0)) = 0x10000d03;
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__REG(CSCR_A(0)) = 0x00720900;
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__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
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__REG(CSCR_L(1)) = 0x444a4541;
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__REG(CSCR_A(1)) = 0x44443302;
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__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
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__REG(CSCR_L(4)) = 0x22252521;
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__REG(CSCR_A(4)) = 0x22220a00;
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
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/* setup pins for I2C2 (for EEPROM, RTC) */
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mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
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mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
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gd->bd->bi_arch_number = 447; /* board id for linux */
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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return 0;
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}
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int checkboard (void)
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{
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printf("Board: Phytec phyCore i.MX31\n");
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return 0;
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}
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@ -0,0 +1,104 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/mx31-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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REG IPU_CONF, IPU_CONF_DI_EN
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REG CCM_CCMR, 0x074B0BF5
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
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REG 0x43FAC26C, 0 /* SDCLK */
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REG 0x43FAC270, 0 /* CAS */
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REG 0x43FAC274, 0 /* RAS */
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REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */
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REG 0x43FAC284, 0 /* DQM3 */
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REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
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REG 0x43FAC28C, 0
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REG 0x43FAC290, 0
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REG 0x43FAC294, 0
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REG 0x43FAC298, 0
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REG 0x43FAC29C, 0
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REG 0x43FAC2A0, 0
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REG 0x43FAC2A4, 0
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REG 0x43FAC2A8, 0
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REG 0x43FAC2AC, 0
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REG 0x43FAC2B0, 0
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REG 0x43FAC2B4, 0
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REG 0x43FAC2B8, 0
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REG 0x43FAC2BC, 0
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REG 0x43FAC2C0, 0
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REG 0x43FAC2C4, 0
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REG 0x43FAC2C8, 0
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REG 0x43FAC2CC, 0
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REG 0x43FAC2D0, 0
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REG 0x43FAC2D4, 0
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REG 0x43FAC2D8, 0
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REG 0x43FAC2DC, 0
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REG 0xB8001010, 0x00000004
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REG 0xB8001004, 0x006ac73a
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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REG 0xB8001000, 0x82226080
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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mov pc, lr
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@ -0,0 +1,59 @@
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/*
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* January 2004 - Changed to support H4 device
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* Copyright (c) 2004 Texas Instruments
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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cpu/arm1136/start.o (.text)
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*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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.data : { *(.data) }
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. = ALIGN(4);
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.got : { *(.got) }
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = ALIGN(4);
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__bss_start = .;
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.bss : { *(.bss) }
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_end = .;
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}
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@ -0,0 +1,180 @@
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/*
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* (C) Copyright 2004
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Kshitij Gupta <kshitij@ti.com>
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*
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* Configuration settings for the 242x TI H4 board.
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_MX31 1 /* in a mx31 */
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#define CONFIG_MX31_HCLK_FREQ 26000000
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Temporarily disabled */
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#if 0
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_FIT 1
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#define CONFIG_FIT_VERBOSE 1
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#endif
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_I2C_MXC 1
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#define CFG_I2C_MX31_PORT2 1
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#define CFG_I2C_SPEED 100000
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#define CFG_I2C_SLAVE 0xfe
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#define CONFIG_MX31_UART 1
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#define CFG_MX31_UART1 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_BOOTDELAY 3
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#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.23.168
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#define CONFIG_SERVERIP 192.168.23.2
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 $(uimage); bootm\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x80000000\0" \
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"unlock=yes\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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||||
"prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \
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"prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0" \
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||||
"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
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||||
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||||
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||||
#define CONFIG_DRIVER_SMC911X 1
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#define CONFIG_DRIVER_SMC911X_BASE 0xa8000000
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|
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/*
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* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
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||||
#define CFG_PROMPT "uboot> "
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x10000
|
||||
|
||||
#define CFG_LOAD_ADDR 0 /* default load address */
|
||||
|
||||
#define CFG_HZ 32000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xa0000000
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 259 /* max number of sectors on one chip */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
|
||||
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_ENV_OFFSET 0x00 /* environment starts here */
|
||||
#define CFG_ENV_SIZE 4096
|
||||
#define CFG_I2C_EEPROM_ADDR 0x52
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
#undef CONFIG_JFFS2_CMDLINE
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue