p2020ds: add alternate boot bank support using the ngPIXIS FPGA
The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS. The ngPIXIS has one distinct new feature: the values of the on-board switches can be selectively overridden with shadow registers. This feature is used to boot from a different NOR flash bank, instead of having a register dedicated for this purpose. Because the ngPIXIS is so different from the previous PIXIS, a new file is introduced: ngpixis.c. Also update the P2020DS checkboard() function to use the new macros defined in the header file. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
Kumar Gala
parent
2feb4af001
commit
5a46960883
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@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
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COBJS-${CONFIG_FSL_VIA} += cds_via.o
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COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
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COBJS-${CONFIG_FSL_PIXIS} += pixis.o
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COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
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COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
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COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
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COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
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@ -0,0 +1,136 @@
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/**
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* Copyright 2010 Freescale Semiconductor
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* Author: Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*
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* A "switch" is black rectangular block on the motherboard. It contains
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* eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
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* shadow the actual physical switches. There is also another set of
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* registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
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* used to override the values of the bits in the physical switches.
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*
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* The following macros need to be defined:
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*
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* PIXIS_BASE - The virtual address of the base of the PIXIS register map
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*
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* PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
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* is used in the PIXIS_SW() macro to determine which offset in
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* the PIXIS register map corresponds to the physical switch that controls
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* the boot bank.
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*
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* PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
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*
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* PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
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*
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* PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
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* boot from the alternate bank.
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*/
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include "ngpixis.h"
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/*
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* Reset the board. This ignores the ENx registers.
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*/
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void pixis_reset(void)
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{
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out_8(&pixis->rst, 0);
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while (1);
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}
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/*
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* Reset the board. Like pixis_reset(), but it honors the ENx registers.
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*/
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void pixis_bank_reset(void)
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{
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out_8(&pixis->vctl, 0);
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out_8(&pixis->vctl, 1);
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while (1);
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}
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/**
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* Set the boot bank to the power-on default bank
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*/
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void clear_altbank(void)
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{
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/* Tell the ngPIXIS to use this the bits in the physical switch for the
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* boot bank value, instead of the SWx register. We need to be careful
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* only to set the bits in SWx that correspond to the boot bank.
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*/
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clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
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}
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/**
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* Set the boot bank to the alternate bank
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*/
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void set_altbank(void)
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{
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/* Program the alternate bank number into the SWx register.
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*/
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clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
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PIXIS_LBMAP_ALTBANK);
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/* Tell the ngPIXIS to use this the bits in the SWx register for the
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* boot bank value, instead of the physical switch. We need to be
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* careful only to set the bits in SWx that correspond to the boot bank.
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*/
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setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
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}
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int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned int i;
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char *p_altbank = NULL;
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char *unknown_param = NULL;
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/* No args is a simple reset request.
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*/
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if (argc <= 1)
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pixis_reset();
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for (i = 1; i < argc; i++) {
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if (strcmp(argv[i], "altbank") == 0) {
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p_altbank = argv[i];
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continue;
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}
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unknown_param = argv[i];
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}
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if (unknown_param) {
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printf("Invalid option: %s\n", unknown_param);
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return 1;
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}
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if (p_altbank)
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set_altbank();
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else
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clear_altbank();
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pixis_bank_reset();
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/* Shouldn't be reached. */
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return 0;
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}
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U_BOOT_CMD(
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pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
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"Reset the board using the FPGA sequencer",
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"- hard reset to default bank\n"
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"pixis_reset altbank - reset to alternate bank\n"
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);
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@ -0,0 +1,57 @@
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/**
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* Copyright 2010 Freescale Semiconductor
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* Author: Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/* ngPIXIS register set. Hopefully, this won't change too much over time.
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* Feel free to add board-specific #ifdefs where necessary.
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*/
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typedef struct ngpixis {
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u8 id;
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u8 arch;
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u8 scver;
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u8 csr;
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u8 rst;
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u8 res1;
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u8 aux;
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u8 spd;
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u8 brdcfg0;
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u8 dma;
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u8 addr;
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u8 res2[2];
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u8 data;
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u8 led;
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u8 res3;
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u8 vctl;
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u8 vstat;
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u8 vcfgen0;
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u8 res4;
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u8 ocmcsr;
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u8 ocmmsg;
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u8 gmdbg;
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u8 res5[2];
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u8 sclk[3];
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u8 dclk[3];
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u8 watch;
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struct {
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u8 sw;
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u8 en;
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} s[8];
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} ngpixis_t __attribute__ ((aligned(1)));
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/* Pointer to the PIXIS register set */
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#define pixis ((ngpixis_t *)PIXIS_BASE)
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/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
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#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
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/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
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#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
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@ -38,6 +38,7 @@
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#include <asm/mp.h>
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#include <netdev.h>
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#include "../common/ngpixis.h"
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#include "../common/sgmii_riser.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -46,30 +47,24 @@ phys_size_t fixed_sdram(void);
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int checkboard(void)
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{
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u8 sw7;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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u8 sw;
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puts("Board: P2020DS ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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printf("Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
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sw7 = in_8(pixis_base + PIXIS_SW(7));
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switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
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case 0:
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case 1:
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printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
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break;
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case 2:
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case 3:
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puts ("Promjet\n");
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break;
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}
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sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
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sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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/* The lower two bits are the actual vbank number */
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printf("vBank: %d\n", sw & 3);
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else
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puts("Promjet\n");
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return 0;
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}
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@ -370,30 +365,22 @@ unsigned long get_board_ddr_clk(ulong dummy)
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return gd->mem_clk;
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}
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unsigned long
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calculate_board_sys_clk(ulong dummy)
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unsigned long calculate_board_sys_clk(ulong dummy)
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{
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ulong val;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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val = ics307_clk_freq(
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in_8(pixis_base + PIXIS_VSYSCLK0),
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in_8(pixis_base + PIXIS_VSYSCLK1),
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in_8(pixis_base + PIXIS_VSYSCLK2));
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val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
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in_8(&pixis->sclk[2]));
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debug("sysclk val = %lu\n", val);
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return val;
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}
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unsigned long
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calculate_board_ddr_clk(ulong dummy)
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unsigned long calculate_board_ddr_clk(ulong dummy)
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{
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ulong val;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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val = ics307_clk_freq(
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in_8(pixis_base + PIXIS_VDDRCLK0),
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in_8(pixis_base + PIXIS_VDDRCLK1),
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in_8(pixis_base + PIXIS_VDDRCLK2));
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val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
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in_8(&pixis->dclk[2]));
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debug("ddrclk val = %lu\n", val);
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return val;
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}
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@ -402,9 +389,8 @@ unsigned long get_board_sys_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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i = in_8(pixis_base + PIXIS_SPD);
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i = in_8(&pixis->spd);
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i &= 0x07;
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switch (i) {
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@ -441,9 +427,8 @@ unsigned long get_board_ddr_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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i = in_8(pixis_base + PIXIS_SPD);
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i = in_8(&pixis->spd);
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i &= 0x38;
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i >>= 3;
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@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
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#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
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#ifdef CONFIG_FSL_NGPIXIS
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#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
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#ifdef CONFIG_PHYS_64BIT
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#define PIXIS_BASE_PHYS 0xfffdf0000ull
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@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
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#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
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#define PIXIS_ID 0x0 /* Board ID at offset 0 */
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#define PIXIS_VER 0x1 /* Board version at offset 1 */
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#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
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#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
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#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
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#define PIXIS_PWR 0x5 /* PIXIS Power status register */
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#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
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#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
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#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
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#define PIXIS_VCTL 0x10 /* VELA Control Register */
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#define PIXIS_VSTAT 0x11 /* VELA Status Register */
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#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
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#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
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#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
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#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
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#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
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#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
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#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
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#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
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#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
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#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
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#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
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#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
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#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
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#define PIXIS_VWATCH 0x24 /* Watchdog Register */
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#define PIXIS_LED 0x25 /* LED Register */
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#define PIXIS_SW(x) 0x20 + (x - 1) * 2
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#define PIXIS_EN(x) 0x21 + (x - 1) * 2
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#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
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#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
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/* old pixis referenced names */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
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#define PIXIS_VSPEED2_TSEC1SER 0x8
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#define PIXIS_VSPEED2_TSEC2SER 0x4
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#define PIXIS_VSPEED2_TSEC3SER 0x2
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#define PIXIS_VSPEED2_TSEC4SER 0x1
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#define PIXIS_VCFGEN1_TSEC1SER 0x20
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#define PIXIS_VCFGEN1_TSEC2SER 0x20
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#define PIXIS_VCFGEN1_TSEC3SER 0x20
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#define PIXIS_VCFGEN1_TSEC4SER 0x20
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#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
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| PIXIS_VSPEED2_TSEC2SER \
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| PIXIS_VSPEED2_TSEC3SER \
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| PIXIS_VSPEED2_TSEC4SER)
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#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
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| PIXIS_VCFGEN1_TSEC2SER \
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| PIXIS_VCFGEN1_TSEC3SER \
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| PIXIS_VCFGEN1_TSEC4SER)
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xf0
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#define PIXIS_LBMAP_SHIFT 4
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#define PIXIS_LBMAP_ALTBANK 0x20
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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