ppc4xx: Add static support for 44x IBM SDRAM Controller
This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Adam Graham
Stefan Roese
parent
f09f09d389
commit
59217bae40
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@ -60,6 +60,26 @@
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"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
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} while (0)
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#if defined(CONFIG_440)
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2
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* memory region. Right now the cache should still be disabled in U-Boot
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* because of the EMAC driver, that need its buffer descriptor to be located
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* in non cached memory.
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*
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* If at some time this restriction doesn't apply anymore, just define
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* CONFIG_4xx_DCACHE in the board config file and this code should setup
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* everything correctly.
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*/
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#ifdef CONFIG_4xx_DCACHE
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/* enable caching on SDRAM */
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#define MY_TLB_WORD2_I_ENABLE 0
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#else
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/* disable caching on SDRAM */
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
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#endif /* CONFIG_4xx_DCACHE */
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#endif /* CONFIG_440 */
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#if defined(CONFIG_SPD_EEPROM)
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/*-----------------------------------------------------------------------------+
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@ -130,22 +150,6 @@
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#define NUMMEMWORDS 8
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#define NUMLOOPS 64 /* memory test loops */
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
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* region. Right now the cache should still be disabled in U-Boot because of the
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* EMAC driver, that need it's buffer descriptor to be located in non cached
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* memory.
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*
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* If at some time this restriction doesn't apply anymore, just define
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* CONFIG_4xx_DCACHE in the board config file and this code should setup
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* everything correctly.
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*/
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#ifdef CONFIG_4xx_DCACHE
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#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
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#else
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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#endif
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/*
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* Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
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* To support such configurations, we "only" map the first 2GB via the TLB's. We
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@ -2958,9 +2962,10 @@ static void test(void)
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/*-----------------------------------------------------------------------------
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* Function: initdram
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* Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
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* banks. The configuration is performed using static, compile-
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* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
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* The configuration is performed using static, compile-
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* time parameters.
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* Configures the PPC405EX(r) and PPC460EX/GT
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*---------------------------------------------------------------------------*/
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phys_size_t initdram(int board_type)
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{
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@ -2976,6 +2981,18 @@ phys_size_t initdram(int board_type)
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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unsigned long val;
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#if defined(CONFIG_440)
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mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
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mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
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mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
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mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
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mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
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mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
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mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
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mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
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mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
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#endif
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/* Set Memory Bank Configuration Registers */
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mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
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@ -3069,6 +3086,14 @@ phys_size_t initdram(int board_type)
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mfsdram(SDRAM_MCOPT2, val);
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mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
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#if defined(CONFIG_440)
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/*
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* Program TLB entries with caches enabled, for best performace
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* while auto-calibrating and ECC generation
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*/
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program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
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#endif
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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/*------------------------------------------------------------------
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@ -3082,6 +3107,16 @@ phys_size_t initdram(int board_type)
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ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
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#endif /* defined(CONFIG_DDR_ECC) */
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#if defined(CONFIG_440)
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/*
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* Now after initialization (auto-calibration and ECC generation)
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* remove the TLB entries with caches enabled and program again with
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* desired cache functionality
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*/
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remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
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program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
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#endif
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ppc4xx_ibm_ddr2_register_dump();
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
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