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Update 86xx address map and LAWBARs.

This commit is contained in:
Jon Loeliger 2006-05-19 13:22:44 -05:00
parent cccce5d058
commit 586d1d5abd
3 changed files with 54 additions and 27 deletions
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25
board/mpc8641hpcn/init.S
View File

@ -36,11 +36,10 @@
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
* 0xf810_0000 0xf81f_ffff PIXIS 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
@ -76,9 +75,16 @@
/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */
#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR8 0
#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
#endif
.section .bootpg, "ax"
.globl law_entry
@ -151,5 +157,14 @@ law_entry:
ori r6,r6,LAWAR7@l
stwu r6, 0x20(r5)
/* LAWBAR8, LAWAR8 */
lis r6,LAWBAR8@h
ori r6,r6,LAWBAR8@l
stwu r6, 0x20(r4)
lis r6,LAWAR8@h
ori r6,r6,LAWAR8@l
stwu r6, 0x20(r5)
blr

4
include/asm-ppc/immap_86xx.h
View File

@ -52,7 +52,7 @@ typedef struct ccsr_local_mcm {
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
char res20[16];
char res20[20];
uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
char res21[4];
uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
@ -60,7 +60,7 @@ typedef struct ccsr_local_mcm {
uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
char res23[4];
uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
char res24[720];
char res24[716];
uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
char res25[4];
uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */

52
include/configs/MPC8641HPCN.h
View File

@ -136,15 +136,16 @@
/*
* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
* We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
* In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
* There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
* map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
* However, when u-boot comes up, the flash_init needs hard start addresses
* to build its info table. For user convenience, we have the flash addresses
* as fe800000 and ff800000. That way, when we do flash operations, u-boot
* knows where the flash is and the user can download u-boot code from promjet to
* fef00000 <- more intuitive than fe700000. Note that, on switching the boot
* location, fef00000 becomes fff00000.
* to build its info table. For user convenience, the flash addresses is
* fe800000 and ff800000. That way, u-boot knows where the flash is
* and the user can download u-boot code from promjet to fef00000, a
* more intuitive location than fe700000.
*
* Note that, on switching the boot location, fef00000 becomes fff00000.
*/
#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
#define CFG_FLASH_BASE2 0xff800000
@ -257,14 +258,18 @@
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
/* I2C */
/*
* I2C
*/
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
/* RapidIO MMU */
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
@ -347,19 +352,21 @@
#endif /* CONFIG_TSEC_ENET */
/* BAT0 2G Cacheable, non-guarded
/*
* BAT0 2G Cacheable, non-guarded
* 0x0000_0000 2G DDR
*/
#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP )
#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP )
#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
#define CFG_IBAT0U CFG_DBAT0U
/* BAT1 1G Cache-inhibited, guarded
/*
* BAT1 1G Cache-inhibited, guarded
* 0x8000_0000 512M PCI-Express 1 Memory
* 0xa000_0000 512M PCI-Express 2 Memory
** SS - Changed it for operating from 0xd0000000
* Changed it for operating from 0xd0000000
*/
#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@ -367,7 +374,8 @@
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U CFG_DBAT1U
/* BAT2 512M Cache-inhibited, guarded
/*
* BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory
*/
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
@ -376,7 +384,8 @@
#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
/* BAT3 4M Cache-inhibited, guarded
/*
* BAT3 4M Cache-inhibited, guarded
* 0xf800_0000 4M CCSR
*/
#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
@ -385,10 +394,11 @@
#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U CFG_DBAT3U
/* BAT4 32M Cache-inhibited, guarded
/*
* BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 16M PCI-Express 1 I/O
* 0xe300_0000 16M PCI-Express 2 I/0
** SS - Note that this is at 0xe0000000
* Note that this is at 0xe0000000
*/
#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
@ -396,7 +406,8 @@
#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT4U CFG_DBAT4U
/* BAT5 128K Cacheable, non-guarded
/*
* BAT5 128K Cacheable, non-guarded
* 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
*/
#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
@ -404,7 +415,8 @@
#define CFG_IBAT5L CFG_DBAT5L
#define CFG_IBAT5U CFG_DBAT5U
/* BAT6 32M Cache-inhibited, guarded
/*
* BAT6 32M Cache-inhibited, guarded
* 0xfe00_0000 32M FLASH
*/
#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \
@ -427,7 +439,7 @@
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */