Davinci MMCSD Support
Added support for MMC/SD cards for Davinci. This feature is enabled by CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC options. This is tested on DM355 and DM365 EVMs with both the available mmc controllers. Signed-off-by: Alagu Sankar <alagusankar@embwise.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sandeep Paulraj
Albert Aribaud
parent
36b4e2dddd
commit
57418d2139
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@ -0,0 +1,175 @@
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/*
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* Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
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*
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* Copyright (C) 2010 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SDMMC_DEFS_H_
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#define _SDMMC_DEFS_H_
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#include <asm/arch/hardware.h>
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/* MMC Control Reg fields */
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#define MMCCTL_DATRST (1 << 0)
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#define MMCCTL_CMDRST (1 << 1)
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#define MMCCTL_WIDTH_4_BIT (1 << 2)
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#define MMCCTL_DATEG_DISABLED (0 << 6)
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#define MMCCTL_DATEG_RISING (1 << 6)
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#define MMCCTL_DATEG_FALLING (2 << 6)
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#define MMCCTL_DATEG_BOTH (3 << 6)
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#define MMCCTL_PERMDR_LE (0 << 9)
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#define MMCCTL_PERMDR_BE (1 << 9)
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#define MMCCTL_PERMDX_LE (0 << 10)
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#define MMCCTL_PERMDX_BE (1 << 10)
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/* MMC Clock Control Reg fields */
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#define MMCCLK_CLKEN (1 << 8)
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#define MMCCLK_CLKRT_MASK (0xFF << 0)
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/* MMC Status Reg0 fields */
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#define MMCST0_DATDNE (1 << 0)
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#define MMCST0_BSYDNE (1 << 1)
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#define MMCST0_RSPDNE (1 << 2)
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#define MMCST0_TOUTRD (1 << 3)
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#define MMCST0_TOUTRS (1 << 4)
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#define MMCST0_CRCWR (1 << 5)
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#define MMCST0_CRCRD (1 << 6)
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#define MMCST0_CRCRS (1 << 7)
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#define MMCST0_DXRDY (1 << 9)
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#define MMCST0_DRRDY (1 << 10)
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#define MMCST0_DATED (1 << 11)
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#define MMCST0_TRNDNE (1 << 12)
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#define MMCST0_ERR_MASK (0x00F8)
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/* MMC Status Reg1 fields */
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#define MMCST1_BUSY (1 << 0)
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#define MMCST1_CLKSTP (1 << 1)
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#define MMCST1_DXEMP (1 << 2)
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#define MMCST1_DRFUL (1 << 3)
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#define MMCST1_DAT3ST (1 << 4)
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#define MMCST1_FIFOEMP (1 << 5)
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#define MMCST1_FIFOFUL (1 << 6)
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/* MMC INT Mask Reg fields */
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#define MMCIM_EDATDNE (1 << 0)
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#define MMCIM_EBSYDNE (1 << 1)
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#define MMCIM_ERSPDNE (1 << 2)
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#define MMCIM_ETOUTRD (1 << 3)
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#define MMCIM_ETOUTRS (1 << 4)
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#define MMCIM_ECRCWR (1 << 5)
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#define MMCIM_ECRCRD (1 << 6)
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#define MMCIM_ECRCRS (1 << 7)
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#define MMCIM_EDXRDY (1 << 9)
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#define MMCIM_EDRRDY (1 << 10)
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#define MMCIM_EDATED (1 << 11)
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#define MMCIM_ETRNDNE (1 << 12)
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#define MMCIM_MASKALL (0xFFFFFFFF)
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/* MMC Resp Tout Reg fields */
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#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
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#define MMCTOR_TOD_20_16_SHIFT (8)
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/* MMC Data Read Tout Reg fields */
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#define MMCTOD_TOD_0_15_MASK (0xFFFF)
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/* MMC Block len Reg fields */
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#define MMCBLEN_BLEN_MASK (0xFFF)
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/* MMC Num Blocks Reg fields */
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#define MMCNBLK_NBLK_MASK (0xFFFF)
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#define MMCNBLK_NBLK_MAX (0xFFFF)
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/* MMC Num Blocks Counter Reg fields */
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#define MMCNBLC_NBLC_MASK (0xFFFF)
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/* MMC Cmd Reg fields */
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#define MMCCMD_CMD_MASK (0x3F)
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#define MMCCMD_PPLEN (1 << 7)
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#define MMCCMD_BSYEXP (1 << 8)
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#define MMCCMD_RSPFMT_NONE (0 << 9)
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#define MMCCMD_RSPFMT_R1567 (1 << 9)
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#define MMCCMD_RSPFMT_R2 (2 << 9)
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#define MMCCMD_RSPFMT_R3 (3 << 9)
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#define MMCCMD_DTRW (1 << 11)
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#define MMCCMD_STRMTP (1 << 12)
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#define MMCCMD_WDATX (1 << 13)
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#define MMCCMD_INITCK (1 << 14)
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#define MMCCMD_DCLR (1 << 15)
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#define MMCCMD_DMATRIG (1 << 16)
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/* FIFO control Reg fields */
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#define MMCFIFOCTL_FIFORST (1 << 0)
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#define MMCFIFOCTL_FIFODIR (1 << 1)
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#define MMCFIFOCTL_FIFOLEV (1 << 2)
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#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
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#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
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#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
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#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
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/* Davinci MMC Register definitions */
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struct davinci_mmc_regs {
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dv_reg mmcctl;
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dv_reg mmcclk;
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dv_reg mmcst0;
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dv_reg mmcst1;
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dv_reg mmcim;
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dv_reg mmctor;
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dv_reg mmctod;
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dv_reg mmcblen;
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dv_reg mmcnblk;
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dv_reg mmcnblc;
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dv_reg mmcdrr;
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dv_reg mmcdxr;
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dv_reg mmccmd;
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dv_reg mmcarghl;
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dv_reg mmcrsp01;
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dv_reg mmcrsp23;
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dv_reg mmcrsp45;
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dv_reg mmcrsp67;
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dv_reg mmcdrsp;
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dv_reg mmcetok;
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dv_reg mmccidx;
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dv_reg mmcckc;
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dv_reg mmctorc;
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dv_reg mmctodc;
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dv_reg mmcblnc;
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dv_reg sdioctl;
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dv_reg sdiost0;
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dv_reg sdioien;
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dv_reg sdioist;
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dv_reg mmcfifoctl;
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};
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/* Davinci MMC board definitions */
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struct davinci_mmc {
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struct davinci_mmc_regs *reg_base; /* Register base address */
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uint input_clk; /* Input clock to MMC controller */
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uint host_caps; /* Host capabilities */
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uint voltages; /* Host supported voltages */
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uint version; /* MMC Controller version */
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};
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enum {
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MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
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MMC_CTLR_VERSION_2, /* DA830 */
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};
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int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
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#endif /* _SDMMC_DEFS_H */
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@ -27,6 +27,7 @@ LIB := $(obj)libmmc.o
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COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
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COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
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COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
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COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
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COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
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COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
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@ -0,0 +1,404 @@
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/*
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* Davinci MMC Controller Driver
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*
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* Copyright (C) 2010 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <mmc.h>
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#include <part.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/sdmmc_defs.h>
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#define DAVINCI_MAX_BLOCKS (32)
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#define WATCHDOG_COUNT (100000)
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#define get_val(addr) REG(addr)
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#define set_val(addr, val) REG(addr) = (val)
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#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
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#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
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/* Set davinci clock prescalar value based on the required clock in HZ */
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static void dmmc_set_clock(struct mmc *mmc, uint clock)
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{
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struct davinci_mmc *host = mmc->priv;
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struct davinci_mmc_regs *regs = host->reg_base;
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uint clkrt, sysclk2, act_clock;
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if (clock < mmc->f_min)
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clock = mmc->f_min;
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if (clock > mmc->f_max)
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clock = mmc->f_max;
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set_val(®s->mmcclk, 0);
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sysclk2 = host->input_clk;
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clkrt = (sysclk2 / (2 * clock)) - 1;
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/* Calculate the actual clock for the divider used */
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act_clock = (sysclk2 / (2 * (clkrt + 1)));
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/* Adjust divider if actual clock exceeds the required clock */
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if (act_clock > clock)
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clkrt++;
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/* check clock divider boundary and correct it */
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if (clkrt > 0xFF)
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clkrt = 0xFF;
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set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
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}
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/* Status bit wait loop for MMCST1 */
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static int
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dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
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{
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uint mmcstatus1, wdog = WATCHDOG_COUNT;
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mmcstatus1 = get_val(®s->mmcst1);
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while (--wdog && ((get_val(®s->mmcst1) & status) != status))
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udelay(10);
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if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
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udelay(100);
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if (wdog == 0)
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return COMM_ERR;
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return 0;
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}
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/* Busy bit wait loop for MMCST1 */
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static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
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{
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uint mmcstatus1, wdog = WATCHDOG_COUNT;
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mmcstatus1 = get_val(®s->mmcst1);
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while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
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udelay(10);
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if (wdog == 0)
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return COMM_ERR;
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return 0;
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}
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/* Status bit wait loop for MMCST0 - Checks for error bits as well */
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static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
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uint *cur_st, uint st_ready, uint st_error)
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{
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uint wdog = WATCHDOG_COUNT;
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uint mmcstatus = *cur_st;
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while (wdog--) {
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if (mmcstatus & st_ready) {
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*cur_st = mmcstatus;
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mmcstatus = get_val(®s->mmcst1);
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return 0;
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} else if (mmcstatus & st_error) {
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if (mmcstatus & MMCST0_TOUTRS)
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return TIMEOUT;
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printf("[ ST0 ERROR %x]\n", mmcstatus);
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/*
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* Ignore CRC errors as some MMC cards fail to
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* initialize on DM365-EVM on the SD1 slot
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*/
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if (mmcstatus & MMCST0_CRCRS)
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return 0;
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return COMM_ERR;
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}
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udelay(10);
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mmcstatus = get_val(®s->mmcst0);
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}
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printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
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get_val(®s->mmcst1));
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return COMM_ERR;
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}
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/*
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* Sends a command out on the bus. Takes the mmc pointer,
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* a command pointer, and an optional data pointer.
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*/
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static int
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dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct davinci_mmc *host = mmc->priv;
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volatile struct davinci_mmc_regs *regs = host->reg_base;
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uint mmcstatus, status_rdy, status_err;
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uint i, cmddata, bytes_left = 0;
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int fifo_words, fifo_bytes, err;
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char *data_buf = NULL;
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/* Clear status registers */
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mmcstatus = get_val(®s->mmcst0);
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fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
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fifo_bytes = fifo_words << 2;
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/* Wait for any previous busy signal to be cleared */
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dmmc_busy_wait(regs);
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cmddata = cmd->cmdidx;
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cmddata |= MMCCMD_PPLEN;
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/* Send init clock for CMD0 */
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if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
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cmddata |= MMCCMD_INITCK;
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switch (cmd->resp_type) {
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case MMC_RSP_R1b:
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cmddata |= MMCCMD_BSYEXP;
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/* Fall-through */
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case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
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cmddata |= MMCCMD_RSPFMT_R1567;
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break;
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case MMC_RSP_R2:
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cmddata |= MMCCMD_RSPFMT_R2;
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break;
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case MMC_RSP_R3: /* R3, R4 */
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cmddata |= MMCCMD_RSPFMT_R3;
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break;
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}
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set_val(®s->mmcim, 0);
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if (data) {
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/* clear previous data transfer if any and set new one */
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bytes_left = (data->blocksize * data->blocks);
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/* Reset FIFO - Always use 32 byte fifo threshold */
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set_val(®s->mmcfifoctl,
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(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
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if (host->version == MMC_CTLR_VERSION_2)
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cmddata |= MMCCMD_DMATRIG;
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cmddata |= MMCCMD_WDATX;
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if (data->flags == MMC_DATA_READ) {
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set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
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} else if (data->flags == MMC_DATA_WRITE) {
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set_val(®s->mmcfifoctl,
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(MMCFIFOCTL_FIFOLEV |
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MMCFIFOCTL_FIFODIR));
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cmddata |= MMCCMD_DTRW;
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}
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set_val(®s->mmctod, 0xFFFF);
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set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
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set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
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if (data->flags == MMC_DATA_WRITE) {
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uint val;
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data_buf = (char *)data->src;
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/* For write, fill FIFO with data before issue of CMD */
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for (i = 0; (i < fifo_words) && bytes_left; i++) {
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memcpy((char *)&val, data_buf, 4);
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set_val(®s->mmcdxr, val);
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data_buf += 4;
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bytes_left -= 4;
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}
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}
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} else {
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set_val(®s->mmcblen, 0);
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set_val(®s->mmcnblk, 0);
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}
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set_val(®s->mmctor, 0x1FFF);
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/* Send the command */
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set_val(®s->mmcarghl, cmd->cmdarg);
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set_val(®s->mmccmd, cmddata);
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status_rdy = MMCST0_RSPDNE;
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status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
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MMCST0_CRCWR | MMCST0_CRCRD);
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if (cmd->resp_type & MMC_RSP_CRC)
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status_err |= MMCST0_CRCRS;
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mmcstatus = get_val(®s->mmcst0);
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err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
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if (err)
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return err;
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/* For R1b wait for busy done */
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if (cmd->resp_type == MMC_RSP_R1b)
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dmmc_busy_wait(regs);
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/* Collect response from controller for specific commands */
|
||||
if (mmcstatus & MMCST0_RSPDNE) {
|
||||
/* Copy the response to the response buffer */
|
||||
if (cmd->resp_type & MMC_RSP_136) {
|
||||
cmd->response[0] = get_val(®s->mmcrsp67);
|
||||
cmd->response[1] = get_val(®s->mmcrsp45);
|
||||
cmd->response[2] = get_val(®s->mmcrsp23);
|
||||
cmd->response[3] = get_val(®s->mmcrsp01);
|
||||
} else if (cmd->resp_type & MMC_RSP_PRESENT) {
|
||||
cmd->response[0] = get_val(®s->mmcrsp67);
|
||||
}
|
||||
}
|
||||
|
||||
if (data == NULL)
|
||||
return 0;
|
||||
|
||||
if (data->flags == MMC_DATA_READ) {
|
||||
/* check for DATDNE along with DRRDY as the controller might
|
||||
* set the DATDNE without DRRDY for smaller transfers with
|
||||
* less than FIFO threshold bytes
|
||||
*/
|
||||
status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
|
||||
status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
|
||||
data_buf = data->dest;
|
||||
} else {
|
||||
status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
|
||||
status_err = MMCST0_CRCWR;
|
||||
}
|
||||
|
||||
/* Wait until all of the blocks are transferred */
|
||||
while (bytes_left) {
|
||||
err = dmmc_check_status(regs, &mmcstatus, status_rdy,
|
||||
status_err);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (data->flags == MMC_DATA_READ) {
|
||||
/*
|
||||
* MMC controller sets the Data receive ready bit
|
||||
* (DRRDY) in MMCST0 even before the entire FIFO is
|
||||
* full. This results in erratic behavior if we start
|
||||
* reading the FIFO soon after DRRDY. Wait for the
|
||||
* FIFO full bit in MMCST1 for proper FIFO clearing.
|
||||
*/
|
||||
if (bytes_left > fifo_bytes)
|
||||
dmmc_wait_fifo_status(regs, 0x4a);
|
||||
else if (bytes_left == fifo_bytes)
|
||||
dmmc_wait_fifo_status(regs, 0x40);
|
||||
|
||||
for (i = 0; bytes_left && (i < fifo_words); i++) {
|
||||
cmddata = get_val(®s->mmcdrr);
|
||||
memcpy(data_buf, (char *)&cmddata, 4);
|
||||
data_buf += 4;
|
||||
bytes_left -= 4;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* MMC controller sets the Data transmit ready bit
|
||||
* (DXRDY) in MMCST0 even before the entire FIFO is
|
||||
* empty. This results in erratic behavior if we start
|
||||
* writing the FIFO soon after DXRDY. Wait for the
|
||||
* FIFO empty bit in MMCST1 for proper FIFO clearing.
|
||||
*/
|
||||
dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
|
||||
for (i = 0; bytes_left && (i < fifo_words); i++) {
|
||||
memcpy((char *)&cmddata, data_buf, 4);
|
||||
set_val(®s->mmcdxr, cmddata);
|
||||
data_buf += 4;
|
||||
bytes_left -= 4;
|
||||
}
|
||||
dmmc_busy_wait(regs);
|
||||
}
|
||||
}
|
||||
|
||||
err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Initialize Davinci MMC controller */
|
||||
static int dmmc_init(struct mmc *mmc)
|
||||
{
|
||||
struct davinci_mmc *host = mmc->priv;
|
||||
struct davinci_mmc_regs *regs = host->reg_base;
|
||||
|
||||
/* Clear status registers explicitly - soft reset doesn't clear it
|
||||
* If Uboot is invoked from UBL with SDMMC Support, the status
|
||||
* registers can have uncleared bits
|
||||
*/
|
||||
get_val(®s->mmcst0);
|
||||
get_val(®s->mmcst1);
|
||||
|
||||
/* Hold software reset */
|
||||
set_bit(®s->mmcctl, MMCCTL_DATRST);
|
||||
set_bit(®s->mmcctl, MMCCTL_CMDRST);
|
||||
udelay(10);
|
||||
|
||||
set_val(®s->mmcclk, 0x0);
|
||||
set_val(®s->mmctor, 0x1FFF);
|
||||
set_val(®s->mmctod, 0xFFFF);
|
||||
|
||||
/* Clear software reset */
|
||||
clear_bit(®s->mmcctl, MMCCTL_DATRST);
|
||||
clear_bit(®s->mmcctl, MMCCTL_CMDRST);
|
||||
|
||||
udelay(10);
|
||||
|
||||
/* Reset FIFO - Always use the maximum fifo threshold */
|
||||
set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
|
||||
set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set buswidth or clock as indicated by the GENERIC_MMC framework */
|
||||
static void dmmc_set_ios(struct mmc *mmc)
|
||||
{
|
||||
struct davinci_mmc *host = mmc->priv;
|
||||
struct davinci_mmc_regs *regs = host->reg_base;
|
||||
|
||||
/* Set the bus width */
|
||||
if (mmc->bus_width == 4)
|
||||
set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
|
||||
else
|
||||
clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
|
||||
|
||||
/* Set clock speed */
|
||||
if (mmc->clock)
|
||||
dmmc_set_clock(mmc, mmc->clock);
|
||||
}
|
||||
|
||||
/* Called from board_mmc_init during startup. Can be called multiple times
|
||||
* depending on the number of slots available on board and controller
|
||||
*/
|
||||
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
|
||||
mmc = malloc(sizeof(struct mmc));
|
||||
memset(mmc, 0, sizeof(struct mmc));
|
||||
|
||||
sprintf(mmc->name, "davinci");
|
||||
mmc->priv = host;
|
||||
mmc->send_cmd = dmmc_send_cmd;
|
||||
mmc->set_ios = dmmc_set_ios;
|
||||
mmc->init = dmmc_init;
|
||||
|
||||
mmc->f_min = 200000;
|
||||
mmc->f_max = 25000000;
|
||||
mmc->voltages = host->voltages;
|
||||
mmc->host_caps = host->host_caps;
|
||||
|
||||
#ifdef CONFIG_MMC_MBLOCK
|
||||
mmc->b_max = DAVINCI_MAX_BLOCKS;
|
||||
#endif
|
||||
mmc_register(mmc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -274,6 +274,9 @@ struct mmc {
|
|||
struct mmc_cmd *cmd, struct mmc_data *data);
|
||||
void (*set_ios)(struct mmc *mmc);
|
||||
int (*init)(struct mmc *mmc);
|
||||
#ifdef CONFIG_MMC_MBLOCK
|
||||
uint b_max;
|
||||
#endif
|
||||
};
|
||||
|
||||
int mmc_register(struct mmc *mmc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue