Add support for Prodrive P3P440 board:
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c - CFG_FLASH_QUIET_TEST added to use the common CFI driver for bank autodetection Patch by Stefan Roese, 22 Nov 2005
This commit is contained in:
Stefan Roese
parent
fe126d8b34
commit
5568e613ee
|
|
@ -2,6 +2,12 @@
|
|||
Changes for U-Boot 1.1.4:
|
||||
======================================================================
|
||||
|
||||
* Add support for Prodrive P3P440 board:
|
||||
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
|
||||
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
|
||||
for bank autodetection
|
||||
Patch by Stefan Roese, 22 Nov 2005
|
||||
|
||||
* Change all '$(...)' variable references into '${...}'
|
||||
which makes the environment compatible with the hush shell.
|
||||
WARNING: Support for the old '$(...)' syntax will be
|
||||
|
|
|
|||
8
MAKEALL
8
MAKEALL
|
|
@ -70,10 +70,10 @@ LIST_4xx=" \
|
|||
HH405 HUB405 JSE KAREF \
|
||||
METROBOX MIP405 MIP405T ML2 \
|
||||
ml300 ocotea OCRTC ORSG \
|
||||
PCI405 PIP405 PLU405 PMC405 \
|
||||
PPChameleonEVB sbc405 VOH405 VOM405 \
|
||||
W7OLMC W7OLMG walnut WUH405 \
|
||||
XPEDITE1K yellowstone yosemite \
|
||||
p3p440 PCI405 PIP405 PLU405 \
|
||||
PMC405 PPChameleonEVB sbc405 VOH405 \
|
||||
VOM405 W7OLMC W7OLMG walnut \
|
||||
WUH405 XPEDITE1K yellowstone yosemite \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
|
|||
3
Makefile
3
Makefile
|
|
@ -839,6 +839,9 @@ OCRTC_config \
|
|||
ORSG_config: unconfig
|
||||
@./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
|
||||
|
||||
p3p440_config: unconfig
|
||||
@./mkconfig $(@:_config=) ppc ppc4xx p3p440 prodrive
|
||||
|
||||
PCI405_config: unconfig
|
||||
@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
|
||||
|
||||
|
|
|
|||
6
README
6
README
|
|
@ -1766,6 +1766,12 @@ Configuration Settings:
|
|||
This option also enables the building of the cfi_flash driver
|
||||
in the drivers directory
|
||||
|
||||
- CFG_FLASH_QUIET_TEST
|
||||
If this option is defined, the common CFI flash doesn't
|
||||
print it's warning upon not recognized FLASH banks. This
|
||||
is useful, if some of the configured banks are only
|
||||
optionally available.
|
||||
|
||||
- CFG_RX_ETH_BUFFER:
|
||||
Defines the number of ethernet receive buffers. On some
|
||||
ethernet controllers it is recommended to set this value
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o
|
||||
SOBJS = init.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# esd ADCIOP boards
|
||||
#
|
||||
|
||||
#TEXT_BASE = 0xFFFE0000
|
||||
|
||||
ifeq ($(ramsym),1)
|
||||
TEXT_BASE = 0x07FD0000
|
||||
else
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbtab_end
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
|
||||
#include "p3p440.h"
|
||||
|
||||
void set_led(int color)
|
||||
{
|
||||
switch (color) {
|
||||
case LED_OFF:
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
|
||||
break;
|
||||
|
||||
case LED_GREEN:
|
||||
out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
|
||||
break;
|
||||
|
||||
case LED_RED:
|
||||
out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
|
||||
break;
|
||||
|
||||
case LED_ORANGE:
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int is_monarch(void)
|
||||
{
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY);
|
||||
udelay(1000);
|
||||
|
||||
if (in32(GPIO0_IR) & CFG_MONARCH_IO)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void wait_for_pci_ready(void)
|
||||
{
|
||||
/*
|
||||
* Configure EREADY_IO as input
|
||||
*/
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
|
||||
udelay(1000);
|
||||
|
||||
for (;;) {
|
||||
if (in32(GPIO0_IR) & CFG_EREADY_IO)
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
uint reg;
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
reg = mfdcr(ebccfgd);
|
||||
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup pin multiplexing (GPIO/IRQ...)
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(cpc0_gpio, 0x03F01F80);
|
||||
|
||||
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
|
||||
out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
|
||||
out32(GPIO0_OR, CFG_GPIO_RDY);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
|
||||
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
|
||||
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
|
||||
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
|
||||
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
|
||||
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
char *s = getenv("serial#");
|
||||
char buf[32];
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
|
||||
printf("Board: P3P440");
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
|
||||
if (is_monarch()) {
|
||||
puts(", Monarch");
|
||||
} else {
|
||||
puts(", None-Monarch");
|
||||
}
|
||||
|
||||
putc('\n');
|
||||
|
||||
printf(" at %s MHz (VCO=%lu, PLB=%lu, OPB=%lu, EBC=%lu MHz)\n",
|
||||
strmhz(buf, sysinfo.freqProcessor),
|
||||
sysinfo.freqVCOMhz / 1000000,
|
||||
sysinfo.freqPLB / 1000000,
|
||||
sysinfo.freqOPB / 1000000,
|
||||
sysinfo.freqEPB / 1000000);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Adjust flash start and offset to detected values
|
||||
*/
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
/*
|
||||
* Check if only one FLASH bank is available
|
||||
*/
|
||||
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
|
||||
mtebc(pb1cr, 0); /* disable cs */
|
||||
mtebc(pb1ap, 0);
|
||||
mtebc(pb2cr, 0); /* disable cs */
|
||||
mtebc(pb2ap, 0);
|
||||
mtebc(pb3cr, 0); /* disable cs */
|
||||
mtebc(pb3ap, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long strap;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* The P3P440 board is always configured as the host & requires the
|
||||
* PCI arbiter to be disabled because it's an PMC module.
|
||||
*--------------------------------------------------------------------------*/
|
||||
strap = mfdcr(cpc0_strp1);
|
||||
if (strap & 0x00100000) {
|
||||
printf("PCI: CPC0_STRP1[PAE] set.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r(PCIX0_PIM0SA, 0); /* disable */
|
||||
out32r(PCIX0_PIM1SA, 0); /* disable */
|
||||
out32r(PCIX0_PIM2SA, 0); /* disable */
|
||||
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
|
||||
* options to not support sizes such as 128/256 MB.
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
|
||||
out32r(PCIX0_PIM0LAH, 0);
|
||||
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
|
||||
|
||||
out32r(PCIX0_BAR0, 0);
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id
|
||||
*--------------------------------------------------------------------------*/
|
||||
out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
|
||||
out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
|
||||
|
||||
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
if (is_monarch()) {
|
||||
wait_for_pci_ready();
|
||||
return 1; /* return 1 for host controller */
|
||||
} else {
|
||||
return 0; /* return 0 for adapter controller */
|
||||
}
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __P3P440_H__
|
||||
#define __P3P440_H__
|
||||
|
||||
#define CFG_GPIO_RDY (0x80000000 >> 11)
|
||||
#define CFG_MONARCH_IO (0x80000000 >> 18)
|
||||
#define CFG_EREADY_IO (0x80000000 >> 20)
|
||||
#define CFG_LED_GREEN (0x80000000 >> 21)
|
||||
#define CFG_LED_RED (0x80000000 >> 22)
|
||||
|
||||
#define LED_OFF 1
|
||||
#define LED_GREEN 2
|
||||
#define LED_RED 3
|
||||
#define LED_ORANGE 4
|
||||
|
||||
long int fixed_sdram(void);
|
||||
|
||||
#endif /* __P3P440_H__ */
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/prodrive/p3p440/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -431,20 +431,24 @@ static struct pci_controller ppc440_hose = {0};
|
|||
void pci_440_init (struct pci_controller *hose)
|
||||
{
|
||||
int reg_num = 0;
|
||||
unsigned long strap;
|
||||
|
||||
#ifndef CONFIG_DISABLE_PISE_TEST
|
||||
/*--------------------------------------------------------------------------+
|
||||
* The PCI initialization sequence enable bit must be set ... if not abort
|
||||
* pci setup since updating the bit requires chip reset.
|
||||
*--------------------------------------------------------------------------*/
|
||||
#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#if defined(CONFIG_440GX)
|
||||
unsigned long strap;
|
||||
|
||||
mfsdr(sdr_sdstp1,strap);
|
||||
if ( (strap & 0x00010000) == 0 ){
|
||||
printf("PCI: SDR0_STRP1[PISE] not set.\n");
|
||||
printf("PCI: Configuration aborted.\n");
|
||||
return;
|
||||
}
|
||||
#else
|
||||
#elif defined(CONFIG_440GP)
|
||||
unsigned long strap;
|
||||
|
||||
strap = mfdcr(cpc0_strp1);
|
||||
if( (strap & 0x00040000) == 0 ){
|
||||
printf("PCI: CPC0_STRP1[PISE] not set.\n");
|
||||
|
|
@ -452,6 +456,8 @@ void pci_440_init (struct pci_controller *hose)
|
|||
return;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_DISABLE_PISE_TEST */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* PCI controller init
|
||||
*--------------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2002-2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
|
|
@ -39,6 +42,7 @@ struct sdram_conf_s {
|
|||
|
||||
typedef struct sdram_conf_s sdram_conf_t;
|
||||
|
||||
#ifndef CFG_SDRAM_TABLE
|
||||
sdram_conf_t mb0cf[] = {
|
||||
{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
|
||||
{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
|
||||
|
|
@ -46,9 +50,18 @@ sdram_conf_t mb0cf[] = {
|
|||
{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
|
||||
{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
|
||||
};
|
||||
#else
|
||||
sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
|
||||
#endif
|
||||
|
||||
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
|
||||
|
||||
|
||||
#ifndef CONFIG_440
|
||||
|
||||
/*
|
||||
* Autodetect onboard SDRAM on 405 platforms
|
||||
*/
|
||||
void sdram_init(void)
|
||||
{
|
||||
ulong sdtr1;
|
||||
|
|
@ -105,4 +118,61 @@ void sdram_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
#else /* CONFIG_440 */
|
||||
|
||||
/*
|
||||
* Autodetect onboard DDR SDRAM on 440 platforms
|
||||
*
|
||||
* NOTE: Some of the hardcoded values are hardware dependant,
|
||||
* so this should be extended for other future boards
|
||||
* using this routine!
|
||||
*/
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<N_MB0CF; i++) {
|
||||
/*
|
||||
* Disable memory controller.
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x00000000);
|
||||
|
||||
/*
|
||||
* Setup some default
|
||||
*/
|
||||
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
|
||||
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
|
||||
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
|
||||
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram(mem_b0cr, mb0cf[i].reg);
|
||||
mtsdram(mem_tr0, 0x41094012);
|
||||
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
|
||||
mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
|
||||
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
|
||||
udelay(400); /* Delay 200 usecs (min) */
|
||||
|
||||
/*
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
|
||||
udelay(10000);
|
||||
|
||||
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
|
||||
/*
|
||||
* OK, size detected -> all done
|
||||
*/
|
||||
return mb0cf[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
return 0; /* nothing found ! */
|
||||
}
|
||||
|
||||
#endif /* CONFIG_440 */
|
||||
|
||||
#endif /* CONFIG_SDRAM_BANK0 */
|
||||
|
|
|
|||
|
|
@ -444,6 +444,8 @@ __440gx_msr_continue:
|
|||
stw r0,+12(r1) /* Save return addr (underflow vect) */
|
||||
|
||||
GET_GOT
|
||||
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
bl board_init_f
|
||||
|
||||
#endif /* CONFIG_440 */
|
||||
|
|
|
|||
|
|
@ -340,8 +340,10 @@ unsigned long flash_init (void)
|
|||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
size += flash_info[i].size = flash_get_size (bank_base[i], i);
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
#ifndef CFG_FLASH_QUIET_TEST
|
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i, flash_info[i].size, flash_info[i].size << 20);
|
||||
#endif /* CFG_FLASH_QUIET_TEST */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,318 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* board/config_p3p440.h - configuration for Prodrive P3P440
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_P3P440 1 /* Board is P3P440 */
|
||||
#define CONFIG_440GP 1 /* Specifc GP support */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
|
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
|
||||
#define CFG_SDRAM_TABLE { \
|
||||
{(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
|
||||
{(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C RTC
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (PCF8594C) for environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
|
||||
/* 8 byte page write mode using */
|
||||
/* last 3 bits of the address */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Default configuration (environment varibles...)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=p3p440\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/p3p440/uImage\0" \
|
||||
"kernel_addr=ff800000\0" \
|
||||
"ramdisk_addr=ff810000\0" \
|
||||
"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x1c /* PHY address */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_SNTP )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */
|
||||
|
||||
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH0 0xFF800000
|
||||
#define CFG_FLASH1 0xFF000000
|
||||
#define CFG_FLASH2 0xFE800000
|
||||
#define CFG_FLASH3 0xFE000000
|
||||
#define CFG_USB 0xF0000000
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x03050200
|
||||
#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB1AP 0x03050200
|
||||
#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB2AP 0x03050200
|
||||
#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB3AP 0x03050200
|
||||
#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 7 (USB controller) initialization */
|
||||
#define CFG_EBC_PB7AP 0x02015000
|
||||
#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -547,6 +547,8 @@
|
|||
#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
|
||||
#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
|
||||
|
||||
#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
|
||||
|
||||
#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
|
||||
#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
|
||||
|
||||
|
|
@ -1392,6 +1394,15 @@
|
|||
/******************************************************************************
|
||||
* GPIO macro register defines
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_440GP)
|
||||
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
|
||||
|
||||
#define GPIO0_OR (GPIO_BASE0+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE0+0x4)
|
||||
#define GPIO0_ODR (GPIO_BASE0+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE0+0x1C)
|
||||
#endif /* CONFIG_440GP */
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
|
||||
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
|
||||
|
|
|
|||
Loading…
Reference in New Issue