mpc83xx: Add the support of MPC8315E SoC
The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu
Kim Phillips
parent
03051c3d35
commit
555da61702
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@ -153,6 +153,18 @@ int checkcpu(void)
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case SPR_8313E_REV10:
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puts("MPC8313E, ");
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break;
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case SPR_8315E_REV10:
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puts("MPC8315E, ");
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break;
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case SPR_8315_REV10:
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puts("MPC8315, ");
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break;
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case SPR_8314E_REV10:
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puts("MPC8314E, ");
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break;
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case SPR_8314_REV10:
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puts("MPC8314, ");
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break;
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case SPR_8379E_REV10:
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puts("MPC8379E, ");
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break;
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@ -113,6 +113,9 @@ int get_clocks(void)
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#if !defined(CONFIG_MPC832X)
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u32 i2c2_clk;
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#endif
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#if defined(CONFIG_MPC8315)
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u32 tdm_clk;
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#endif
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#if defined(CONFIG_MPC837X)
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u32 sdhc_clk;
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#endif
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@ -132,6 +135,8 @@ int get_clocks(void)
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#if defined(CONFIG_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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u32 sata_clk;
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#endif
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@ -197,7 +202,7 @@ int get_clocks(void)
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}
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#endif
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#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
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#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
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case 0:
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tsec2_clk = 0;
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@ -215,7 +220,7 @@ int get_clocks(void)
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/* unkown SCCR_TSEC2CM value */
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return -4;
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}
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#elif defined(CONFIG_MPC831X)
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#elif defined(CONFIG_MPC8313)
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tsec2_clk = tsec1_clk;
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if (!(sccr & SCCR_TSEC1ON))
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@ -288,6 +293,25 @@ int get_clocks(void)
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return -8;
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}
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#endif
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#if defined(CONFIG_MPC8315)
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switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
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case 0:
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tdm_clk = 0;
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break;
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case 1:
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tdm_clk = csb_clk;
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break;
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case 2:
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tdm_clk = csb_clk / 2;
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break;
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case 3:
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tdm_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_TDMCM value */
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return -8;
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}
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#endif
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#if defined(CONFIG_MPC834X)
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i2c1_clk = tsec2_clk;
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@ -342,7 +366,7 @@ int get_clocks(void)
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}
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#endif
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#if defined(CONFIG_MPC837X)
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
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case 0:
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sata_clk = 0;
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@ -428,6 +452,9 @@ int get_clocks(void)
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#if defined(CONFIG_MPC834X)
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gd->usbmph_clk = usbmph_clk;
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#endif
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#if defined(CONFIG_MPC8315)
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gd->tdm_clk = tdm_clk;
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#endif
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#if defined(CONFIG_MPC837X)
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gd->sdhc_clk = sdhc_clk;
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#endif
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@ -450,6 +477,8 @@ int get_clocks(void)
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#if defined(CONFIG_MPC837X)
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gd->pciexp1_clk = pciexp1_clk;
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gd->pciexp2_clk = pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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gd->sata_clk = sata_clk;
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#endif
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gd->pci_clk = pci_sync_in;
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@ -488,6 +517,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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#if !defined(CONFIG_MPC832X)
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printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
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#endif
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#if defined(CONFIG_MPC8315)
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printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
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#endif
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#if defined(CONFIG_MPC837X)
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printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
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#endif
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@ -502,6 +534,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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#if defined(CONFIG_MPC837X)
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printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
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printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
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#endif
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
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#endif
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return 0;
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@ -63,6 +63,9 @@ typedef struct global_data {
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#if defined (CONFIG_MPC834X)
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u32 usbmph_clk;
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#endif /* CONFIG_MPC834X */
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#if defined(CONFIG_MPC815)
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u32 tdm_clk;
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#endif
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#if defined(CONFIG_MPC837X)
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u32 sdhc_clk;
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#endif
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@ -77,6 +80,8 @@ typedef struct global_data {
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#if defined(CONFIG_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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u32 sata_clk;
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#endif
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#if defined(CONFIG_MPC8360)
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@ -589,6 +589,20 @@ typedef struct rom83xx {
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u8 mem[0x10000];
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} rom83xx_t;
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/*
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* TDM
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*/
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typedef struct tdm83xx {
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u8 fixme[0x200];
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} tdm83xx_t;
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/*
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* TDM DMAC
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*/
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typedef struct tdmdmac83xx {
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u8 fixme[0x2000];
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} tdmdmac83xx_t;
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#if defined(CONFIG_MPC834X)
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typedef struct immap {
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sysconf83xx_t sysconf; /* System configuration */
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@ -626,7 +640,7 @@ typedef struct immap {
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u8 res7[0xC0000];
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} immap_t;
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#elif defined(CONFIG_MPC831X)
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#elif defined(CONFIG_MPC8313)
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typedef struct immap {
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sysconf83xx_t sysconf; /* System configuration */
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wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
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@ -661,6 +675,51 @@ typedef struct immap {
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u8 res7[0xC0000];
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} immap_t;
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#elif defined(CONFIG_MPC8315)
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typedef struct immap {
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sysconf83xx_t sysconf; /* System configuration */
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wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
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rtclk83xx_t rtc; /* Real Time Clock Module Registers */
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rtclk83xx_t pit; /* Periodic Interval Timer */
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gtm83xx_t gtm[2]; /* Global Timers Module */
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ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
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arbiter83xx_t arbiter; /* System Arbiter Registers */
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reset83xx_t reset; /* Reset Module */
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clk83xx_t clk; /* System Clock Module */
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pmc83xx_t pmc; /* Power Management Control Module */
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gpio83xx_t gpio[1]; /* General purpose I/O module */
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u8 res0[0x1300];
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ddr83xx_t ddr; /* DDR Memory Controller Memory */
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fsl_i2c_t i2c[2]; /* I2C Controllers */
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u8 res1[0x1300];
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duart83xx_t duart[2]; /* DUART */
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u8 res2[0x900];
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lbus83xx_t lbus; /* Local Bus Controller Registers */
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u8 res3[0x1000];
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spi83xx_t spi; /* Serial Peripheral Interface */
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dma83xx_t dma; /* DMA */
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pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
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u8 res4[0x80];
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ios83xx_t ios; /* Sequencer */
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pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
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u8 res5[0xa00];
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pex83xx_t pciexp[2]; /* PCI Express Controller */
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u8 res6[0xb000];
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tdm83xx_t tdm; /* TDM Controller */
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u8 res7[0x1e00];
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sata83xx_t sata[2]; /* SATA Controller */
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u8 res8[0x9000];
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usb83xx_t usb[1]; /* USB DR Controller */
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tsec83xx_t tsec[2];
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u8 res9[0x6000];
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tdmdmac83xx_t tdmdmac; /* TDM DMAC */
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u8 res10[0x2000];
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security83xx_t security;
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u8 res11[0xA3000];
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serdes83xx_t serdes[1]; /* SerDes Registers */
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u8 res12[0x1CF00];
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} immap_t;
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#elif defined(CONFIG_MPC837X)
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typedef struct immap {
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sysconf83xx_t sysconf; /* System configuration */
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@ -102,6 +102,10 @@
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#define SPR_8313_REV10 0x80B10010
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#define SPR_8311E_REV10 0x80B20010
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#define SPR_8311_REV10 0x80B30010
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#define SPR_8315E_REV10 0x80B40010
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#define SPR_8315_REV10 0x80B50010
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#define SPR_8314E_REV10 0x80B60010
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#define SPR_8314_REV10 0x80B70010
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#define SPR_8379E_REV10 0x80C20010
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#define SPR_8379_REV10 0x80C30010
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@ -220,8 +224,8 @@
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#define SICRL_URT_CTPR 0x06000000
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#define SICRL_IRQ_CTPR 0x00C00000
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#elif defined(CONFIG_MPC831X)
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/* SICRL bits - MPC831x specific */
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#elif defined(CONFIG_MPC8313)
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/* SICRL bits - MPC8313 specific */
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#define SICRL_LBC 0x30000000
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#define SICRL_UART 0x0C000000
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#define SICRL_SPI_A 0x03000000
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@ -232,7 +236,7 @@
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#define SICRL_ETSEC1_A 0x0000000C
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#define SICRL_ETSEC2_A 0x00000003
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/* SICRH bits - MPC831x specific */
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/* SICRH bits - MPC8313 specific */
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#define SICRH_INTR_A 0x02000000
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#define SICRH_INTR_B 0x00C00000
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#define SICRH_IIC 0x00300000
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@ -249,6 +253,41 @@
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#define SICRH_TSOBI1 0x00000002
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#define SICRH_TSOBI2 0x00000001
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#elif defined(CONFIG_MPC8315)
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/* SICRL bits - MPC8315 specific */
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#define SICRL_DMA_CH0 0xc0000000
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#define SICRL_DMA_SPI 0x30000000
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#define SICRL_UART 0x0c000000
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#define SICRL_IRQ4 0x02000000
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#define SICRL_IRQ5 0x01800000
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#define SICRL_IRQ6_7 0x00400000
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#define SICRL_IIC1 0x00300000
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#define SICRL_TDM 0x000c0000
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#define SICRL_TDM_SHARED 0x00030000
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#define SICRL_PCI_A 0x0000c000
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#define SICRL_ELBC_A 0x00003000
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#define SICRL_ETSEC1_A 0x000000c0
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#define SICRL_ETSEC1_B 0x00000030
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#define SICRL_ETSEC1_C 0x0000000c
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#define SICRL_TSEXPOBI 0x00000001
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/* SICRH bits - MPC8315 specific */
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#define SICRH_GPIO_0 0xc0000000
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#define SICRH_GPIO_1 0x30000000
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#define SICRH_GPIO_2 0x0c000000
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#define SICRH_GPIO_3 0x03000000
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#define SICRH_GPIO_4 0x00c00000
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#define SICRH_GPIO_5 0x00300000
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#define SICRH_GPIO_6 0x000c0000
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#define SICRH_GPIO_7 0x00030000
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#define SICRH_GPIO_8 0x0000c000
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#define SICRH_GPIO_9 0x00003000
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#define SICRH_GPIO_10 0x00000c00
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#define SICRH_GPIO_11 0x00000300
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#define SICRH_ETSEC2_A 0x000000c0
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#define SICRH_TSOBI1 0x00000002
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#define SICRH_TSOBI2 0x00000001
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#elif defined(CONFIG_MPC837X)
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/* SICRL bits - MPC837x specific */
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#define SICRL_USB_A 0xC0000000
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@ -447,7 +486,7 @@
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#define HRCWL_CE_TO_PLL_1X30 0x0000001E
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#define HRCWL_CE_TO_PLL_1X31 0x0000001F
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#elif defined(CONFIG_MPC837X)
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#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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#define HRCWL_SVCOD 0x30000000
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#define HRCWL_SVCOD_SHIFT 28
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#define HRCWL_SVCOD_DIV_4 0x00000000
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@ -556,7 +595,7 @@
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/* RSR - Reset Status Register
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*/
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#if defined(CONFIG_MPC837X)
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#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
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#define RSR_RSTSRC 0xF0000000 /* Reset source */
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#define RSR_RSTSRC_SHIFT 28
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#else
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@ -677,7 +716,7 @@
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#define SCCR_USBCM_2 0x00A00000
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#define SCCR_USBCM_3 0x00F00000
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#elif defined(CONFIG_MPC831X)
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#elif defined(CONFIG_MPC8313)
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/* TSEC1 bits are for TSEC2 as well */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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@ -697,6 +736,48 @@
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#define SCCR_USBDRCM_2 0x00200000
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#define SCCR_USBDRCM_3 0x00300000
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#elif defined(CONFIG_MPC8315)
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/* SCCR bits - MPC8315 specific */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC1CM_0 0x00000000
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#define SCCR_TSEC1CM_1 0x40000000
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#define SCCR_TSEC1CM_2 0x80000000
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#define SCCR_TSEC1CM_3 0xC0000000
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#define SCCR_TSEC2CM 0x30000000
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#define SCCR_TSEC2CM_SHIFT 28
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#define SCCR_TSEC2CM_0 0x00000000
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#define SCCR_TSEC2CM_1 0x10000000
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#define SCCR_TSEC2CM_2 0x20000000
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#define SCCR_TSEC2CM_3 0x30000000
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#define SCCR_USBDRCM 0x00300000
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#define SCCR_USBDRCM_SHIFT 20
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#define SCCR_USBDRCM_0 0x00000000
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#define SCCR_USBDRCM_1 0x00100000
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#define SCCR_USBDRCM_2 0x00200000
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#define SCCR_USBDRCM_3 0x00300000
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#define SCCR_PCIEXP1CM 0x00080000
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#define SCCR_PCIEXP2CM 0x00040000
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#define SCCR_SATA1CM 0x0000c000
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#define SCCR_SATA1CM_SHIFT 14
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#define SCCR_SATACM 0x0000f000
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#define SCCR_SATACM_SHIFT 8
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#define SCCR_SATACM_0 0x00000000
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#define SCCR_SATACM_1 0x00005000
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#define SCCR_SATACM_2 0x0000a000
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#define SCCR_SATACM_3 0x0000f000
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#define SCCR_TDMCM 0x000000c0
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#define SCCR_TDMCM_SHIFT 6
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#define SCCR_TDMCM_0 0x00000000
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#define SCCR_TDMCM_1 0x00000040
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#define SCCR_TDMCM_2 0x00000080
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#define SCCR_TDMCM_3 0x000000c0
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#elif defined(CONFIG_MPC837X)
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/* SCCR bits - MPC837x specific */
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#define SCCR_TSEC1CM 0xc0000000
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