85xx: Export invalidate_{i,d}cache and add flush_dcache
Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -565,6 +565,7 @@ mck_return:
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/* Cache functions.
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*/
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.globl invalidate_icache
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invalidate_icache:
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mfspr r0,L1CSR1
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ori r0,r0,L1CSR1_ICFI
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@ -574,6 +575,7 @@ invalidate_icache:
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isync
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blr /* entire I cache */
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.globl invalidate_dcache
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invalidate_dcache:
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mfspr r0,L1CSR0
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ori r0,r0,L1CSR0_DCFI
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@ -1019,3 +1021,50 @@ unlock_ram_in_cache:
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tlbivax 0,r3
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isync
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blr
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.globl flush_dcache
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flush_dcache:
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mfspr r3,SPRN_L1CFG0
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rlwinm r5,r3,9,3 /* Extract cache block size */
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twlgti r5,1 /* Only 32 and 64 byte cache blocks
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* are currently defined.
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*/
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li r4,32
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subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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* log2(number of ways)
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*/
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slw r5,r4,r5 /* r5 = cache block size */
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rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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mulli r7,r7,13 /* An 8-way cache will require 13
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* loads per set.
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*/
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slw r7,r7,r6
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/* save off HID0 and set DCFA */
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mfspr r8,SPRN_HID0
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ori r9,r8,HID0_DCFA@l
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mtspr SPRN_HID0,r9
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isync
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lis r4,0
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mtctr r7
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1: lwz r3,0(r4) /* Load... */
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add r4,r4,r5
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bdnz 1b
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msync
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lis r4,0
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mtctr r7
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1: dcbf 0,r4 /* ...and flush. */
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add r4,r4,r5
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bdnz 1b
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/* restore HID0 */
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mtspr SPRN_HID0,r8
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isync
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blr
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@ -44,6 +44,7 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache(void);
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extern void invalidate_dcache(void);
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extern void invalidate_icache(void);
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#ifdef CONFIG_SYS_INIT_RAM_LOCK
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extern void unlock_ram_in_cache(void);
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#endif /* CONFIG_SYS_INIT_RAM_LOCK */
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