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PCU_E: remove code for yet another corpse

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The PCU_E board has long reached EOL, and support for it is no longer
relevant in current versions of U-Boot.  Remove it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
master
Wolfgang Denk 13 years ago
parent 6f984adb31
commit 544d97e9aa
15 changed files with 9 additions and 2163 deletions
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1
MAINTAINERS
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@ -117,7 +117,6 @@ Wolfgang Denk <wd@denx.de>
c2mon MPC855
hermes MPC860
lwmon MPC823
pcu_e MPC855
CU824 MPC8240
Sandpoint8240 MPC8240

2
README
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@ -1781,7 +1781,7 @@ The following options need to be configured:
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON, LANTEC,
PCU_E, FLAGADM, TQM8260
FLAGADM, TQM8260
- Error Recovery:
CONFIG_PANIC_HANG

4
arch/m68k/lib/board.c
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@ -73,10 +73,6 @@ DECLARE_GLOBAL_DATA_PTR;
static char *failed = "*** failed ***\n";
#ifdef CONFIG_PCU_E
extern flash_info_t flash_info[];
#endif
#include <environment.h>
extern ulong __init_end;

1
arch/powerpc/cpu/mpc8xx/cpu_init.c
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@ -156,7 +156,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MHPC) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_RPXCLASSIC) || \

4
arch/powerpc/lib/board.c
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@ -107,7 +107,7 @@ void doc_init (void);
static char *failed = "*** failed ***\n";
#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
extern flash_info_t flash_info[];
#endif
@ -735,7 +735,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
#endif
# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = TEXT_BASE + flash_size;
# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE

44
board/siemens/pcu_e/Makefile
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@ -1,44 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

28
board/siemens/pcu_e/config.mk
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@ -1,28 +0,0 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Siemens PCU E Boards
#
TEXT_BASE = 0xFFF00000

700
board/siemens/pcu_e/flash.c
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@ -1,700 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
# endif
# ifndef CONFIG_ENV_SECT_SIZE
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# endif
#endif
/*---------------------------------------------------------------------*/
#undef DEBUG_FLASH
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*
* The PCU E uses an address map where flash banks are aligned top
* down, so that the "first" flash bank ends at top of memory, and
* the monitor entry point is at address (0xFFF00100). The second
* flash bank is mapped immediately below bank 0.
*
* This is NOT in conformance to the "official" memory map!
*
*/
#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
- (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long base, size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
/*
* Warning:
*
* Since the PCU E memory map assigns flash banks top down,
* we swap the numbering later if both banks are equipped,
* so they look like a contiguous area of memory.
*/
DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
if (size_b1 > size_b0) {
printf ("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,
size_b0, size_b0<<20
);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
flash_info[1].sector_count = -1;
flash_info[0].size = 0;
flash_info[1].size = 0;
return (0);
}
DEBUGF ("## Before remap: "
"BR0: 0x%08x OR0: 0x%08x "
"BR6: 0x%08x OR6: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0,
memctl->memc_br6, memctl->memc_or6);
/* Remap FLASH according to real size */
base = 0 - size_b0;
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
base = 0 - size_b0;
flash_info[0].size = size_b0;
flash_get_offsets (base, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
PCU_MONITOR_BASE,
PCU_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
&flash_info[0]);
#endif
if (size_b1) {
flash_info_t tmp_info;
memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
BR_PS_16 | BR_MS_GPCM | BR_V;
DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
memctl->memc_br6, memctl->memc_or6);
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)(base - size_b1),
&flash_info[1]);
base -= size_b1;
flash_get_offsets (base, &flash_info[1]);
flash_info[1].size = size_b1;
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
&flash_info[1]);
#endif
/*
* Swap bank numbers so that addresses are in ascending order
*/
tmp_info = flash_info[0];
flash_info[0] = flash_info[1];
flash_info[1] = tmp_info;
} else {
memctl->memc_br1 = 0; /* invalidate bank */
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
short n;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
return;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMDL322T:
case FLASH_AMDL323T:
case FLASH_AMDL324T:
/* set sector offsets for top boot block type */
base += info->size;
i = info->sector_count;
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
base -= 8 << 10;
--i;
info->start[i] = base;
}
while (i > 0) { /* 64k regular sectors */
base -= 64 << 10;
--i;
info->start[i] = base;
}
return;
case FLASH_AMDL322B:
case FLASH_AMDL323B:
case FLASH_AMDL324B:
/* set sector offsets for bottom boot block type */
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
info->start[i] = base;
base += 8 << 10;
}
while (base < info->size) { /* 64k regular sectors */
info->start[i] = base;
base += 64 << 10;
++i;
}
return;
case FLASH_AMDL640:
/* set sector offsets for dual boot block type */
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
info->start[i] = base;
base += 8 << 10;
}
n = info->sector_count - 8;
while (i < n) { /* 64k regular sectors */
info->start[i] = base;
base += 64 << 10;
++i;
}
while (i < info->sector_count) { /* 8 x 8k boot sectors */
info->start[i] = base;
base += 8 << 10;
++i;
}
return;
default:
return;
}
/* NOTREACHED */
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
break;
case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
break;
default: printf ("Unknown Chip Type 0x%lX\n",
info->flash_id);
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ushort value;
vu_short *saddr = (vu_short *)addr;
/* Write auto select command: read Manufacturer ID */
saddr[0x0555] = 0x00AA;
saddr[0x02AA] = 0x0055;
saddr[0x0555] = 0x0090;
value = saddr[0];
DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
switch (value) {
case (AMD_MANUFACT & 0xFFFF):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & 0xFFFF):
info->flash_id = FLASH_MAN_FUJ;
break;
default:
DEBUGF("Unknown Manufacturer ID\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = saddr[1]; /* device ID */
DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
switch (value) {
case (AMD_ID_DL322T & 0xFFFF):
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL322B & 0xFFFF):
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL323T & 0xFFFF):
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL323B & 0xFFFF):
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL324T & 0xFFFF):
info->flash_id += FLASH_AMDL324T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL324B & 0xFFFF):
info->flash_id += FLASH_AMDL324B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
case (AMD_ID_DL640 & 0xFFFF):
info->flash_id += FLASH_AMDL640;
info->sector_count = 142;
info->size = 0x00800000;
break;
default:
DEBUGF("Unknown Device ID\n");
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
flash_get_offsets ((ulong)addr, info);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
#if 0
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
saddr = (vu_short *)(info->start[i]);
info->protect[i] = saddr[2] & 1;
#else
info->protect[i] =0;
#endif
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
saddr = (vu_short *)info->start[0];
*saddr = 0x00F0; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_short *addr = (vu_short*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
addr[0x0555] = 0x0080;
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_short*)(info->start[sect]);
addr[0] = 0x0030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_short*)(info->start[l_sect]);
while ((addr[0] & 0x0080) != 0x0080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_short *)info->start[0];
addr[0] = 0x00F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
#define FLASH_WIDTH 2 /* flash bus width in bytes */
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<FLASH_WIDTH && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += FLASH_WIDTH;
}
/*
* handle FLASH_WIDTH aligned part
*/
while (cnt >= FLASH_WIDTH) {
data = 0;
for (i=0; i<FLASH_WIDTH; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += FLASH_WIDTH;
cnt -= FLASH_WIDTH;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<FLASH_WIDTH; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_data(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, ulong data)
{
vu_short *addr = (vu_short*)(info->start[0]);
vu_short *sdest = (vu_short *)dest;
ushort sdata = (ushort)data;
ushort sval;
ulong start, passed;
int flag, rc;
/* Check if Flash is (sufficiently) erased */
if ((*sdest & sdata) != sdata) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
addr[0x0555] = 0x00A0;
#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
/* work around the timeout bugs */
udelay(20);
#endif
*sdest = sdata;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
rc = 0;
/* data polling for D7 */
start = get_timer (0);
for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
sval = *sdest;
if ((sval & 0x0080) == (sdata & 0x0080))
break;
if ((sval & 0x0020) == 0) /* DQ5: Timeout? */
continue;
sval = *sdest;
if ((sval & 0x0080) != (sdata & 0x0080))
rc = 1;
break;
}
if (rc) {
DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
dest, sval, sdata);
}
if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
dest, sval, sdata);
rc = 1;
}
/* reset to read mode */
addr = (vu_short *)info->start[0];
addr[0] = 0x00F0; /* reset bank */
return (rc);
}
/*-----------------------------------------------------------------------
*/

562
board/siemens/pcu_e/pcu_e.c
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@ -1,562 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
static void puma_status (void);
static void puma_set_mode (int mode);
static int puma_init_done (void);
static void puma_load (ulong addr, ulong len);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
/*
* 50 MHz SDRAM access using UPM A
*/
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
0x1ffddc47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7ffffc07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* PUMA access using UPM B
*/
const uint puma_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_,
/*
* Precharge and MRS
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7ffffc07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
*/
int checkboard (void)
{
puts ("Board: Siemens PCU E\n");
return (0);
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0, reg;
int i;
/*
* Configure UPMA for SDRAM
*/
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
/* burst length=4, burst type=sequential, CAS latency=2 */
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 2 to the SDRAM bank at preliminary address.
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#else /* XXX */
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif /* XXX */
/* initialize memory address register */
memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
/* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay (200); /* 0x8000A105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
#else /* XXX */
udelay (200); /* 0x80004105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
#endif /* XXX */
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay (1); /* 0x8000A830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
#else /* XXX */
udelay (1); /* 0x80004830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
#endif /* XXX */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay (1); /* 0x8000A106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
#else /* XXX */
udelay (1); /* 0x80004106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
#endif /* XXX */
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
reg |= MAMR_TLFA_4X; /* ... to 4x */
reg |= MAMR_PTAE; /* enable refresh */
memctl->memc_mamr = reg;
udelay (200);
/* Need at least 10 DRAM accesses to stabilize */
for (i = 0; i < 10; ++i) {
#if PCU_E_WITH_SWAPPED_CS /* XXX */
volatile unsigned long *addr =
(volatile unsigned long *) SDRAM_BASE5_PRELIM;
#else /* XXX */
volatile unsigned long *addr =
(volatile unsigned long *) SDRAM_BASE2_PRELIM;
#endif /* XXX */
unsigned long val;
val = *(addr + i);
*(addr + i) = val;
}
/*
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
/*
* Final mapping:
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#else /* XXX */
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#endif /* XXX */
udelay (1000);
/*
* Configure UPMB for PUMA
*/
upmconfig (UPMB, (uint *) puma_table,
sizeof (puma_table) / sizeof (uint));
return (size_b0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
memctl->memc_mamr = mamr_value;
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
#else /* XXX */
#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
#endif /* XXX */
#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
void reset_phy (void)
{
immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ulong value;
/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
# endif
immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */
#endif /* XXX */
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
value = immr->im_cpm.cp_pbdat;
/* Assert Powerdown and Reset signals */
value |= CONFIG_SYS_PB_ETH_POWERDOWN;
value &= ~(CONFIG_SYS_PB_ETH_RESET);
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
value |= CONFIG_SYS_PB_ETH_MDDIS;
# else
value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
# endif
#endif
#ifdef CONFIG_SYS_ETH_CFG1_VALUE
value |= CONFIG_SYS_PB_ETH_CFG1;
#else
value &= ~(CONFIG_SYS_PB_ETH_CFG1);
#endif
#ifdef CONFIG_SYS_ETH_CFG2_VALUE
value |= CONFIG_SYS_PB_ETH_CFG2;
#else
value &= ~(CONFIG_SYS_PB_ETH_CFG2);
#endif
#ifdef CONFIG_SYS_ETH_CFG3_VALUE
value |= CONFIG_SYS_PB_ETH_CFG3;
#else
value &= ~(CONFIG_SYS_PB_ETH_CFG3);
#endif
/* Drive output signals to initial state */
immr->im_cpm.cp_pbdat = value;
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
udelay (10000);
/* De-assert Ethernet Powerdown */
immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay (10000);
/* de-assert RESET signal of PHY */
immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
udelay (1000);
}
/*-----------------------------------------------------------------------
* Board Special Commands: access functions for "PUMA" FPGA
*/
#if defined(CONFIG_CMD_BSP)
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, len;
switch (argc) {
case 2: /* PUMA reset */
if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
puma_status ();
return 0;
}
break;
case 4: /* PUMA load addr len */
if (strcmp (argv[1], "load") != 0)
break;
addr = simple_strtoul (argv[2], NULL, 16);
len = simple_strtoul (argv[3], NULL, 16);
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
addr, len, len);
puma_load (addr, len);
return 0;
default:
break;
}
return cmd_usage(cmdtp);
}
U_BOOT_CMD (puma, 4, 1, do_puma,
"access PUMA FPGA",
"status - print PUMA status\n"
"puma load addr len - load PUMA configuration data"
);
#endif
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_set_mode (int mode)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_br3 = 0;
#else /* XXX */
memctl->memc_br4 = 0;
#endif /* XXX */
switch (mode) {
case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_READ;
memctl->memc_br3 = PUMA_CONF_BR_READ;
#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
break;
case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_LOAD;
memctl->memc_br3 = PUMA_CONF_BR_LOAD;
#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
break;
}
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
static void puma_load (ulong addr, ulong len)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
uchar *data = (uchar *) addr;
int i;
/* align length */
if (len & 1)
++len;
/* Reset FPGA */
immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */
#else
immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */
#endif /* XXX */
udelay (100);
#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
#else
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
#endif /* XXX */
/* wait until INIT indicates completion of reset */
for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
udelay (1000);
if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
break;
}
if (i == PUMA_INIT_TIMEOUT) {
printf ("*** PUMA init timeout ***\n");
return;
}
puma_set_mode (PUMA_LOAD_MODE);
while (len--)
*fpga_addr = *data++;
puma_set_mode (PUMA_READ_MODE);
puma_status ();
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_status (void)
{
/* Check state */
printf ("PUMA initialization is %scomplete\n",
puma_init_done ()? "" : "NOT ");
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static int puma_init_done (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* make sure pin is GPIO input */
immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
ulong addr = 0;
ulong len = 0;
char *s;
printf ("PUMA: ");
if (puma_init_done ()) {
printf ("initialized\n");
return 0;
}
if ((s = getenv ("puma_addr")) != NULL)
addr = simple_strtoul (s, NULL, 16);
if ((s = getenv ("puma_len")) != NULL)
len = simple_strtoul (s, NULL, 16);
if ((!addr) || (!len)) {
printf ("net list undefined\n");
return 0;
}
printf ("loading... ");
puma_load (addr, len);
return (0);
}
/* ------------------------------------------------------------------------- */

127
board/siemens/pcu_e/u-boot.lds
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@ -1,127 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;