OMAP3: SPI driver
CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Dirk Behme
Sandeep Paulraj
parent
3e664f6d50
commit
53736baaff
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@ -35,6 +35,7 @@ COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
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COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
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COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
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COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
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COBJS := $(COBJS-y)
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@ -0,0 +1,352 @@
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/*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include "omap3_spi.h"
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#define WORD_LEN 8
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#define SPI_WAIT_TIMEOUT 3000000;
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static void spi_reset(struct omap3_spi_slave *ds)
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{
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unsigned int tmp;
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writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &ds->regs->sysconfig);
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do {
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tmp = readl(&ds->regs->sysstatus);
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} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
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writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
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&ds->regs->sysconfig);
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writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
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}
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct omap3_spi_slave *ds;
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ds = malloc(sizeof(struct omap3_spi_slave));
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if (!ds) {
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printf("SPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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/*
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* OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
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* with different number of chip selects (CS, channels):
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* McSPI1 has 4 CS (bus 0, cs 0 - 3)
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* McSPI2 has 2 CS (bus 1, cs 0 - 1)
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* McSPI3 has 2 CS (bus 2, cs 0 - 1)
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* McSPI4 has 1 CS (bus 3, cs 0)
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*/
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switch (bus) {
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case 0:
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ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
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break;
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case 1:
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ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
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break;
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case 2:
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ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
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break;
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case 3:
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ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
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break;
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default:
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printf("SPI error: unsupported bus %i. \
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Supported busses 0 - 3\n", bus);
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return NULL;
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}
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ds->slave.bus = bus;
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if (((bus == 0) && (cs > 3)) ||
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((bus == 1) && (cs > 1)) ||
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((bus == 2) && (cs > 1)) ||
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((bus == 3) && (cs > 0))) {
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printf("SPI error: unsupported chip select %i \
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on bus %i\n", cs, bus);
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return NULL;
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}
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ds->slave.cs = cs;
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if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
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printf("SPI error: unsupported frequency %i Hz. \
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Max frequency is 48 Mhz\n", max_hz);
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return NULL;
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}
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ds->freq = max_hz;
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if (mode > SPI_MODE_3) {
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printf("SPI error: unsupported SPI mode %i\n", mode);
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return NULL;
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}
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ds->mode = mode;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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unsigned int conf, div = 0;
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/* McSPI global module configuration */
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/*
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* setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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spi_reset(ds);
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conf = readl(&ds->regs->modulctrl);
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conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
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conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
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writel(conf, &ds->regs->modulctrl);
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/* McSPI individual channel configuration */
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/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
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if (ds->freq) {
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while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
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> ds->freq)
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div++;
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} else
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div = 0xC;
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conf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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conf |= OMAP3_MCSPI_CHCONF_DPE0;
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/* wordlength */
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conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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conf |= (WORD_LEN - 1) << 7;
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/* set chipselect polarity; manage with FORCE */
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if (!(ds->mode & SPI_CS_HIGH))
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conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
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else
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conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
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/* set clock divisor */
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conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
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conf |= div << 2;
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/* set SPI mode 0..3 */
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if (ds->mode & SPI_CPOL)
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conf |= OMAP3_MCSPI_CHCONF_POL;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_POL;
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if (ds->mode & SPI_CPHA)
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conf |= OMAP3_MCSPI_CHCONF_PHA;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_PHA;
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/* Transmit & receive mode */
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conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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writel(conf, &ds->regs->channel[ds->slave.cs].chconf);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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/* Reset the SPI hardware */
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spi_reset(ds);
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}
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int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
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unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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int i;
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int timeout = SPI_WAIT_TIMEOUT;
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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if (flags & SPI_XFER_BEGIN)
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writel(OMAP3_MCSPI_CHCTRL_EN,
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&ds->regs->channel[ds->slave.cs].chctrl);
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chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
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for (i = 0; i < len; i++) {
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/* wait till TX register is empty (TXS == 1) */
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (--timeout <= 0) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
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}
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if (flags & SPI_XFER_END) {
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/* wait to finish of transfer */
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_EOT));
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
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writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
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}
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return 0;
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}
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int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
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unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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int i;
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int timeout = SPI_WAIT_TIMEOUT;
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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if (flags & SPI_XFER_BEGIN)
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writel(OMAP3_MCSPI_CHCTRL_EN,
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&ds->regs->channel[ds->slave.cs].chctrl);
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chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
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writel(0, &ds->regs->channel[ds->slave.cs].tx);
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for (i = 0; i < len; i++) {
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/* Wait till RX register contains data (RXS == 1) */
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while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (--timeout <= 0) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&ds->regs->channel[ds->slave.cs].chstat));
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return -1;
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}
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}
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/* Read the data */
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rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
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writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct omap3_spi_slave *ds = to_omap3_spi(slave);
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unsigned int len;
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const u8 *txp = dout;
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u8 *rxp = din;
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int ret = -1;
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if (bitlen % 8)
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return -1;
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len = bitlen / 8;
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if (bitlen == 0) { /* only change CS */
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int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
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if (flags & SPI_XFER_BEGIN) {
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writel(OMAP3_MCSPI_CHCTRL_EN,
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&ds->regs->channel[ds->slave.cs].chctrl);
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf,
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&ds->regs->channel[ds->slave.cs].chconf);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf,
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&ds->regs->channel[ds->slave.cs].chconf);
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writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
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}
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ret = 0;
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} else {
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if (dout != NULL)
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ret = omap3_spi_write(slave, len, txp, flags);
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if (din != NULL)
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ret = omap3_spi_read(slave, len, rxp, flags);
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}
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return ret;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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@ -0,0 +1,117 @@
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/*
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* Register definitions for the OMAP3 McSPI Controller
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP3_SPI_H_
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#define _OMAP3_SPI_H_
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#define OMAP3_MCSPI1_BASE 0x48098000
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#define OMAP3_MCSPI2_BASE 0x4809A000
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#define OMAP3_MCSPI3_BASE 0x480B8000
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#define OMAP3_MCSPI4_BASE 0x480BA000
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#define OMAP3_MCSPI_MAX_FREQ 48000000
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/* OMAP3 McSPI registers */
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struct mcspi_channel {
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unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
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unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
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unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
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unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
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unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
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};
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struct mcspi {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned int irqstatus; /* 0x18 */
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unsigned int irqenable; /* 0x1C */
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unsigned int wakeupenable; /* 0x20 */
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unsigned int syst; /* 0x24 */
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unsigned int modulctrl; /* 0x28 */
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struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
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/* channel1: 0x40 - 0x50, bus 0 & 1 */
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/* channel2: 0x54 - 0x64, bus 0 & 1 */
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/* channel3: 0x68 - 0x78, bus 0 */
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};
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/* per-register bitmasks */
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#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
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#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
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#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
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#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
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#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
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#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
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#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
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#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
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#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
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#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
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#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
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#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
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||||
#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
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||||
#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
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||||
#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
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||||
#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
|
||||
#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
|
||||
#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
|
||||
#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
|
||||
#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
|
||||
|
||||
#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
|
||||
#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
|
||||
#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
|
||||
|
||||
#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
|
||||
|
||||
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
|
||||
|
||||
struct omap3_spi_slave {
|
||||
struct spi_slave slave;
|
||||
struct mcspi *regs;
|
||||
unsigned int freq;
|
||||
unsigned int mode;
|
||||
};
|
||||
|
||||
static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
|
||||
{
|
||||
return container_of(slave, struct omap3_spi_slave, slave);
|
||||
}
|
||||
|
||||
int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
|
||||
unsigned long flags);
|
||||
int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
|
||||
unsigned long flags);
|
||||
|
||||
#endif /* _OMAP3_SPI_H_ */
|
||||
|
|
@ -335,4 +335,6 @@ extern unsigned int boot_flash_type;
|
|||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_OMAP3_SPI
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue