POST: Add ECC POST for the lwmon5 board
This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pavel Kolesnikov
Stefan Roese
parent
8f085e324a
commit
531e3e8b83
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@ -463,3 +463,14 @@ void hw_watchdog_reset(void)
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val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
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gpio_write_bit(CFG_GPIO_WATCHDOG, val);
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}
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
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#endif
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@ -74,11 +74,13 @@
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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* Serial Port
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@ -133,6 +135,10 @@
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#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
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#if 0 /* test-only: disable ECC for now */
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#define CONFIG_DDR_ECC 1 /* enable ECC */
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/* POST support */
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#define CONFIG_POST (CFG_POST_ECC)
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#endif
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/*-----------------------------------------------------------------------
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@ -92,6 +92,7 @@ extern int post_hotkeys_pressed(void);
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#define CFG_POST_DSP 0x00001000
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#define CFG_POST_CODEC 0x00002000
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#define CFG_POST_FPU 0x00004000
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#define CFG_POST_ECC 0x00008000
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#endif /* CONFIG_POST */
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@ -0,0 +1,29 @@
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#
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# (C) Copyright 2002-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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LIB = libpostlwmon5.a
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COBJS = ecc.o
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include $(TOPDIR)/post/rules.mk
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@ -0,0 +1,257 @@
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/*
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* (C) Copyright 2007
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* Developed for DENX Software Engineering GmbH.
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*
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* Author: Pavel Kolesnikov <concord@emcraft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <watchdog.h>
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#ifdef CONFIG_POST
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#include <post.h>
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#if CONFIG_POST & CFG_POST_ECC
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/*
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* MEMORY ECC test
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*
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* This test performs the checks ECC facility of memory.
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*/
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <ppc440.h>
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#include "../../../board/lwmon5/sdram.h"
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DECLARE_GLOBAL_DATA_PTR;
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const static unsigned char syndrome_codes[] = {
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0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
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0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
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0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
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0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
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0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
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0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
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0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
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0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
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0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
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};
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#define ECC_START_ADDR 0x10
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#define ECC_STOP_ADDR 0x2000
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#define ECC_PATTERN 0x0101010101010101ull
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#define ECC_PATTERN_CORR 0x0101010101010100ull
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#define ECC_PATTERN_UNCORR 0x010101010101010Full
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static int test_ecc_error(void)
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{
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unsigned long value;
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unsigned long hdata, ldata, haddr, laddr;
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unsigned int bit;
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int ret = 0;
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mfsdram(DDR0_23, value);
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for (bit = 0; bit < sizeof(syndrome_codes); bit++)
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if (syndrome_codes[bit] == ((value >> 16) & 0xff))
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break;
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mfsdram(DDR0_00, value);
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if (value & DDR0_00_INT_STATUS_BIT0) {
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debug("Bit0. A single access outside the defined PHYSICAL"
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" memory space detected\n");
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mfsdram(DDR0_32, laddr);
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mfsdram(DDR0_33, haddr);
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debug(" addr = 0x%08x%08x\n", haddr, laddr);
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ret = 1;
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}
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if (value & DDR0_00_INT_STATUS_BIT1) {
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debug("Bit1. Multiple accesses outside the defined PHYSICAL"
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" memory space detected\n");
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ret = 2;
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}
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if (value & DDR0_00_INT_STATUS_BIT2) {
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debug("Bit2. Single correctable ECC event detected\n");
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mfsdram(DDR0_38, laddr);
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mfsdram(DDR0_39, haddr);
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mfsdram(DDR0_40, ldata);
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mfsdram(DDR0_41, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 3;
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}
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if (value & DDR0_00_INT_STATUS_BIT3) {
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debug("Bit3. Multiple correctable ECC events detected\n");
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mfsdram(DDR0_38, laddr);
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mfsdram(DDR0_39, haddr);
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mfsdram(DDR0_40, ldata);
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mfsdram(DDR0_41, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 4;
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}
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if (value & DDR0_00_INT_STATUS_BIT4) {
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debug("Bit4. Single uncorrectable ECC event detected\n");
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mfsdram(DDR0_34, laddr);
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mfsdram(DDR0_35, haddr);
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mfsdram(DDR0_36, ldata);
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mfsdram(DDR0_37, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 5;
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}
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if (value & DDR0_00_INT_STATUS_BIT5) {
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debug("Bit5. Multiple uncorrectable ECC events detected\n");
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mfsdram(DDR0_34, laddr);
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mfsdram(DDR0_35, haddr);
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mfsdram(DDR0_36, ldata);
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mfsdram(DDR0_37, hdata);
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debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
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laddr, hdata, ldata, bit);
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ret = 6;
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}
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if (value & DDR0_00_INT_STATUS_BIT6) {
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debug("Bit6. DRAM initialization complete\n");
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ret = 7;
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}
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/* error status cleared */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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return ret;
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}
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static int test_ecc(unsigned long ecc_addr)
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{
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volatile unsigned long long *ecc_mem;
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unsigned long value;
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unsigned long ecc_data;
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volatile unsigned long *lecc_mem;
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int pret, ret = 0;
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sync();
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eieio();
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WATCHDOG_RESET();
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ecc_mem = (unsigned long long *)ecc_addr;
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lecc_mem = (ulong *)ecc_addr;
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*ecc_mem = ECC_PATTERN;
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pret = test_ecc_error();
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if (pret != 0)
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ret = 1;
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/* disconnect ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_DISABLE);
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/* injecting error */
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*ecc_mem = ECC_PATTERN_CORR;
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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ecc_data = *lecc_mem;
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pret = test_ecc_error();
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/* if read data ok, 1 correctable error must be fixed */
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if (pret != 3)
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ret = 1;
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/* test for uncorrectable error */
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/* disconnect from ecc storage */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_NO_ECC_RAM);
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/* injecting multiply bit error */
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*ecc_mem = ECC_PATTERN_UNCORR;
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/* enable ecc */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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ecc_data = *lecc_mem;
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/* what the data should be read? */
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pret = test_ecc_error();
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/* info about uncorrectable error must appear */
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if (pret != 5)
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ret = 1;
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sync();
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eieio();
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return ret;
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}
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int ecc_post_test (int flags)
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{
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int ret = 0;
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unsigned long value;
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unsigned long iaddr;
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#if CONFIG_DDR_ECC
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sync();
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eieio();
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/* mask all int */
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mfsdram(DDR0_01, value);
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mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK)
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| DDR0_01_INT_MASK_ALL_OFF);
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/* clear error status */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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/* enable full support of ECC */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) {
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ret = test_ecc(iaddr);
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if (ret)
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break;
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}
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#endif
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return ret;
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}
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#endif /* CONFIG_POST & CFG_POST_ECC */
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#endif /* CONFIG_POST */
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13
post/tests.c
13
post/tests.c
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@ -46,6 +46,7 @@ extern int spr_post_test (int flags);
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extern int sysmon_post_test (int flags);
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extern int dsp_post_test (int flags);
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extern int codec_post_test (int flags);
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extern int ecc_post_test (int flags);
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extern int sysmon_init_f (void);
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@ -236,6 +237,18 @@ struct post_test post_list[] =
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CFG_POST_CODEC
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},
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#endif
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#if CONFIG_POST & CFG_POST_ECC
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{
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"ECC test",
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"ecc",
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"This test checks ECC facility of memory.",
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POST_ROM | POST_ALWAYS,
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&ecc_post_test,
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NULL,
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NULL,
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CFG_POST_ECC
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},
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#endif
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};
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unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
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