* Patch by David Mller, 13 Sep 2003:
various changes to VCMA9 board specific files * Add I2C support for MGT5100 / MPC5200
This commit is contained in:
wdenk
parent
b70e7a00c8
commit
531716e171
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@ -2,6 +2,11 @@
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Changes for U-Boot 1.0.0:
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======================================================================
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* Patch by David Müller, 13 Sep 2003:
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various changes to VCMA9 board specific files
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* Add I2C support for MGT5100 / MPC5200
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* Patch by Rune Torgersen, 11 Sep 2003:
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Changed default memory option on MPC8266ADS to NOT be Page Based
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Interleave, since this doesn't work very well with the standard
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3
README
3
README
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@ -203,6 +203,7 @@ Directory Hierarchy:
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- board/mpl/common Common files for MPL boards
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- board/mpl/pip405 Files specific to PIP405 boards
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- board/mpl/mip405 Files specific to MIP405 boards
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- board/mpl/vcma9 Files specific to VCMA9 boards
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- board/musenki Files specific to MUSEKNI boards
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- board/mvs1 Files specific to MVS1 boards
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- board/nx823 Files specific to NX823 boards
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@ -363,7 +364,7 @@ The following options need to be configured:
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CONFIG_IMPA7, CONFIG_LART, CONFIG_LUBBOCK,
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CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610
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CONFIG_SHANNON, CONFIG_SMDK2400, CONFIG_SMDK2410,
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CONFIG_TRAB, CONFIG_AT91RM9200DK
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CONFIG_TRAB, CONFIG_VCMA9, CONFIG_AT91RM9200DK
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- CPU Module Type: (if CONFIG_COGENT is defined)
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@ -41,9 +41,12 @@ static uchar cs8900_chksum(ushort data)
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#endif
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extern void print_vcma9_info(void);
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extern int vcma9_cantest(void);
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extern int vcma9_cantest(int);
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extern int vcma9_nandtest(void);
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extern int vcma9_dactest(void);
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extern int vcma9_nanderase(void);
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extern int vcma9_nandread(ulong);
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extern int vcma9_nandwrite(ulong);
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extern int vcma9_dactest(int);
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extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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/* ------------------------------------------------------------------------- */
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@ -126,18 +129,53 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#endif
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#if 0
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if (strcmp(argv[1], "cantest") == 0) {
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vcma9_cantest();
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if (argc >= 3)
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vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
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else
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vcma9_cantest(0);
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return 0;
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}
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if (strcmp(argv[1], "nandtest") == 0) {
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vcma9_nandtest();
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return 0;
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}
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if (strcmp(argv[1], "nanderase") == 0) {
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vcma9_nanderase();
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return 0;
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}
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if (strcmp(argv[1], "nandread") == 0) {
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ulong offset = 0;
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if (argc >= 3)
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offset = simple_strtoul(argv[2], NULL, 16);
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vcma9_nandread(offset);
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return 0;
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}
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if (strcmp(argv[1], "nandwrite") == 0) {
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ulong offset = 0;
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if (argc >= 3)
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offset = simple_strtoul(argv[2], NULL, 16);
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vcma9_nandwrite(offset);
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return 0;
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}
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if (strcmp(argv[1], "dactest") == 0) {
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vcma9_dactest();
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if (argc >= 3)
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vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
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else
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vcma9_dactest(0);
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return 0;
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}
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#endif
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return (do_mplcommon(cmdtp, flag, argc, argv));
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}
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U_BOOT_CMD(
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vcma9, 6, 1, do_vcma9,
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"vcma9 - VCMA9 specific commands\n",
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"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
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);
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@ -1,5 +1,5 @@
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#
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# (C) Copyright 2002
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# (C) Copyright 2002, 2003
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# MPL VCMA9 board with S3C2410X (ARM920T) cpu
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@ -8,17 +8,17 @@
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#
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#
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# MPL VCMA9 has 1 bank of 64 MB DRAM
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#
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# 3000'0000 to 3400'0000
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# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
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# from 0x30000000
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#
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# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
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# optionally with a ramdisk at 3080'0000
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# optionally with a ramdisk at 3040'0000
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#
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# we load ourself to 33F8'0000
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# we load ourself to 30F8'0000
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#
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# download area is 3300'0000
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# download area is 3080'0000
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#
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#TEXT_BASE = 0x30F80000
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TEXT_BASE = 0x33F80000
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@ -34,7 +34,9 @@
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/* some parameters for the board */
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#define BWSCON 0x48000000
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#define BWSCON 0x48000000
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#define PLD_BASE 0x2C000000
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#define SDRAM_REG 0x2C000106
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/* BWSCON */
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#define DW8 (0x0)
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@ -43,6 +45,9 @@
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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/* BANKSIZE */
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#define BURST_EN (0x1<<7)
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#define B1_BWSCON (DW16)
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#define B2_BWSCON (DW32)
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#define B3_BWSCON (DW32)
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@ -130,24 +135,39 @@ memsetup:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r0, =CSDATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #13*4
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add r2, r0, #CSDATA_END-CSDATA
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* PLD access is now possible */
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/* r0 == SDRAMDATA */
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/* r1 == SDRAM controller regs */
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ldr r2, =PLD_BASE
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ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
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mov r4, #SDRAMDATA1_END-SDRAMDATA
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/* calculate start and end point */
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mla r0, r3, r4, r0
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add r2, r0, r4
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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CSDATA:
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
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@ -155,9 +175,38 @@ SMRDATA:
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
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CSDATA_END:
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SDRAMDATA:
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/* 4Mx8x4 */
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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SDRAMDATA1_END:
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/* 8Mx8x4 (not implemented yet) */
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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/* 2Mx8x4 (not implemented yet) */
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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/* 4Mx8x2 (not implemented yet) */
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32 + BURST_EN
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.word 0x30
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.word 0x30
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@ -130,16 +130,6 @@ int board_init(void)
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return 0;
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}
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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/*
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* NAND flash initialization.
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*/
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@ -162,9 +152,16 @@ static inline void NF_Reset(void)
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static inline void NF_Init(void)
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{
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#if 0 /* a little bit too optimistic */
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#define TACLS 0
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#define TWRPH0 3
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#define TWRPH1 0
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#else
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#define TACLS 0
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#define TWRPH0 4
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#define TWRPH1 2
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#endif
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NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
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/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
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/* 1 1 1 1, 1 xxx, r xxx, r xxx */
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@ -177,15 +174,12 @@ void
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nand_init(void)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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unsigned totlen;
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NF_Init();
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#ifdef DEBUG
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printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
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#endif
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totlen = nand_probe((ulong)nand) >> 20;
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printf ("%4lu MB\n", totlen >> 20);
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printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
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}
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#endif
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@ -193,29 +187,40 @@ nand_init(void)
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* Get some Board/PLD Info
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*/
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static uchar Get_PLD_ID(void)
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static u8 Get_PLD_ID(void)
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{
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return(*(volatile uchar *)PLD_ID_REG);
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VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
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return(pld->ID);
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}
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static uchar Get_PLD_BOARD(void)
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static u8 Get_PLD_BOARD(void)
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{
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return(*(volatile uchar *)PLD_BOARD_REG);
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VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
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return(pld->BOARD);
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}
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static uchar Get_PLD_Version(void)
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static u8 Get_PLD_SDRAM(void)
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{
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VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
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return(pld->SDRAM);
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}
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static u8 Get_PLD_Version(void)
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{
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return((Get_PLD_ID() >> 4) & 0x0F);
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}
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static uchar Get_PLD_Revision(void)
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static u8 Get_PLD_Revision(void)
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{
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return(Get_PLD_ID() & 0x0F);
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}
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static int Get_Board_Config(void)
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{
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uchar config = Get_PLD_BOARD() & 0x03;
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u8 config = Get_PLD_BOARD() & 0x03;
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if (config == 3)
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return 1;
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@ -228,6 +233,54 @@ static uchar Get_Board_PCB(void)
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return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
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}
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static u8 Get_SDRAM_ChipNr(void)
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{
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switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
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case 0: return 4;
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case 1: return 1;
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case 2: return 2;
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default: return 0;
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}
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}
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static ulong Get_SDRAM_ChipSize(void)
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{
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switch (Get_PLD_SDRAM() & 0x0F) {
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case 0: return 16 * (1024*1024);
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case 1: return 32 * (1024*1024);
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case 2: return 8 * (1024*1024);
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case 3: return 8 * (1024*1024);
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default: return 0;
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}
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}
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static const char * Get_SDRAM_ChipGeom(void)
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{
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switch (Get_PLD_SDRAM() & 0x0F) {
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case 0: return "4Mx8x4";
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case 1: return "8Mx8x4";
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case 2: return "2Mx8x4";
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case 3: return "4Mx8x2";
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default: return "unknown";
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}
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}
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static void Show_VCMA9_Info(char *board_name, char *serial)
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{
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printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
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board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
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printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
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}
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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@ -240,8 +293,6 @@ int checkboard(void)
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int i;
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backup_t *b = (backup_t *) s;
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puts("Board: ");
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i = getenv_r("serial#", s, 32);
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if ((i < 0) || strncmp (s, "VCMA9", 5)) {
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get_backup_values (b);
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@ -249,32 +300,23 @@ int checkboard(void)
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puts ("### No HW ID - assuming VCMA9");
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} else {
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b->serial_name[5] = 0;
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printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
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Get_Board_PCB(), &b->serial_name[6]);
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Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
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}
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} else {
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s[5] = 0;
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printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
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&s[6]);
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Show_VCMA9_Info(s, &s[6]);
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}
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printf("\n");
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/*printf("\n");*/
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return(0);
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}
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void print_vcma9_rev(void)
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{
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printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
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Get_Board_Config(), Get_Board_PCB(),
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Get_PLD_Version(), Get_PLD_Revision());
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}
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extern void mem_test_reloc(void);
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int last_stage_init(void)
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{
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mem_test_reloc();
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print_vcma9_rev();
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checkboard();
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show_stdio_dev();
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check_env();
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return 0;
|
||||
|
|
@ -295,6 +337,15 @@ int overwrite_console(void)
|
|||
* Print VCMA9 Info
|
||||
************************************************************************/
|
||||
void print_vcma9_info(void)
|
||||
{
|
||||
print_vcma9_rev();
|
||||
{
|
||||
unsigned char s[50];
|
||||
int i;
|
||||
|
||||
if ((i = getenv_r("serial#", s, 32)) < 0) {
|
||||
puts ("### No HW ID - assuming VCMA9");
|
||||
printf("i %d", i*24);
|
||||
} else {
|
||||
s[5] = 0;
|
||||
Show_VCMA9_Info(s, &s[6]);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* (C) Copyright 2002, 2003
|
||||
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -116,11 +116,19 @@ static inline u32 NF_Read_ECC(void)
|
|||
|
||||
#endif
|
||||
|
||||
/* VCMA9 PLD regsiters */
|
||||
typedef struct {
|
||||
S3C24X0_REG8 ID;
|
||||
S3C24X0_REG8 NIC;
|
||||
S3C24X0_REG8 CAN;
|
||||
S3C24X0_REG8 MISC;
|
||||
S3C24X0_REG8 GPCD;
|
||||
S3C24X0_REG8 BOARD;
|
||||
S3C24X0_REG8 SDRAM;
|
||||
} /*__attribute__((__packed__))*/ VCMA9_PLD;
|
||||
|
||||
#define PLD_BASE_ADDRESS 0x2C000100
|
||||
#define PLD_ID_REG (PLD_BASE_ADDRESS + 0)
|
||||
#define PLD_NIC_REG (PLD_BASE_ADDRESS + 1)
|
||||
#define PLD_CAN_REG (PLD_BASE_ADDRESS + 2)
|
||||
#define PLD_MISC_REG (PLD_BASE_ADDRESS + 3)
|
||||
#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4)
|
||||
#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5)
|
||||
#define VCMA9_PLD_BASE 0x2C000100
|
||||
static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
|
||||
{
|
||||
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ LIB = lib$(CPU).a
|
|||
|
||||
START = start.o
|
||||
ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
|
||||
OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
|
||||
OBJS = i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
|
||||
loadtask.o fec.o pci_mpc5200.o
|
||||
|
||||
all: .depend $(START) $(ASOBJS) $(LIB)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
#include <mpc5xxx.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#ifdef CFG_I2C_MODULE
|
||||
#define I2C_BASE MPC5XXX_I2C2
|
||||
#else
|
||||
#define I2C_BASE MPC5XXX_I2C1
|
||||
#endif
|
||||
|
||||
#define I2C_TIMEOUT 100
|
||||
#define I2C_RETRIES 3
|
||||
|
||||
static int mpc_reg_in (volatile u32 *reg);
|
||||
static void mpc_reg_out (volatile u32 *reg, int val, int mask);
|
||||
static int wait_for_bb (void);
|
||||
static int wait_for_pin (int *status);
|
||||
static int do_address (uchar chip, char rdwr_flag);
|
||||
static int send_bytes (uchar chip, char *buf, int len);
|
||||
static int receive_bytes (uchar chip, char *buf, int len);
|
||||
|
||||
static int mpc_reg_in(volatile u32 *reg)
|
||||
{
|
||||
return *reg >> 24;
|
||||
__asm__ __volatile__ ("eieio");
|
||||
}
|
||||
|
||||
static void mpc_reg_out(volatile u32 *reg, int val, int mask)
|
||||
{
|
||||
int tmp;
|
||||
|
||||
if (!mask) {
|
||||
*reg = val << 24;
|
||||
} else {
|
||||
tmp = mpc_reg_in(reg);
|
||||
*reg = ((tmp & ~mask) | (val & mask)) << 24;
|
||||
}
|
||||
__asm__ __volatile__ ("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int wait_for_bb(void)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
int status;
|
||||
|
||||
status = mpc_reg_in(®s->msr);
|
||||
|
||||
while (timeout-- && (status & I2C_BB)) {
|
||||
#if 1
|
||||
volatile int temp;
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
temp = mpc_reg_in(®s->mdr);
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
mpc_reg_out(®s->mcr, 0, 0);
|
||||
mpc_reg_out(®s->mcr, I2C_EN, 0);
|
||||
#endif
|
||||
udelay(1000);
|
||||
status = mpc_reg_in(®s->msr);
|
||||
}
|
||||
|
||||
return (status & I2C_BB);
|
||||
}
|
||||
|
||||
static int wait_for_pin(int *status)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
|
||||
*status = mpc_reg_in(®s->msr);
|
||||
|
||||
while (timeout-- && !(*status & I2C_IF)) {
|
||||
udelay(1000);
|
||||
*status = mpc_reg_in(®s->msr);
|
||||
}
|
||||
|
||||
if (!(*status & I2C_IF)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->msr, 0, I2C_IF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_address(uchar chip, char rdwr_flag)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int status;
|
||||
|
||||
chip <<= 1;
|
||||
|
||||
if (rdwr_flag) {
|
||||
chip |= 1;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_TX, I2C_TX);
|
||||
mpc_reg_out(®s->mdr, chip, 0);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -2;
|
||||
}
|
||||
|
||||
if (status & I2C_RXAK) {
|
||||
return -3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int send_bytes(uchar chip, char *buf, int len)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int wrcount;
|
||||
int status;
|
||||
|
||||
for (wrcount = 0; wrcount < len; ++wrcount) {
|
||||
|
||||
mpc_reg_out(®s->mdr, buf[wrcount], 0);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (status & I2C_RXAK) {
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return !(wrcount == len);
|
||||
}
|
||||
|
||||
static int receive_bytes(uchar chip, char *buf, int len)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int dummy = 1;
|
||||
int rdcount = 0;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_TX);
|
||||
|
||||
for (i = 0; i < len; ++i) {
|
||||
buf[rdcount] = mpc_reg_in(®s->mdr);
|
||||
|
||||
if (dummy) {
|
||||
dummy = 0;
|
||||
} else {
|
||||
rdcount++;
|
||||
}
|
||||
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -4;
|
||||
}
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK);
|
||||
buf[rdcount++] = mpc_reg_in(®s->mdr);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -5;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_TXAK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**************** I2C API ****************/
|
||||
|
||||
void i2c_init(int speed, int saddr)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, 0);
|
||||
mpc_reg_out(®s->madr, saddr << 1, 0);
|
||||
|
||||
/* Set clock
|
||||
*/
|
||||
mpc_reg_out(®s->mfdr, speed, 0);
|
||||
|
||||
/* Enable module
|
||||
*/
|
||||
mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
|
||||
mpc_reg_out(®s->msr, 0, I2C_IF);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < I2C_RETRIES; i++) {
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
|
||||
if (! do_address(chip, 0)) {
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
break;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
return (i == I2C_RETRIES);
|
||||
}
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb()) {
|
||||
printf("i2c_read: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address(chip, 0)) {
|
||||
printf("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, &xaddr[4-alen], alen)) {
|
||||
printf("i2c_read: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA);
|
||||
if (do_address(chip, 1)) {
|
||||
printf("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (receive_bytes(chip, buf, len)) {
|
||||
printf("i2c_read: receive_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb()) {
|
||||
printf("i2c_write: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address(chip, 0)) {
|
||||
printf("i2c_write: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, &xaddr[4-alen], alen)) {
|
||||
printf("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, buf, len)) {
|
||||
printf("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uchar i2c_reg_read(uchar chip, uchar reg)
|
||||
{
|
||||
char buf;
|
||||
|
||||
i2c_read(chip, reg, 1, &buf, 1);
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
void i2c_reg_write(uchar chip, uchar reg, uchar val)
|
||||
{
|
||||
i2c_write(chip, reg, 1, &val, 1);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
|
@ -83,7 +83,8 @@
|
|||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD)
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | CFG_CMD_EEPROM)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
|
@ -98,6 +99,23 @@
|
|||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_MODULE 1 /* If defined then I2C module #2 is used
|
||||
* otherwise I2C module #1 is used */
|
||||
#ifdef CONFIG_MPC5200
|
||||
#define CFG_I2C_SPEED 0x3D /* 86KHz given 133MHz IPBI */
|
||||
#else
|
||||
#define CFG_I2C_SPEED 0x35 /* 86KHz given 33MHz IPBI */
|
||||
#endif
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 35
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* (C) Copyright 2002, 2003
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* Gary Jennejohn <gj@denx.de>
|
||||
|
|
@ -160,9 +160,10 @@
|
|||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x33F80000 /* 63.5 MB in DRAM */
|
||||
#define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
|
||||
|
||||
#define CFG_ALT_MEMTEST
|
||||
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
|
||||
#define CFG_LOAD_ADDR 0x30800000 /* default load address */
|
||||
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
|
@ -197,8 +198,6 @@
|
|||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
|
|
|||
|
|
@ -108,6 +108,9 @@
|
|||
|
||||
#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
|
||||
|
||||
#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
|
||||
#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
|
||||
|
||||
#if defined(CONFIG_MGT5100)
|
||||
#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
|
||||
#define MPC5XXX_SRAM_SIZE (8*1024)
|
||||
|
|
@ -197,6 +200,24 @@
|
|||
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
|
||||
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
|
||||
|
||||
/* I2Cn control register bits */
|
||||
#define I2C_EN 0x80
|
||||
#define I2C_IEN 0x40
|
||||
#define I2C_STA 0x20
|
||||
#define I2C_TX 0x10
|
||||
#define I2C_TXAK 0x08
|
||||
#define I2C_RSTA 0x04
|
||||
#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
|
||||
|
||||
/* I2Cn status register bits */
|
||||
#define I2C_CF 0x80
|
||||
#define I2C_AAS 0x40
|
||||
#define I2C_BB 0x20
|
||||
#define I2C_AL 0x10
|
||||
#define I2C_SRW 0x04
|
||||
#define I2C_IF 0x02
|
||||
#define I2C_RXAK 0x01
|
||||
|
||||
/* Programmable Serial Controller (PSC) status register bits */
|
||||
#define PSC_SR_CDE 0x0080
|
||||
#define PSC_SR_RXRDY 0x0100
|
||||
|
|
@ -505,6 +526,14 @@ struct mpc5xxx_sdma {
|
|||
volatile u32 EU37; /* SDMA + 0xfc */
|
||||
};
|
||||
|
||||
struct mpc5xxx_i2c {
|
||||
volatile u32 madr; /* I2Cn + 0x00 */
|
||||
volatile u32 mfdr; /* I2Cn + 0x04 */
|
||||
volatile u32 mcr; /* I2Cn + 0x08 */
|
||||
volatile u32 msr; /* I2Cn + 0x0C */
|
||||
volatile u32 mdr; /* I2Cn + 0x10 */
|
||||
};
|
||||
|
||||
/* function prototypes */
|
||||
void loadtask(int basetask, int tasks);
|
||||
|
||||
|
|
|
|||
|
|
@ -80,13 +80,15 @@ void rtc_get (struct rtc_time *tmp)
|
|||
SetRTC_Access(RTC_ENABLE);
|
||||
|
||||
/* read RTC registers */
|
||||
sec = rtc->BCDSEC;
|
||||
min = rtc->BCDMIN;
|
||||
hour = rtc->BCDHOUR;
|
||||
mday = rtc->BCDDATE;
|
||||
wday = rtc->BCDDAY;
|
||||
mon = rtc->BCDMON;
|
||||
year = rtc->BCDYEAR;
|
||||
do {
|
||||
sec = rtc->BCDSEC;
|
||||
min = rtc->BCDMIN;
|
||||
hour = rtc->BCDHOUR;
|
||||
mday = rtc->BCDDATE;
|
||||
wday = rtc->BCDDAY;
|
||||
mon = rtc->BCDMON;
|
||||
year = rtc->BCDYEAR;
|
||||
} while (sec != rtc->BCDSEC);
|
||||
|
||||
/* read ALARM registers */
|
||||
a_sec = rtc->ALMSEC;
|
||||
|
|
@ -170,7 +172,7 @@ void rtc_reset (void)
|
|||
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
|
||||
|
||||
rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
|
||||
rtc->RTCCON &= ~0x08;
|
||||
rtc->RTCCON &= ~(0x08|0x01);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
|
|||
Loading…
Reference in New Issue