Patches by Robert Schwebel, 14 Jun 2003:
- add support for Logotronic DL datalogger board - cleanup serial line after kermit binary download - add debugX macro (debug level support) - update mach-types.h to latest arm.linux.org.uk master list.
This commit is contained in:
wdenk
parent
48b42616e9
commit
52f52c1494
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@ -2,6 +2,12 @@
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Changes since U-Boot 0.3.1:
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======================================================================
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* Patches by Robert Schwebel, 14 Jun 2003:
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- add support for Logotronic DL datalogger board
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- cleanup serial line after kermit binary download
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- add debugX macro (debug level support)
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- update mach-types.h to latest arm.linux.org.uk master list.
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* Patches by David Müller, 12 Jun 2003:
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- rewrite of the S3C24X0 register definitions stuff
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- "driver" for the built-in S3C24X0 RTC
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3
Makefile
3
Makefile
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@ -737,6 +737,9 @@ innokom_config : unconfig
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lubbock_config : unconfig
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@./mkconfig $(@:_config=) arm pxa lubbock
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logodl_config : unconfig
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@./mkconfig $(@:_config=) arm pxa logodl
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wepep250_config : unconfig
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@./mkconfig $(@:_config=) arm pxa wepep250
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15
README
15
README
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@ -2651,6 +2651,14 @@ Unix, I recommend to use C-Kermit for general purpose use (and
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especially for kermit binary protocol download ("loadb" command), and
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use "cu" for S-Record download ("loads" command).
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Nevertheless, if you absolutely want to use it try adding this
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configuration to your "File transfer protocols" section:
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Name Program Name U/D FullScr IO-Red. Multi
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X kermit /usr/bin/kermit -i -l %l -s Y U Y N N
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Y kermit /usr/bin/kermit -i -l %l -r N D Y N N
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NetBSD Notes:
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=============
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@ -3002,6 +3010,13 @@ it:
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We accept patches as plain text, MIME attachments or as uuencoded
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gzipped text.
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* If one logical set of modifications affects or creates several
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files, all these changes shall be submitted in a SINGLE patch file.
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* Changesets that contain different, unrelated modifications shall be
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submitted as SEPARATE patches, one patch per changeset.
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Notes:
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* Before sending the patch, run the MAKEALL script on your patched
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := logodl.o flash.o
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SOBJS := memsetup.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $^
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,15 @@
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#
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# Linux-Kernel is expected to be at c000'8000, entry c000'8000
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#
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# we load ourself to c170'0000, the upper 1 MB of second bank
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#
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# download areas is c800'0000
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#
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#TEXT_BASE = 0
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# FIXME: armboot does only work correctly when being compiled
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# # for the addresses _after_ relocation to RAM!! Otherwhise the
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# # .bss segment is assumed in flash...
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#
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TEXT_BASE = 0x083E0000
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@ -0,0 +1,844 @@
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/*
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* (C) 2000 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* (C) 2003 August Hoeraendl, Logotronic GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#undef CONFIG_FLASH_16BIT
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#include <common.h>
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#define FLASH_BANK_SIZE 0x1000000
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#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
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* has nothing to do with the flash chip being 8-bit or 16-bit.
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*/
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#ifdef CONFIG_FLASH_16BIT
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typedef unsigned short FLASH_PORT_WIDTH;
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typedef volatile unsigned short FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFFFF
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#else
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typedef unsigned long FLASH_PORT_WIDTH;
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typedef volatile unsigned long FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFFFFFFFF
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#endif
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define ORMASK(size) ((-size) & OR_AM_MSK)
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (FPWV * addr, flash_info_t * info);
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static void flash_reset (flash_info_t * info);
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static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data);
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static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
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#define write_word(in, de, da) write_word_amd(in, de, da)
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static void flash_get_offsets (ulong base, flash_info_t * info);
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#ifdef CFG_FLASH_PROTECTION
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static void flash_sync_real_protect (flash_info_t * info);
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#endif
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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ulong flash_init (void)
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{
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int i, j;
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ulong size = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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ulong flashbase = 0;
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flash_info[i].flash_id =
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(FLASH_MAN_AMD & FLASH_VENDMASK) |
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(FLASH_AM640U & FLASH_TYPEMASK);
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flash_info[i].size = FLASH_BANK_SIZE;
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
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memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
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switch (i) {
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case 0:
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flashbase = PHYS_FLASH_1;
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break;
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case 1:
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flashbase = PHYS_FLASH_2;
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break;
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default:
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panic ("configured to many flash banks!\n");
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break;
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}
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for (j = 0; j < flash_info[i].sector_count; j++) {
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flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
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}
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size += flash_info[i].size;
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}
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/* Protect monitor and environment sectors
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*/
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flash_protect (FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
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&flash_info[0]);
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_reset (flash_info_t * info)
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{
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FPWV *base = (FPWV *) (info->start[0]);
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/* Put FLASH back in read mode */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
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*base = (FPW) 0x00FF00FF; /* Intel Read Mode */
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
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*base = (FPW) 0x00F000F0; /* AMD Read Mode */
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t * info)
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{
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int i;
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/* set up sector start address table */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
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&& (info->flash_id & FLASH_BTYPE)) {
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int bootsect_size; /* number of bytes/boot sector */
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int sect_size; /* number of bytes/regular sector */
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bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
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sect_size = 0x00010000 * (sizeof (FPW) / 2);
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/* set sector offsets for bottom boot block type */
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for (i = 0; i < 8; ++i) {
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info->start[i] = base + (i * bootsect_size);
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}
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = base + ((i - 7) * sect_size);
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}
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} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
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&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
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int sect_size; /* number of bytes/sector */
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sect_size = 0x00010000 * (sizeof (FPW) / 2);
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/* set up sector start address table (uniform sector type) */
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * sect_size);
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t * info)
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{
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int i;
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uchar *boottype;
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uchar *bootletter;
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uchar *fmt;
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uchar botbootletter[] = "B";
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uchar topbootletter[] = "T";
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uchar botboottype[] = "bottom boot sector";
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uchar topboottype[] = "top boot sector";
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf ("AMD ");
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break;
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case FLASH_MAN_BM:
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printf ("BRIGHT MICRO ");
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break;
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case FLASH_MAN_FUJ:
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printf ("FUJITSU ");
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break;
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case FLASH_MAN_SST:
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printf ("SST ");
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break;
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case FLASH_MAN_STM:
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printf ("STM ");
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break;
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case FLASH_MAN_INTEL:
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printf ("INTEL ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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/* check for top or bottom boot, if it applies */
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if (info->flash_id & FLASH_BTYPE) {
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boottype = botboottype;
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bootletter = botbootletter;
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} else {
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boottype = topboottype;
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bootletter = topbootletter;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM640U:
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fmt = "29LV641D (64 Mbit, uniform sectors)\n";
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break;
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case FLASH_28F800C3B:
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case FLASH_28F800C3T:
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fmt = "28F800C3%s (8 Mbit, %s)\n";
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break;
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case FLASH_INTEL800B:
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case FLASH_INTEL800T:
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fmt = "28F800B3%s (8 Mbit, %s)\n";
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break;
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case FLASH_28F160C3B:
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case FLASH_28F160C3T:
|
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fmt = "28F160C3%s (16 Mbit, %s)\n";
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break;
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case FLASH_INTEL160B:
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case FLASH_INTEL160T:
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fmt = "28F160B3%s (16 Mbit, %s)\n";
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break;
|
||||
case FLASH_28F320C3B:
|
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case FLASH_28F320C3T:
|
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fmt = "28F320C3%s (32 Mbit, %s)\n";
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break;
|
||||
case FLASH_INTEL320B:
|
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case FLASH_INTEL320T:
|
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fmt = "28F320B3%s (32 Mbit, %s)\n";
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break;
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
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fmt = "28F640C3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_INTEL640T:
|
||||
fmt = "28F640B3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
default:
|
||||
fmt = "Unknown Chip Type\n";
|
||||
break;
|
||||
}
|
||||
|
||||
printf (fmt, bootletter, boottype);
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
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info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
ulong flash_get_size (FPWV * addr, flash_info_t * info)
|
||||
{
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
|
||||
addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
|
||||
addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */
|
||||
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width.
|
||||
*/
|
||||
switch (addr[0] & 0xff) {
|
||||
|
||||
case (uchar) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
|
||||
case (uchar) INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
|
||||
if (info->flash_id != FLASH_UNKNOWN)
|
||||
switch (addr[1]) {
|
||||
|
||||
case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F800C3B:
|
||||
info->flash_id += FLASH_28F800C3B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof (FPW) / 2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F800B3B:
|
||||
info->flash_id += FLASH_INTEL800B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof (FPW) / 2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F160C3B:
|
||||
info->flash_id += FLASH_28F160C3B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof (FPW) / 2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F160B3B:
|
||||
info->flash_id += FLASH_INTEL160B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof (FPW) / 2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F320C3B:
|
||||
info->flash_id += FLASH_28F320C3B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof (FPW) / 2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F320B3B:
|
||||
info->flash_id += FLASH_INTEL320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof (FPW) / 2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640C3B:
|
||||
info->flash_id += FLASH_28F640C3B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640B3B:
|
||||
info->flash_id += FLASH_INTEL640B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof (FPW) / 2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* => no or unknown flash */
|
||||
}
|
||||
|
||||
flash_get_offsets ((ulong) addr, info);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset (info);
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static void flash_sync_real_protect (flash_info_t * info)
|
||||
{
|
||||
FPWV *addr = (FPWV *) (info->start[0]);
|
||||
FPWV *sect;
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
/* check for protected sectors */
|
||||
*addr = (FPW) 0x00900090;
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected.
|
||||
* If at least one device is protected the sector is marked
|
||||
* protected, but mixed protected and unprotected devices
|
||||
* within a sector should never happen.
|
||||
*/
|
||||
sect = (FPWV *) (info->start[i]);
|
||||
info->protect[i] = (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset (info);
|
||||
break;
|
||||
|
||||
case FLASH_AM640U:
|
||||
default:
|
||||
/* no hardware protect that we support */
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
FPWV *addr;
|
||||
int flag, prot, sect;
|
||||
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
|
||||
ulong start, now, last;
|
||||
int rcode = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_INTEL800B:
|
||||
case FLASH_INTEL160B:
|
||||
case FLASH_INTEL320B:
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_AM640U:
|
||||
break;
|
||||
case FLASH_UNKNOWN:
|
||||
default:
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
|
||||
|
||||
if (info->protect[sect] != 0) /* protected, skip it */
|
||||
continue;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
addr = (FPWV *) (info->start[sect]);
|
||||
if (intel) {
|
||||
*addr = (FPW) 0x00500050; /* clear status register */
|
||||
*addr = (FPW) 0x00200020; /* erase setup */
|
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */
|
||||
} else {
|
||||
/* must be AMD style if not Intel */
|
||||
FPWV *base; /* first address in bank */
|
||||
|
||||
base = (FPWV *) (info->start[0]);
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
base[0x0555] = (FPW) 0x00800080; /* erase mode */
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
*addr = (FPW) 0x00300030; /* erase sector */
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 50us for AMD, 80us for Intel.
|
||||
* Let's wait 1 ms.
|
||||
*/
|
||||
udelay (1000);
|
||||
|
||||
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
|
||||
if (intel) {
|
||||
/* suspend erase */
|
||||
*addr = (FPW) 0x00B000B0;
|
||||
}
|
||||
|
||||
flash_reset (info); /* reset to read mode */
|
||||
rcode = 1; /* failed */
|
||||
break;
|
||||
}
|
||||
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
flash_reset (info); /* reset to read mode */
|
||||
}
|
||||
|
||||
printf (" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
FPW data = 0; /* 16 or 32 bit word, matches flash bus width */
|
||||
int bytes; /* number of bytes to program in current word */
|
||||
int left; /* number of bytes left to program */
|
||||
int i, res;
|
||||
|
||||
/* printf("write_buff: src: %8p addr %08lx count: %ld\n", src, addr, cnt); */
|
||||
|
||||
for (left = cnt, res = 0;
|
||||
left > 0 && res == 0;
|
||||
addr += sizeof (data), left -= sizeof (data) - bytes) {
|
||||
|
||||
bytes = addr & (sizeof (data) - 1);
|
||||
addr &= ~(sizeof (data) - 1);
|
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits
|
||||
*/
|
||||
for (i = 0; i < sizeof (data); i++) {
|
||||
data <<= 8;
|
||||
if (i < bytes || i - bytes >= left)
|
||||
data += *((uchar *) addr + i);
|
||||
else
|
||||
data += *src++;
|
||||
}
|
||||
|
||||
/* write one word to the flash */
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
res = write_word_amd (info, (FPWV *) addr, data);
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
res = write_word_intel (info, (FPWV *) addr, data);
|
||||
break;
|
||||
default:
|
||||
/* unknown flash type, error! */
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
res = 1; /* not really a timeout, but gives error */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/**
|
||||
* write_buf: - Copy memory to flash.
|
||||
*
|
||||
* @param info:
|
||||
* @param src: source of copy transaction
|
||||
* @param addr: where to copy to
|
||||
* @param cnt: number of bytes to copy
|
||||
*
|
||||
* @return error code
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
||||
FPW data;
|
||||
int l;
|
||||
int i, rc;
|
||||
|
||||
wp = (addr & ~1); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
for (; i < 2 && cnt > 0; ++i) {
|
||||
data = (data >> 8) | (*src++ << 8);
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < 2; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 2;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 2) {
|
||||
/* data = *((vushort*)src); */
|
||||
data = *((FPW *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += sizeof (FPW);
|
||||
wp += sizeof (FPW);
|
||||
cnt -= sizeof (FPW);
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return ERR_OK;
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
|
||||
data = (data >> 8) | (*src++ << 8);
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 2; ++i, ++cp) {
|
||||
data = (data >> 8) | (*(uchar *) cp << 8);
|
||||
}
|
||||
|
||||
return write_word (info, wp, data);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
FPWV *base; /* first address in flash bank */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
|
||||
base = (FPWV *) (info->start[0]);
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
|
||||
base[0x02AA] = (FPW) 0x00550055; /* unlock */
|
||||
base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
/* data polling for D7 */
|
||||
while (res == 0
|
||||
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW) 0x00F000F0; /* reset bank */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for Intel FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */
|
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
|
||||
*dest = (FPW) 0x00400040; /* program setup */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW) 0x00B000B0; /* Suspend program */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (res == 0 && (*dest & (FPW) 0x00100010))
|
||||
res = 1; /* write failed, time out error is close enough */
|
||||
|
||||
*dest = (FPW) 0x00500050; /* clear status register */
|
||||
*dest = (FPW) 0x00FF00FF; /* make sure in read mode */
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect (flash_info_t * info, long sector, int prot)
|
||||
{
|
||||
int rcode = 0; /* assume success */
|
||||
FPWV *addr; /* address of sector */
|
||||
FPW value;
|
||||
|
||||
addr = (FPWV *) (info->start[sector]);
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
flash_reset (info); /* make sure in read mode */
|
||||
*addr = (FPW) 0x00600060L; /* lock command setup */
|
||||
if (prot)
|
||||
*addr = (FPW) 0x00010001L; /* lock sector */
|
||||
else
|
||||
*addr = (FPW) 0x00D000D0L; /* unlock sector */
|
||||
flash_reset (info); /* reset to read mode */
|
||||
|
||||
/* now see if it really is locked/unlocked as requested */
|
||||
*addr = (FPW) 0x00900090;
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
||||
* D0 = 1 for each device if protected.
|
||||
* If at least one device is protected the sector is marked
|
||||
* protected, but return failure. Mixed protected and
|
||||
* unprotected devices within a sector should never happen.
|
||||
*/
|
||||
value = addr[2] & (FPW) 0x00010001;
|
||||
if (value == 0)
|
||||
info->protect[sector] = 0;
|
||||
else if (value == (FPW) 0x00010001)
|
||||
info->protect[sector] = 1;
|
||||
else {
|
||||
/* error, mixed protected and unprotected */
|
||||
rcode = 1;
|
||||
info->protect[sector] = 1;
|
||||
}
|
||||
if (info->protect[sector] != prot)
|
||||
rcode = 1; /* failed to protect/unprotect as requested */
|
||||
|
||||
/* reload all protection bits from hardware for now */
|
||||
flash_sync_real_protect (info);
|
||||
break;
|
||||
|
||||
case FLASH_AM640U:
|
||||
default:
|
||||
/* no hardware protect that we support */
|
||||
info->protect[sector] = prot;
|
||||
break;
|
||||
}
|
||||
|
||||
return rcode;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* (C) 2002 Kyle Harris <kharris@nexus-tech.net>, Nexus Technologies, Inc.
|
||||
* (C) 2002 Marius Groeger <mgroeger@sysgo.de>, Sysgo GmbH
|
||||
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
/**
|
||||
* board_init: - setup some data structures
|
||||
*
|
||||
* @return: 0 in case of success
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* memory and cpu-speed are setup before relocation */
|
||||
/* so we do _nothing_ here */
|
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_LOGODL;
|
||||
gd->bd->bi_boot_params = 0x08000100;
|
||||
gd->bd->bi_baudrate = CONFIG_BAUDRATE;
|
||||
|
||||
(*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */
|
||||
(*((volatile short*)0x14000000)) = 0xff; /* power on uart */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* dram_init: - setup dynamic RAM
|
||||
*
|
||||
* @return: 0 in case of success
|
||||
*/
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* logodl_set_led: - switch LEDs on or off
|
||||
*
|
||||
* @param led: LED to switch (0,1)
|
||||
* @param state: switch on (1) or off (0)
|
||||
*/
|
||||
|
||||
void logodl_set_led(int led, int state)
|
||||
{
|
||||
switch(led) {
|
||||
|
||||
case 0:
|
||||
if (state==1) {
|
||||
CFG_LED_A_CR = CFG_LED_A_BIT;
|
||||
} else if (state==0) {
|
||||
CFG_LED_A_SR = CFG_LED_A_BIT;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
if (state==1) {
|
||||
CFG_LED_B_CR = CFG_LED_B_BIT;
|
||||
} else if (state==0) {
|
||||
CFG_LED_B_SR = CFG_LED_B_BIT;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* show_boot_progress: - indicate state of the boot process
|
||||
*
|
||||
* @param status: Status number - see README for details.
|
||||
*
|
||||
* The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
|
||||
* important states (1, 5, 15).
|
||||
*/
|
||||
|
||||
void show_boot_progress (int status)
|
||||
{
|
||||
/*
|
||||
switch(status) {
|
||||
case 1: logodl_set_led(0,1); break;
|
||||
case 5: logodl_set_led(1,1); break;
|
||||
case 15: logodl_set_led(2,1); break;
|
||||
}
|
||||
*/
|
||||
logodl_set_led(0, (status & 1)==1);
|
||||
logodl_set_led(1, (status & 2)==2);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,438 @@
|
|||
/*
|
||||
* Most of this taken from Redboot hal_platform_setup.h with cleanup
|
||||
*
|
||||
* NOTE: I haven't clean this up considerably, just enough to get it
|
||||
* running. See hal_platform_setup.h for the source. See
|
||||
* board/cradle/memsetup.S for another PXA250 setup that is
|
||||
* much cleaner.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
DRAM_SIZE: .long CFG_DRAM_SIZE
|
||||
|
||||
/* wait for coprocessor write complete */
|
||||
.macro CPWAIT reg
|
||||
mrc p15,0,\reg,c2,c0,0
|
||||
mov \reg,\reg
|
||||
sub pc,pc,#4
|
||||
.endm
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
|
||||
/*
|
||||
* Memory setup
|
||||
*/
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* Set up GPIO pins first ----------------------------------------- */
|
||||
|
||||
ldr r0, =GPSR0
|
||||
ldr r1, =CFG_GPSR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPSR1
|
||||
ldr r1, =CFG_GPSR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPSR2
|
||||
ldr r1, =CFG_GPSR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR0
|
||||
ldr r1, =CFG_GPCR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR1
|
||||
ldr r1, =CFG_GPCR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR2
|
||||
ldr r1, =CFG_GPCR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR0
|
||||
ldr r1, =CFG_GPDR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR1
|
||||
ldr r1, =CFG_GPDR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR2
|
||||
ldr r1, =CFG_GPDR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR0_L
|
||||
ldr r1, =CFG_GAFR0_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR0_U
|
||||
ldr r1, =CFG_GAFR0_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR1_L
|
||||
ldr r1, =CFG_GAFR1_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR1_U
|
||||
ldr r1, =CFG_GAFR1_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR2_L
|
||||
ldr r1, =CFG_GAFR2_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR2_U
|
||||
ldr r1, =CFG_GAFR2_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =PSSR /* enable GPIO pins */
|
||||
ldr r1, =CFG_PSSR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
|
||||
/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
|
||||
/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
|
||||
/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
|
||||
/* */
|
||||
/* ldr r1, =LED_BLANK */
|
||||
/* mov r0, #0xFF */
|
||||
/* str r0, [r1] / turn on hex leds */
|
||||
/* */
|
||||
/*loop: */
|
||||
/* */
|
||||
/* ldr r0, =0xB0070001 */
|
||||
/* ldr r1, =_LED */
|
||||
/* str r0, [r1] / hex display */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Enable memory interface */
|
||||
/* */
|
||||
/* The sequence below is based on the recommended init steps */
|
||||
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
|
||||
/* Chapter 10. */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 1: Wait for at least 200 microsedonds to allow internal */
|
||||
/* clocks to settle. Only necessary after hard reset... */
|
||||
/* FIXME: can be optimized later */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
|
||||
/* so 0x300 should be plenty */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
mem_init:
|
||||
|
||||
ldr r1, =MEMC_BASE /* get memory controller base addr. */
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2a: Initialize Asynchronous static memory controller */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* MSC registers: timing, bus width, mem type */
|
||||
|
||||
/* MSC0: nCS(0,1) */
|
||||
ldr r2, =CFG_MSC0_VAL
|
||||
str r2, [r1, #MSC0_OFFSET]
|
||||
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
|
||||
/* that data latches */
|
||||
/* MSC1: nCS(2,3) */
|
||||
ldr r2, =CFG_MSC1_VAL
|
||||
str r2, [r1, #MSC1_OFFSET]
|
||||
ldr r2, [r1, #MSC1_OFFSET]
|
||||
|
||||
/* MSC2: nCS(4,5) */
|
||||
ldr r2, =CFG_MSC2_VAL
|
||||
str r2, [r1, #MSC2_OFFSET]
|
||||
ldr r2, [r1, #MSC2_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2b: Initialize Card Interface */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* MECR: Memory Expansion Card Register */
|
||||
ldr r2, =CFG_MECR_VAL
|
||||
str r2, [r1, #MECR_OFFSET]
|
||||
ldr r2, [r1, #MECR_OFFSET]
|
||||
|
||||
/* MCMEM0: Card Interface slot 0 timing */
|
||||
ldr r2, =CFG_MCMEM0_VAL
|
||||
str r2, [r1, #MCMEM0_OFFSET]
|
||||
ldr r2, [r1, #MCMEM0_OFFSET]
|
||||
|
||||
/* MCMEM1: Card Interface slot 1 timing */
|
||||
ldr r2, =CFG_MCMEM1_VAL
|
||||
str r2, [r1, #MCMEM1_OFFSET]
|
||||
ldr r2, [r1, #MCMEM1_OFFSET]
|
||||
|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
|
||||
ldr r2, =CFG_MCATT0_VAL
|
||||
str r2, [r1, #MCATT0_OFFSET]
|
||||
ldr r2, [r1, #MCATT0_OFFSET]
|
||||
|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
|
||||
ldr r2, =CFG_MCATT1_VAL
|
||||
str r2, [r1, #MCATT1_OFFSET]
|
||||
ldr r2, [r1, #MCATT1_OFFSET]
|
||||
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
|
||||
ldr r2, =CFG_MCIO0_VAL
|
||||
str r2, [r1, #MCIO0_OFFSET]
|
||||
ldr r2, [r1, #MCIO0_OFFSET]
|
||||
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
|
||||
ldr r2, =CFG_MCIO1_VAL
|
||||
str r2, [r1, #MCIO1_OFFSET]
|
||||
ldr r2, [r1, #MCIO1_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
|
||||
adr r3, mem_init /* r0 <- current position of code */
|
||||
ldr r2, =mem_init
|
||||
cmp r3, r2 /* skip init if in place */
|
||||
beq initirqs
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Before accessing MDREFR we need a valid DRI field, so we set */
|
||||
/* this to power on defaults + DRI field. */
|
||||
|
||||
ldr r3, =CFG_MDREFR_VAL
|
||||
ldr r2, =0xFFF
|
||||
and r3, r3, r2
|
||||
ldr r4, =0x03ca4000
|
||||
orr r4, r4, r3
|
||||
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits */
|
||||
|
||||
/* Write SXMRS to cause an MRS command to all enabled banks of */
|
||||
/* synchronous static memory. Note that SXLCR need not be written */
|
||||
/* at this time. */
|
||||
|
||||
/* FIXME: we use async mode for now */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 4: Initialize SDRAM */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Step 4a: assert MDREFR:K?RUN and configure */
|
||||
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
|
||||
|
||||
ldr r4, =CFG_MDREFR_VAL
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
/* Step 4b: de-assert MDREFR:SLFRSH. */
|
||||
|
||||
bic r4, r4, #(MDREFR_SLFRSH)
|
||||
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
|
||||
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
|
||||
|
||||
orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
|
||||
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
|
||||
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
|
||||
/* configure but not enable each SDRAM partition pair. */
|
||||
|
||||
ldr r4, =CFG_MDCNFG_VAL
|
||||
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
|
||||
|
||||
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
|
||||
ldr r4, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
|
||||
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
|
||||
/* 100..200 µsec. */
|
||||
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
|
||||
/* so 0x300 should be plenty */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
|
||||
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
|
||||
/* attempting non-burst read or write accesses to disabled */
|
||||
/* SDRAM, as commonly specified in the power up sequence */
|
||||
/* documented in SDRAM data sheets. The address(es) used */
|
||||
/* for this purpose must not be cacheable. */
|
||||
|
||||
/* There should 9 writes, since the first write doesn't */
|
||||
/* trigger a refresh cycle on PXA250. See Intel PXA250 and */
|
||||
/* PXA210 Processors Specification Update, */
|
||||
/* Jan 2003, Errata #116, page 30. */
|
||||
|
||||
|
||||
ldr r3, =CFG_DRAM_BASE
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
|
||||
/* Step 4g: Write MDCNFG with enable bits asserted */
|
||||
/* (MDCNFG:DEx set to 1). */
|
||||
|
||||
ldr r3, [r1, #MDCNFG_OFFSET]
|
||||
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
|
||||
str r3, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
/* Step 4h: Write MDMRS. */
|
||||
|
||||
ldr r2, =CFG_MDMRS_VAL
|
||||
str r2, [r1, #MDMRS_OFFSET]
|
||||
|
||||
|
||||
/* We are finished with Intel's memory controller initialisation */
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Disable (mask) all interrupts at interrupt controller */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
initirqs:
|
||||
|
||||
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
|
||||
ldr r2, =ICLR
|
||||
str r1, [r2]
|
||||
|
||||
ldr r2, =ICMR /* mask all interrupts at the controller */
|
||||
str r1, [r2]
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Clock initialisation */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
initclks:
|
||||
|
||||
/* Disable the peripheral clocks, and set the core clock frequency */
|
||||
/* (hard-coding at 398.12MHz for now). */
|
||||
|
||||
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
|
||||
/* Note: See label 'ENABLECLKS' for the re-enabling */
|
||||
ldr r1, =CKEN
|
||||
mov r2, #0
|
||||
str r2, [r1]
|
||||
|
||||
|
||||
/* default value in case no valid rotary switch setting is found */
|
||||
ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
|
||||
|
||||
/* ... and write the core clock config register */
|
||||
ldr r1, =CCCR
|
||||
str r2, [r1]
|
||||
|
||||
/* enable the 32Khz oscillator for RTC and PowerManager */
|
||||
/*
|
||||
ldr r1, =OSCC
|
||||
mov r2, #OSCC_OON
|
||||
str r2, [r1]
|
||||
*/
|
||||
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
|
||||
/* has settled. */
|
||||
60:
|
||||
ldr r2, [r1]
|
||||
ands r2, r2, #1
|
||||
beq 60b
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Save SDRAM size */
|
||||
ldr r1, =DRAM_SIZE
|
||||
str r8, [r1]
|
||||
|
||||
/* Interrupt init: Mask all interrupts */
|
||||
ldr r0, =ICMR /* enable no sources */
|
||||
mov r1, #0
|
||||
str r1, [r0]
|
||||
|
||||
/* FIXME */
|
||||
|
||||
#ifndef DEBUG
|
||||
/*Disable software and data breakpoints */
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
|
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/*Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* End memsetup */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
endmemsetup:
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/pxa/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
armboot_end_data = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
bss_end = .;
|
||||
|
||||
armboot_end = .;
|
||||
}
|
||||
|
|
@ -406,12 +406,13 @@ read_record (char *buf, ulong len)
|
|||
}
|
||||
|
||||
/* Check for the console hangup (if any different from serial) */
|
||||
|
||||
#ifdef CONFIG_PPC /* we don't have syscall_tbl anywhere else */
|
||||
if (syscall_tbl[SYSCALL_GETC] != serial_getc) {
|
||||
if (ctrlc()) {
|
||||
return (-1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* line too long - truncate */
|
||||
|
|
@ -691,11 +692,24 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
|
||||
static ulong load_serial_bin (ulong offset)
|
||||
{
|
||||
int size;
|
||||
int size, i;
|
||||
char buf[32];
|
||||
|
||||
set_kerm_bin_mode ((ulong *) offset);
|
||||
size = k_recv ();
|
||||
|
||||
/*
|
||||
* Gather any trailing characters (for instance, the ^D which
|
||||
* is sent by 'cu' after sending a file), and give the
|
||||
* box some time (100 * 1 ms)
|
||||
*/
|
||||
for (i=0; i<100; ++i) {
|
||||
if (serial_tstc()) {
|
||||
(void) serial_getc();
|
||||
}
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
flush_cache (offset, size);
|
||||
|
||||
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -64,8 +64,10 @@ typedef volatile unsigned char vu_char;
|
|||
|
||||
#ifdef DEBUG
|
||||
#define debug(fmt,args...) printf (fmt ,##args)
|
||||
#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args);
|
||||
#else
|
||||
#define debug(fmt,args...)
|
||||
#define debugX(level,fmt,args...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
typedef void (interrupt_handler_t)(void *);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
|
||||
*
|
||||
* Configuration for the Logotronic DL board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* include/configs/logodl.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start U-Boot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* for timer/console/ethernet */
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_FFUART 1 /* we use FFUART */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
/*#define CONFIG_MISC_INIT_R 1 / * we have a misc_init_r() function */
|
||||
#undef CONFIG_MISC_INIT_R /* FIXME */
|
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
|
||||
/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,19200"
|
||||
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.1.56
|
||||
#define CONFIG_SERVERIP 192.168.1.2
|
||||
#define CONFIG_BOOTCOMMAND "bootm 0x40000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
/*
|
||||
* Size of malloc() pool; this lives below the uppermost 128 KiB which are
|
||||
* used for the RAM copy of the uboot code
|
||||
*
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (256*1024)
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x08000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
/* RS: the oscillator is actually 3680130?? */
|
||||
|
||||
#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
|
||||
/* 0101000001 */
|
||||
/* ^^^^^ Memory Speed 99.53 MHz */
|
||||
/* ^^ Run Mode Speed = 2x Mem Speed */
|
||||
/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* SMSC91C111 Network Card
|
||||
*/
|
||||
/*#define CONFIG_DRIVER_SMC91111 1 */
|
||||
/*#define CONFIG_SMC91111_BASE 0x10000000 / * chip select 4 */
|
||||
/*#undef CONFIG_SMC_USE_32_BIT / * 16 bit bus access */
|
||||
/*#undef CONFIG_SMC_91111_EXT_PHY / * we use internal phy */
|
||||
/*#undef CONFIG_SHOW_ACTIVITY */
|
||||
/*#define CONFIG_NET_RETRY_COUNT 10 / * # of retries */
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
|
||||
#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
|
||||
|
||||
#define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
|
||||
#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*
|
||||
* GP?? == FOOBAR is 0/1
|
||||
*/
|
||||
|
||||
#define _BIT0 0x00000001
|
||||
#define _BIT1 0x00000002
|
||||
#define _BIT2 0x00000004
|
||||
#define _BIT3 0x00000008
|
||||
|
||||
#define _BIT4 0x00000010
|
||||
#define _BIT5 0x00000020
|
||||
#define _BIT6 0x00000040
|
||||
#define _BIT7 0x00000080
|
||||
|
||||
#define _BIT8 0x00000100
|
||||
#define _BIT9 0x00000200
|
||||
#define _BIT10 0x00000400
|
||||
#define _BIT11 0x00000800
|
||||
|
||||
#define _BIT12 0x00001000
|
||||
#define _BIT13 0x00002000
|
||||
#define _BIT14 0x00004000
|
||||
#define _BIT15 0x00008000
|
||||
|
||||
#define _BIT16 0x00010000
|
||||
#define _BIT17 0x00020000
|
||||
#define _BIT18 0x00040000
|
||||
#define _BIT19 0x00080000
|
||||
|
||||
#define _BIT20 0x00100000
|
||||
#define _BIT21 0x00200000
|
||||
#define _BIT22 0x00400000
|
||||
#define _BIT23 0x00800000
|
||||
|
||||
#define _BIT24 0x01000000
|
||||
#define _BIT25 0x02000000
|
||||
#define _BIT26 0x04000000
|
||||
#define _BIT27 0x08000000
|
||||
|
||||
#define _BIT28 0x10000000
|
||||
#define _BIT29 0x20000000
|
||||
#define _BIT30 0x40000000
|
||||
#define _BIT31 0x80000000
|
||||
|
||||
|
||||
#define CFG_LED_A_BIT (_BIT18)
|
||||
#define CFG_LED_A_SR GPSR0
|
||||
#define CFG_LED_A_CR GPCR0
|
||||
|
||||
#define CFG_LED_B_BIT (_BIT16)
|
||||
#define CFG_LED_B_SR GPSR1
|
||||
#define CFG_LED_B_CR GPCR1
|
||||
|
||||
|
||||
/* LED A: off, LED B: off */
|
||||
#define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
|
||||
#define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
|
||||
#define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
|
||||
|
||||
#define CFG_GPCR0_VAL 0x00000000
|
||||
#define CFG_GPCR1_VAL 0x00000000
|
||||
#define CFG_GPCR2_VAL 0x00000000
|
||||
|
||||
#define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
|
||||
#define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
|
||||
#define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
|
||||
|
||||
#define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
|
||||
#define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
|
||||
_BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
|
||||
#define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
|
||||
_BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
|
||||
#define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
|
||||
#define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
|
||||
_BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
|
||||
#define CFG_GAFR2_U_VAL (_BIT1)
|
||||
|
||||
#define CFG_PSSR_VAL (0x20)
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
#define CFG_MSC0_VAL 0x123c2980
|
||||
#define CFG_MSC1_VAL 0x123c2661
|
||||
#define CFG_MSC2_VAL 0x7ff87ff8
|
||||
|
||||
|
||||
/* no sdram/pcmcia here */
|
||||
#define CFG_MDCNFG_VAL 0x00000000
|
||||
#define CFG_MDREFR_VAL 0x00000000
|
||||
#define CFG_MDREFR_VAL_100 0x00000000
|
||||
#define CFG_MDMRS_VAL 0x00000000
|
||||
|
||||
/* only SRAM */
|
||||
#define SXCNFG_SETTINGS 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
|
||||
#define CFG_MECR_VAL 0x00000000
|
||||
#define CFG_MCMEM0_VAL 0x00010504
|
||||
#define CFG_MCMEM1_VAL 0x00010504
|
||||
#define CFG_MCATT0_VAL 0x00010504
|
||||
#define CFG_MCATT1_VAL 0x00010504
|
||||
#define CFG_MCIO0_VAL 0x00004715
|
||||
#define CFG_MCIO1_VAL 0x00004715
|
||||
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/* FIXME */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue