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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

This commit is contained in:
Stefan Roese 2008-09-22 15:26:49 +02:00
parent 023824549a 3a9a000d9f
commit 5289feadb7
35 changed files with 459 additions and 1081 deletions
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30
CHANGELOG
View File

@ -1,3 +1,33 @@
commit 7c803be2eb3cae245dedda438776e08fb122250f
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Sep 16 18:02:19 2008 +0200
TQM8xx: Fix CFI flash driver support for all TQM8xx based boards
After switching to using the CFI flash driver, the correct remapping
of the flash banks was forgotten.
Also, some boards were not adapted, and the old legacy flash driver
was not removed yet.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c0d2f87d6c450128b88e73eea715fa3654f65b6c
Author: Wolfgang Denk <wd@denx.de>
Date: Sun Sep 14 00:59:35 2008 +0200
Prepare v2008.10-rc2
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit f12e4549b6fb01cd2654348af95a3c7a6ac161e7
Author: Wolfgang Denk <wd@denx.de>
Date: Sat Sep 13 02:23:05 2008 +0200
Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 0c32565f536609d78feef35c88bbc39d3ac53a73
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Wed Sep 10 09:18:34 2008 -0500

56
board/ms7722se/lowlevel_init.S
View File

@ -43,48 +43,61 @@
lowlevel_init:
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D, r0 ! Instruction Cache Invalidate
/* Address of Cache Control Register */
mov.l CCR_A, r1
/*Instruction Cache Invalidate */
mov.l CCR_D, r0
mov.l r0, @r1
mov.l MMUCR_A, r1 ! Address of MMU Control Register
mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
/* Address of MMU Control Register */
mov.l MMUCR_A, r1
/* TI == TLB Invalidate bit */
mov.l MMUCR_D, r0
mov.l r0, @r1
mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
mov.l MSTPCR0_D, r0 !
/* Address of Power Control Register 0 */
mov.l MSTPCR0_A, r1
mov.l MSTPCR0_D, r0
mov.l r0, @r1
mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
mov.l MSTPCR2_D, r0 !
/* Address of Power Control Register 2 */
mov.l MSTPCR2_A, r1
mov.l MSTPCR2_D, r0
mov.l r0, @r1
mov.l SBSCR_A, r1 !
mov.w SBSCR_D, r0 !
mov.l SBSCR_A, r1
mov.w SBSCR_D, r0
mov.w r0, @r1
mov.l PSCR_A, r1 !
mov.w PSCR_D, r0 !
mov.l PSCR_A, r1
mov.w PSCR_D, r0
mov.w r0, @r1
! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
/* 0xA4520004 (Watchdog Control / Status Register) */
! mov.l RWTCSR_A, r1
/* 0xA507 -> timer_STOP/WDT_CLK=max */
! mov.w RWTCSR_D_1, r0
! mov.w r0, @r1
mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
/* 0xA4520000 (Watchdog Count Register) */
mov.l RWTCNT_A, r1
/*0x5A00 -> Clear */
mov.w RWTCNT_D, r0
mov.w r0, @r1
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
/* 0xA4520004 (Watchdog Control / Status Register) */
mov.l RWTCSR_A, r1
/* 0xA504 -> timer_STOP/CLK=500ms */
mov.w RWTCSR_D_2, r0
mov.w r0, @r1
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
/* 0xA4150000 Frequency control register */
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0 !
mov.l r0, @r1
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D_2, r0 ! ??
mov.l CCR_A, r1
mov.l CCR_D_2, r0
mov.l r0, @r1
bsc_init:
@ -290,5 +303,6 @@ PSCR_D: .word 0x0000
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
SR_MASK_D: .long 0xEFFFFF0F

3
board/r7780mp/lowlevel_init.S
View File

@ -325,8 +325,9 @@ repeat2:
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
BBG_PMMR_A: .long 0xFF800010
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C

21
board/rsk7203/rsk7203.c
View File

@ -48,3 +48,24 @@ int dram_init(void)
void led_set_state(unsigned short value)
{
}
/*
* The RSK board has the SMSC9118 wired up 'incorrectly'.
* Byte-swapping is necessary, and so poor performance is inevitable.
* This problem cannot evade by the swap function of CHIP, this can
* evade by software Byte-swapping.
* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
* functions necessary to solve this problem.
*/
u32 pkt_data_pull(u32 addr)
{
volatile u16 *addr_16 = (u16 *)addr;
return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
| swab16(*(addr_16 + 1));
}
void pkt_data_push(u32 addr, u32 val)
{
*(volatile u16 *)(addr + 2) = swab16((u16)val);
*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
}

4
board/sh7785lcr/selfcheck.c
View File

@ -84,7 +84,7 @@ static void test_net(void)
if (data == 0x816910ec)
printf("Ethernet OK\n");
else
printf("Ethernet NG, data = %08x\n", data);
printf("Ethernet NG, data = %08x\n", (unsigned int)data);
}
static void test_sata(void)
@ -96,7 +96,7 @@ static void test_sata(void)
if (data == 0x35121095)
printf("SATA OK\n");
else
printf("SATA NG, data = %08x\n", data);
printf("SATA NG, data = %08x\n", (unsigned int)data);
}
static void test_pci(void)

2
board/tqc/tqm8xx/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o load_sernum_ethaddr.o
COBJS = $(BOARD).o load_sernum_ethaddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

834
board/tqc/tqm8xx/flash.c
View File

@ -1,834 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#if 0
#define DEBUG
#endif
#include <common.h>
#include <mpc8xx.h>
#include <environment.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
&& !defined(CONFIG_TQM885D)
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
# endif
#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0, size_b1;
int i;
#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
int scy, trlx, flash_or_timing, clk_diff;
scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
trlx = OR_TRLX;
scy *= 2;
} else
trlx = 0;
/* We assume that each 10MHz of bus clock require 1-clk SCY
* adjustment.
*/
clk_diff = (gd->bus_clk / 1000000) - 50;
/* We need proper rounding here. This is what the "+5" and "-5"
* are here for.
*/
if (clk_diff >= 0)
scy += (clk_diff + 5) / 10;
else
scy += (clk_diff - 5) / 10;
/* For bus frequencies above 50MHz, we want to use relaxed timing
* (OR_TRLX).
*/
if (gd->bus_clk >= 50000000)
trlx = OR_TRLX;
else
trlx = 0;
if (trlx)
scy /= 2;
if (scy > 0xf)
scy = 0xf;
if (scy < 1)
scy = 1;
flash_or_timing = (scy << 4) | trlx |
(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
#endif
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
if (size_b1 > size_b0) {
printf ("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,
size_b0, size_b0<<20
);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
flash_info[1].sector_count = -1;
flash_info[0].size = 0;
flash_info[1].size = 0;
return (0);
}
debug ("## Before remap: "
"BR0: 0x%08x OR0: 0x%08x "
"BR1: 0x%08x OR1: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0,
memctl->memc_br1, memctl->memc_or1);
/* Remap FLASH according to real size */
#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
#else
memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
#endif
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
debug ("Protect monitor: %08lx ... %08lx\n",
(ulong)CFG_MONITOR_BASE,
(ulong)CFG_MONITOR_BASE + monitor_flash_len - 1);
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
# ifdef CONFIG_ENV_ADDR_REDUND
debug ("Protect primary environment: %08lx ... %08lx\n",
(ulong)CONFIG_ENV_ADDR,
(ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1);
# else
debug ("Protect environment: %08lx ... %08lx\n",
(ulong)CONFIG_ENV_ADDR,
(ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1);
# endif
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
#ifdef CONFIG_ENV_ADDR_REDUND
debug ("Protect redundand environment: %08lx ... %08lx\n",
(ulong)CONFIG_ENV_ADDR_REDUND,
(ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1);
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
if (size_b1) {
#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
#else
memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
#endif
memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
BR_MS_GPCM | BR_V;
debug ("## BR1: 0x%08x OR1: 0x%08x\n",
memctl->memc_br1, memctl->memc_or1);
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
&flash_info[1]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[1]);
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
&flash_info[1]);
#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
flash_info[1].size = 0;
debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
memctl->memc_br1, memctl->memc_or1);
}
debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
#ifdef CONFIG_TQM8xxM /* mirror bit flash */
case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
break;
case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
break;
case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
break;
case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
break;
# else /* ! TQM8xxM */
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
#endif /* TQM8xxM */
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
ulong value;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00900090;
value = addr[0];
debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
switch (value) {
case AMD_MANUFACT:
debug ("Manufacturer: AMD\n");
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
debug ("Manufacturer: FUJITSU\n");
info->flash_id = FLASH_MAN_FUJ;
break;
default:
debug ("Manufacturer: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
switch (value) {
#ifdef CONFIG_TQM8xxM /* mirror bit flash */
case AMD_ID_MIRROR:
debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
addr[14], addr[15]);
/* Special case for AMLV320MH/L */
if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
(addr[15] & 0x00ff00ff) == 0x00000000) {
debug ("Chip: AMLV320MH/L\n");
info->flash_id += FLASH_AMLV320U;
info->sector_count = 64;
info->size = 0x00800000; /* => 8 MB */
break;
}
switch(addr[14]) {
case AMD_ID_LV128U_2:
if (addr[15] != AMD_ID_LV128U_3) {
debug ("Chip: AMLV128U -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
} else {
debug ("Chip: AMLV128U\n");
info->flash_id += FLASH_AMLV128U;
info->sector_count = 256;
info->size = 0x02000000;
}
break; /* => 32 MB */
case AMD_ID_LV640U_2:
if (addr[15] != AMD_ID_LV640U_3) {
debug ("Chip: AMLV640U -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
} else {
debug ("Chip: AMLV640U\n");
info->flash_id += FLASH_AMLV640U;
info->sector_count = 128;
info->size = 0x01000000;
}
break; /* => 16 MB */
case AMD_ID_LV320B_2:
if (addr[15] != AMD_ID_LV320B_3) {
debug ("Chip: AMLV320B -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
} else {
debug ("Chip: AMLV320B\n");
info->flash_id += FLASH_AMLV320B;
info->sector_count = 71;
info->size = 0x00800000;
}
break; /* => 8 MB */
default:
debug ("Chip: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
break;
}
break;
# else /* ! TQM8xxM */
case AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00800000;
break; /* => 8 MB */
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00800000;
break; /* => 8 MB */
#endif /* TQM8xxM */
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_DL163B:
info->flash_id += FLASH_AMDL163B;
info->sector_count = 39;
info->size = 0x00400000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
switch (value) {
#ifdef CONFIG_TQM8xxM /* mirror bit flash */
case AMD_ID_MIRROR:
switch (info->flash_id & FLASH_TYPEMASK) {
/* only known types here - no default */
case FLASH_AMLV128U:
case FLASH_AMLV640U:
case FLASH_AMLV320U:
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += 0x20000;
}
break;
case FLASH_AMLV320B:
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
/*
* The first 8 sectors are 8 kB,
* all the other ones are 64 kB
*/
base += (i < 8)
? 2 * ( 8 << 10)
: 2 * (64 << 10);
}
break;
}
break;
# else /* ! TQM8xxM */
case AMD_ID_LV400B:
case AMD_ID_LV800B:
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
}
break;
case AMD_ID_LV400T:
case AMD_ID_LV800T:
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
info->start[i--] = base + info->size - 0x00010000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00020000;
}
break;
case AMD_ID_LV320B:
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
/*
* The first 8 sectors are 8 kB,
* all the other ones are 64 kB
*/
base += (i < 8)
? 2 * ( 8 << 10)
: 2 * (64 << 10);
}
break;
case AMD_ID_LV320T:
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
/*
* The last 8 sectors are 8 kB,
* all the other ones are 64 kB
*/
base += (i < (info->sector_count - 8))
? 2 * (64 << 10)
: 2 * ( 8 << 10);
}
break;
#endif /* TQM8xxM */
case AMD_ID_LV160B:
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
}
break;
case AMD_ID_LV160T:
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
info->start[i--] = base + info->size - 0x00010000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00020000;
}
break;
case AMD_ID_DL163B:
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
/*
* The first 8 sectors are 8 kB,
* all the other ones are 64 kB
*/
base += (i < 8)
? 2 * ( 8 << 10)
: 2 * (64 << 10);
}
break;
default:
return (0);
break;
}
#if 0
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
#endif
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *)info->start[0];
*addr = 0x00F000F0; /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00800080;
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long*)(info->start[sect]);
addr[0] = 0x00300030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
while ((addr[0] & 0x00800080) != 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned long *)info->start[0];
addr[0] = 0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00A000A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/
#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */

131
board/tqc/tqm8xx/tqm8xx.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2006
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -21,16 +21,14 @@
* MA 02111-1307 USA
*/
#if 0
#define DEBUG
#endif
#include <common.h>
#include <mpc8xx.h>
#ifdef CONFIG_PS2MULT
#include <ps2mult.h>
#endif
extern flash_info_t flash_info[]; /* FLASH chips info */
DECLARE_GLOBAL_DATA_PTR;
static long int dram_size (long int, long int *, long int);
@ -402,8 +400,6 @@ phys_size_t initdram (int board_type)
memctl->memc_or5 = CFG_OR5_ISP1362;
memctl->memc_br5 = CFG_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
return (size_b0 + size_b1);
}
@ -451,24 +447,112 @@ int board_early_init_r (void)
#endif /* CONFIG_PS2MULT */
/* ---------------------------------------------------------------------------- */
/* HMI10 specific stuff */
/* ---------------------------------------------------------------------------- */
#ifdef CONFIG_HMI10
#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
# ifdef CONFIG_IDE_LED
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
int scy, trlx, flash_or_timing, clk_diff;
scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
trlx = OR_TRLX;
scy *= 2;
} else {
trlx = 0;
}
/*
* We assume that each 10MHz of bus clock require 1-clk SCY
* adjustment.
*/
clk_diff = (gd->bus_clk / 1000000) - 50;
/*
* We need proper rounding here. This is what the "+5" and "-5"
* are here for.
*/
if (clk_diff >= 0)
scy += (clk_diff + 5) / 10;
else
scy += (clk_diff - 5) / 10;
/*
* For bus frequencies above 50MHz, we want to use relaxed timing
* (OR_TRLX).
*/
if (gd->bus_clk >= 50000000)
trlx = OR_TRLX;
else
trlx = 0;
if (trlx)
scy /= 2;
if (scy > 0xf)
scy = 0xf;
if (scy < 1)
scy = 1;
flash_or_timing = (scy << 4) | trlx |
(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
memctl->memc_or0 =
flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
#else
memctl->memc_or0 =
CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
#endif
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
if (flash_info[1].size) {
#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
memctl->memc_or1 = flash_or_timing |
(-flash_info[1].size & 0xFFFF8000);
#else
memctl->memc_or1 = CFG_OR_TIMING_FLASH |
(-flash_info[1].size & 0xFFFF8000);
#endif
memctl->memc_br1 =
((CFG_FLASH_BASE +
flash_info[0].
size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
debug ("## BR1: 0x%08x OR1: 0x%08x\n",
memctl->memc_br1, memctl->memc_or1);
} else {
memctl->memc_br1 = 0; /* invalidate bank */
debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
memctl->memc_br1, memctl->memc_or1);
}
# ifdef CONFIG_IDE_LED
/* Configure PA15 as output port */
immap->im_ioport.iop_padir |= 0x0001;
immap->im_ioport.iop_paodr |= 0x0001;
immap->im_ioport.iop_papar &= ~0x0001;
immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
# endif
#ifdef CONFIG_NSCU
/* wake up ethernet module */
immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
immap->im_ioport.iop_pcdir |= 0x0004; /* output */
immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
#endif /* CONFIG_NSCU */
return (0);
}
#endif /* CONFIG_MISC_INIT_R */
# ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
@ -483,26 +567,6 @@ void ide_led (uchar led, uchar status)
}
}
# endif
#endif /* CONFIG_HMI10 */
/* ---------------------------------------------------------------------------- */
/* NSCU specific stuff */
/* ---------------------------------------------------------------------------- */
#ifdef CONFIG_NSCU
int misc_init_r (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* wake up ethernet module */
immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
immr->im_ioport.iop_pcdir |= 0x0004; /* output */
immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
return (0);
}
#endif /* CONFIG_NSCU */
/* ---------------------------------------------------------------------------- */
/* TK885D specific initializaion */
@ -548,7 +612,4 @@ int last_stage_init(void)
return 0;
}
#endif
/* ------------------------------------------------------------------------- */

71
cpu/sh4/watchdog.c
View File

@ -17,34 +17,55 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#define WDT_BASE WTCNT
static unsigned char cnt_read (void){
return *((volatile unsigned char *)(WDT_BASE + 0x00));
}
#define WDT_WD (1 << 6)
#define WDT_RST_P (0)
#define WDT_RST_M (1 << 5)
#define WDT_ENABLE (1 << 7)
static unsigned char csr_read (void){
return *((volatile unsigned char *)(WDT_BASE + 0x04));
}
static void cnt_write (unsigned char value){
while (csr_read() & (1 << 5)) {
/* delay */
}
*((volatile unsigned short *)(WDT_BASE + 0x00))
= ((unsigned short) value) | 0x5A00;
}
static void csr_write (unsigned char value){
*((volatile unsigned short *)(WDT_BASE + 0x04))
= ((unsigned short) value) | 0xA500;
}
int watchdog_init (void){ return 0; }
void reset_cpu (unsigned long ignored)
#if defined(CONFIG_WATCHDOG)
static unsigned char csr_read(void)
{
while(1);
return inb(WDT_BASE + 0x04);
}
static void cnt_write(unsigned char value)
{
outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
}
static void csr_write(unsigned char value)
{
outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
}
void watchdog_reset(void)
{
outl(0x55000000, WDT_BASE + 0x08);
}
int watchdog_init(void)
{
/* Set overflow time*/
cnt_write(0);
/* Power on reset */
csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
return 0;
}
int watchdog_disable(void)
{
csr_write(csr_read() & ~WDT_ENABLE);
return 0;
}
#endif
void reset_cpu(unsigned long ignored)
{
while (1)
;
}

8
drivers/net/tsec.c
View File

@ -283,11 +283,13 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
{
tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA,
/* Access TBI PHY registers at given TSEC register offset as opposed to the
* register offset used for external PHY accesses */
tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
TBIANA_SETTINGS);
tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON,
tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR,
tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
TBICR_SETTINGS);
}

24
drivers/pci/pci_sh7751.c
View File

@ -23,18 +23,19 @@
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <asm/pci.h>
/* Register addresses and such */
#define SH7751_BCR1 (vu_long *)0xFF800000
#define SH7751_BCR2 (vu_short*)0xFF800004
#define SH7751_BCR2 (vu_short *)0xFF800004
#define SH7751_WCR1 (vu_long *)0xFF800008
#define SH7751_WCR2 (vu_long *)0xFF80000C
#define SH7751_WCR3 (vu_long *)0xFF800010
#define SH7751_MCR (vu_long *)0xFF800014
#define SH7751_BCR3 (vu_short*)0xFF800050
#define SH7751_BCR3 (vu_short *)0xFF800050
#define SH7751_PCICONF0 (vu_long *)0xFE200000
#define SH7751_PCICONF1 (vu_long *)0xFE200004
#define SH7751_PCICONF2 (vu_long *)0xFE200008
@ -87,12 +88,12 @@
#define SH7751_PCIPAR (vu_long *)0xFE2001C0
#define SH7751_PCIPDR (vu_long *)0xFE200220
#define p4_in(addr) *(addr)
#define p4_out(data,addr) *(addr) = (data)
#define p4_in(addr) (*addr)
#define p4_out(data, addr) (*addr) = (data)
/* Double word */
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = 0x80000000 | dev;
@ -103,7 +104,7 @@ int pci_sh4_read_config_dword(struct pci_controller *hose,
}
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
pci_dev_t dev, int offset, u32 value)
{
u32 par_data = 0x80000000 | dev;
@ -126,15 +127,18 @@ int pci_sh7751_init(struct pci_controller *hose)
/* Double-check some BSC config settings */
/* (Area 3 non-MPX 32-bit, PCI bus pins) */
if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
printf("SH7751_BCR1 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR1));
return 2;
}
if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
printf("SH7751_BCR2 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR2));
return 3;
}
if (p4_in(SH7751_BCR2) & 0x01) {
printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
printf("SH7751_BCR2 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR2));
return 4;
}

17
drivers/pci/pci_sh7780.c
View File

@ -25,9 +25,10 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/pci.h>
#include <asm/io.h>
#define SH7780_VENDOR_ID 0x1912
#define SH7780_DEVICE_ID 0x0002
@ -41,10 +42,10 @@
#define SH7780_PCICR_PRST 0x00000002
#define SH7780_PCICR_CFIN 0x00000001
#define p4_in(addr) *((vu_long *)addr)
#define p4_out(data,addr) *(vu_long *)(addr) = (data)
#define p4_inw(addr) *((vu_short *)addr)
#define p4_outw(data,addr) *(vu_short *)(addr) = (data)
#define p4_in(addr) (*(vu_long *)addr)
#define p4_out(data, addr) (*(vu_long *)addr) = (data)
#define p4_inw(addr) (*(vu_short *)addr)
#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
@ -72,9 +73,9 @@ int pci_sh7780_init(struct pci_controller *hose)
p4_out(0x01, SH7780_PCIECR);
if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
printf("PCI: Unknown PCI host bridge.\n");
return;
return -1;
}
printf("PCI: SH7780 PCI host bridge found.\n");

2
drivers/serial/serial_sh.c
View File

@ -76,7 +76,7 @@
# define FIFOLEVEL_MASK 0xFF
# endif
#elif defined(CONFIG_CPU_SH7723)
# if defined(CONIFG_SCIF_A)
# if defined(CONFIG_SCIF_A)
# define SCLSR SCFSR
# define LSR_ORER 0x0200
# define FIFOLEVEL_MASK 0x3F

14
include/asm-sh/cache.h
View File

@ -3,29 +3,31 @@
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
int cache_control(unsigned int cmd);
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
void dcache_wback_range (u32 start, u32 end)
void dcache_wback_range(u32 start, u32 end)
{
u32 v;
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbwb %0": /* no output */
:"m" (__m (v)));
asm volatile ("ocbwb %0" : /* no output */
: "m" (__m(v)));
}
}
void dcache_invalid_range (u32 start, u32 end)
void dcache_invalid_range(u32 start, u32 end)
{
u32 v;
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbi %0": /* no output */
:"m" (__m (v)));
asm volatile ("ocbi %0" : /* no output */
: "m" (__m(v)));
}
}
#endif /* CONFIG_SH4 || CONFIG_SH4A */

107
include/asm-sh/io.h
View File

@ -34,9 +34,9 @@
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
@ -46,9 +46,9 @@ extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_writel(v, a) __arch_putl(v, a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
@ -59,13 +59,13 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
#define __raw_base_readb(base,off) __arch_base_getb(base,off)
#define __raw_base_readw(base,off) __arch_base_getw(base,off)
#define __raw_base_readl(base,off) __arch_base_getl(base,off)
#define __raw_base_readb(base, off) __arch_base_getb(base, off)
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
/*
* Now, pick up the machine-defined IO definitions
@ -91,36 +91,43 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#define outb(v,p) __raw_writeb(v, p)
#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
#define outb(v, p) __raw_writeb(v, p)
#define outw(v, p) __raw_writew(cpu_to_le16(v), p)
#define outl(v, p) __raw_writel(cpu_to_le32(v), p)
#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
#define outsb(p,d,l) __raw_writesb(p,d,l)
#define outsw(p,d,l) __raw_writesw(p,d,l)
#define outsl(p,d,l) __raw_writesl(p,d,l)
#define outsb(p, d, l) __raw_writesb(p, d, l)
#define outsw(p, d, l) __raw_writesw(p, d, l)
#define outsl(p, d, l) __raw_writesl(p, d, l)
#define insb(p,d,l) __raw_readsb(p,d,l)
#define insw(p,d,l) __raw_readsw(p,d,l)
#define insl(p,d,l) __raw_readsl(p,d,l)
#define insb(p, d, l) __raw_readsb(p, d, l)
#define insw(p, d, l) __raw_readsw(p, d, l)
#define insl(p, d, l) __raw_readsl(p, d, l)
#define outb_p(val,port) outb((val),(port))
#define outw_p(val,port) outw((val),(port))
#define outl_p(val,port) outl((val),(port))
#define outb_p(val, port) outb((val), (port))
#define outw_p(val, port) outw((val), (port))
#define outl_p(val, port) outl((val), (port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port,from,len) outsb(port,from,len)
#define outsw_p(port,from,len) outsw(port,from,len)
#define outsl_p(port,from,len) outsl(port,from,len)
#define insb_p(port,to,len) insb(port,to,len)
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)
#define outsb_p(port, from, len) outsb(port, from, len)
#define outsw_p(port, from, len) outsw(port, from, len)
#define outsl_p(port, from, len) outsl(port, from, len)
#define insb_p(port, to, len) insb(port, to, len)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
/* for U-Boot PCI */
#define out_8(port, val) outb(val, port)
#define out_le16(port, val) outw(val, port)
#define out_le32(port, val) outl(val, port)
#define in_8(port) inb(port)
#define in_le16(port) inw(port)
#define in_le32(port) inl(port)
/*
* ioremap and friends.
*
@ -128,7 +135,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
@ -139,20 +146,20 @@ extern void __iounmap(void *addr);
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off,sz,nocache) \
#define __arch_ioremap(off, sz, nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,0); \
_ret = __ioremap(iomem_to_phys(_off), _size, 0); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
#define ioremap(off,sz) __arch_ioremap((off),(sz),0)
#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1)
#define ioremap(off, sz) __arch_ioremap((off), (sz), 0)
#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1)
#define iounmap(_addr) __arch_iounmap(_addr)
/*
@ -180,19 +187,21 @@ extern void _memset_io(unsigned long, int, size_t);
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define readw(c)\
({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c)\
({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
#define eth_io_copy_and_sum(s,c,l,b) \
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
#define eth_io_copy_and_sum(s, c, l, b) \
eth_copy_and_sum((s), __mem_pci(c), (l), (b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
@ -216,11 +225,11 @@ out:
#define readb(addr) __raw_readb(addr)
#define readw(addr) __raw_readw(addr)
#define readl(addr) __raw_readl(addr)
#define writeb(v,addr) __raw_writeb(v, addr)
#define writew(v,addr) __raw_writew(v, addr)
#define writel(v,addr) __raw_writel(v, addr)
#define writeb(v, addr) __raw_writeb(v, addr)
#define writew(v, addr) __raw_writew(v, addr)
#define writel(v, addr) __raw_writel(v, addr)
#define check_signature(io,sig,len) (0)
#define check_signature(io, sig, len) (0)
#endif /* __mem_pci */

1
include/asm-sh/pci.h
View File

@ -36,6 +36,7 @@ int pci_sh7780_init(struct pci_controller *hose);
#error "Not support PCI."
#endif
int pci_sh4_init(struct pci_controller *hose);
/* PCI dword read for sh4 */
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value);

2
include/configs/FPS850L.h
View File

@ -211,6 +211,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/FPS860L.h
View File

@ -211,6 +211,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/HMI10.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this

17
include/configs/SM850.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -157,16 +157,21 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Hardware Information Block
*/

2
include/configs/TQM823L.h
View File

@ -225,6 +225,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM823M.h
View File

@ -221,6 +221,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM850L.h
View File

@ -210,6 +210,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM850M.h
View File

@ -210,6 +210,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM855L.h
View File

@ -215,6 +215,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM855M.h
View File

@ -250,6 +250,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM860L.h
View File

@ -214,6 +214,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

4
include/configs/TQM860M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -215,6 +215,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/TQM862L.h
View File

@ -218,6 +218,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

4
include/configs/TQM862M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -219,6 +219,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

4
include/configs/TQM866M.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2005
* (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -259,6 +259,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

2
include/configs/ads5121.h
View File

@ -421,7 +421,7 @@
#define CONFIG_HOSTNAME ads5121
#define CONFIG_BOOTFILE ads5121/uImage
#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx
#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */

2
include/configs/virtlab2.h
View File

@ -219,6 +219,8 @@
#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
/*-----------------------------------------------------------------------
* Dynamic MTD partition support
*/

115
lib_sh/board.c
View File

@ -23,6 +23,7 @@
#include <malloc.h>
#include <devices.h>
#include <version.h>
#include <watchdog.h>
#include <net.h>
#include <environment.h>
@ -30,7 +31,6 @@ extern void malloc_bin_reloc (void);
extern int cpu_init(void);
extern int board_init(void);
extern int dram_init(void);
extern int watchdog_init(void);
extern int timer_init(void);
const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
@ -41,17 +41,17 @@ static unsigned long mem_malloc_start;
static unsigned long mem_malloc_end;
static unsigned long mem_malloc_brk;
static void mem_malloc_init (void)
static void mem_malloc_init(void)
{
mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN);
mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16);
mem_malloc_brk = mem_malloc_start;
memset ((void *) mem_malloc_start, 0,
memset((void *) mem_malloc_start, 0,
(mem_malloc_end - mem_malloc_start));
}
void *sbrk (ptrdiff_t increment)
void *sbrk(ptrdiff_t increment)
{
unsigned long old = mem_malloc_brk;
unsigned long new = old + increment;
@ -70,37 +70,45 @@ static int sh_flash_init(void)
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_flashsize = flash_init();
printf("FLASH: %dMB\n", gd->bd->bi_flashsize / (1024*1024));
printf("FLASH: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
return 0;
}
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
static int sh_nand_init(void)
{
printf("NAND: ");
nand_init(); /* go init the NAND */
return 0;
}
# include <nand.h>
# define INIT_FUNC_NAND_INIT nand_init,
#else
# define INIT_FUNC_NAND_INIT
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_WATCHDOG)
extern int watchdog_init(void);
extern int watchdog_disable(void);
# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
# define WATCHDOG_DISABLE watchdog_disable
#else
# define INIT_FUNC_WATCHDOG_INIT
# define WATCHDOG_DISABLE
#endif /* CONFIG_WATCHDOG */
#if defined(CONFIG_CMD_IDE)
#include <ide.h>
static int sh_marubun_init(void)
{
puts ("IDE: ");
ide_init();
return 0;
}
#endif /* (CONFIG_CMD_IDE) */
# include <ide.h>
# define INIT_FUNC_IDE_INIT ide_init,
#else
# define INIT_FUNC_IDE_INIT
#endif /* CONFIG_CMD_IDE */
#if defined(CONFIG_PCI)
#include <pci.h>
static int sh_pci_init(void)
{
pci_init();
return 0;
}
# define INIT_FUNC_PCI_INIT sh_pci_init,
#else
# define INIT_FUNC_PCI_INIT
#endif /* CONFIG_PCI */
static int sh_mem_env_init(void)
@ -123,7 +131,8 @@ static int sh_net_init(void)
s = getenv("ethaddr");
for (i = 0; i < 6; ++i) {
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s) s = (*e) ? e + 1 : e;
if (s)
s = (*e) ? e + 1 : e;
}
return 0;
@ -136,24 +145,20 @@ init_fnc_t *init_sequence[] =
{
cpu_init, /* basic cpu dependent setup */
board_init, /* basic board dependent setup */
interrupt_init, /* set up exceptions */
interrupt_init, /* set up exceptions */
env_init, /* event init */
serial_init, /* SCIF init */
watchdog_init, /* watchdog init */
serial_init, /* SCIF init */
INIT_FUNC_WATCHDOG_INIT /* watchdog init */
console_init_f,
display_options,
checkcpu,
checkboard, /* Check support board */
dram_init, /* SDRAM init */
timer_init, /* SuperH Timer (TCNT0 only) init */
sh_flash_init, /* Flash memory(NOR) init*/
sh_flash_init, /* Flash memory(NOR) init*/
sh_mem_env_init,
#if defined(CONFIG_CMD_NAND)
sh_nand_init, /* Flash memory (NAND) init */
#endif
#if defined(CONFIG_PCI)
sh_pci_init, /* PCI Init */
#endif
INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
INIT_FUNC_PCI_INIT /* PCI init */
devices_init,
console_init_r,
interrupt_init,
@ -166,20 +171,18 @@ init_fnc_t *init_sequence[] =
NULL /* Terminate this list */
};
void sh_generic_init (void)
void sh_generic_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
int i;
char *s;
memset (gd, 0, CFG_GBL_DATA_SIZE);
memset(gd, 0, CFG_GBL_DATA_SIZE);
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->bd = (bd_t *)(gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
@ -189,35 +192,51 @@ void sh_generic_init (void)
bd->bi_memsize = CFG_SDRAM_SIZE;
bd->bi_flashstart = CFG_FLASH_BASE;
#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE)
bd->bi_sramstart= CFG_SRAM_BASE;
bd->bi_sramstart = CFG_SRAM_BASE;
bd->bi_sramsize = CFG_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr , i++) {
if ((*init_fnc_ptr) () != 0) {
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();
if ((*init_fnc_ptr) () != 0)
hang();
}
}
#if defined(CONFIG_CMD_NET)
puts ("Net: ");
eth_initialize(gd->bd);
#ifdef CONFIG_WATCHDOG
/* disable watchdog if environment is set */
{
char *s = getenv("watchdog");
if (s != NULL)
if (strncmp(s, "off", 3) == 0)
WATCHDOG_DISABLE();
}
#endif /* CONFIG_WATCHDOG*/
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
#if defined(CONFIG_CMD_NET)
{
char *s;
puts("Net: ");
eth_initialize(gd->bd);
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
}
#endif /* CONFIG_CMD_NET */
while (1) {
WATCHDOG_RESET();
main_loop();
}
}
/***********************************************************************/
void hang (void)
void hang(void)
{
puts ("Board ERROR\n");
for (;;);
puts("Board ERROR\n");
for (;;)
;
}

45
lib_sh/bootm.c
View File

@ -2,6 +2,9 @@
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (c) Copyright 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
* (c) Copyright 2008 Renesas Solutions Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -25,47 +28,37 @@
#include <command.h>
#include <asm/byteorder.h>
/* The SH kernel reads arguments from the empty zero page at location
* 0 at the start of SDRAM. The following are copied from
* arch/sh/kernel/setup.c and may require tweaking if the kernel sources
* change.
*/
#define PARAM ((unsigned char *)CFG_SDRAM_BASE + 0x1000)
#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
#define INITRD_START (*(unsigned long *) (PARAM+0x010))
#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
/* ... */
#define COMMAND_LINE ((char *) (PARAM+0x100))
#define RAMDISK_IMAGE_START_MASK 0x07FF
#ifdef CFG_DEBUG
static void hexdump (unsigned char *buf, int len)
static void hexdump(unsigned char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
if ((i % 16) == 0)
printf ("%s%08x: ", i ? "\n" : "", (unsigned int) &buf[i]);
printf ("%02x ", buf[i]);
printf("%s%08x: ", i ? "\n" : "",
(unsigned int)&buf[i]);
printf("%02x ", buf[i]);
}
printf ("\n");
printf("\n");
}
#endif
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
char *bootargs = getenv("bootargs");
/* Linux kernel load address */
void (*kernel) (void) = (void (*)(void))images->ep;
/* empty_zero_page */
unsigned char *param
= (unsigned char *)image_get_load(images->legacy_hdr_os);
/* Linux kernel command line */
char *cmdline = (char *)param + 0x100;
/* PAGE_SIZE */
unsigned long size = images->ep - (unsigned long)param;
char *bootargs = getenv("bootargs");
/* Setup parameters */
memset(PARAM, 0, 0x1000); /* Clear zero page */
strcpy(COMMAND_LINE, bootargs);
memset(param, 0, size); /* Clear zero page */
strcpy(cmdline, bootargs);
kernel();
/* does not return */